1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2009 3*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com> 4*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Header file for the Marvell's Feroceon CPU core. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _ASM_ARCH_KIRKWOOD_H 12*4882a593Smuzhiyun #define _ASM_ARCH_KIRKWOOD_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* SOC specific definations */ 17*4882a593Smuzhiyun #define INTREG_BASE 0xd0000000 18*4882a593Smuzhiyun #define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) 19*4882a593Smuzhiyun #define KW_OFFSET_REG (INTREG_BASE + 0x20080) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* undocumented registers */ 22*4882a593Smuzhiyun #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) 23*4882a593Smuzhiyun #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) 26*4882a593Smuzhiyun #define KW_TWSI_BASE (KW_REGISTER(0x11000)) 27*4882a593Smuzhiyun #define KW_UART0_BASE (KW_REGISTER(0x12000)) 28*4882a593Smuzhiyun #define KW_UART1_BASE (KW_REGISTER(0x12100)) 29*4882a593Smuzhiyun #define KW_MPP_BASE (KW_REGISTER(0x10000)) 30*4882a593Smuzhiyun #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) 31*4882a593Smuzhiyun #define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) 32*4882a593Smuzhiyun #define KW_RTC_BASE (KW_REGISTER(0x10300)) 33*4882a593Smuzhiyun #define KW_NANDF_BASE (KW_REGISTER(0x10418)) 34*4882a593Smuzhiyun #define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) 35*4882a593Smuzhiyun #define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) 36*4882a593Smuzhiyun #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) 37*4882a593Smuzhiyun #define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) 38*4882a593Smuzhiyun #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) 39*4882a593Smuzhiyun #define KW_USB20_BASE (KW_REGISTER(0x50000)) 40*4882a593Smuzhiyun #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) 41*4882a593Smuzhiyun #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) 42*4882a593Smuzhiyun #define KW_SATA_BASE (KW_REGISTER(0x80000)) 43*4882a593Smuzhiyun #define KW_SDIO_BASE (KW_REGISTER(0x90000)) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Kirkwood Sata controller has two ports */ 46*4882a593Smuzhiyun #define KW_SATA_PORT0_OFFSET 0x2000 47*4882a593Smuzhiyun #define KW_SATA_PORT1_OFFSET 0x4000 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Kirkwood GbE controller has two ports */ 50*4882a593Smuzhiyun #define MAX_MVGBE_DEVS 2 51*4882a593Smuzhiyun #define MVGBE0_BASE KW_EGIGA0_BASE 52*4882a593Smuzhiyun #define MVGBE1_BASE KW_EGIGA1_BASE 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Kirkwood USB Host controller */ 55*4882a593Smuzhiyun #define MVUSB0_BASE KW_USB20_BASE 56*4882a593Smuzhiyun #define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 57*4882a593Smuzhiyun #define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 58*4882a593Smuzhiyun #define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 59*4882a593Smuzhiyun #define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Kirkwood CPU memory windows */ 62*4882a593Smuzhiyun #define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA 63*4882a593Smuzhiyun #define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE 64*4882a593Smuzhiyun #define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #if defined (CONFIG_KW88F6281) 67*4882a593Smuzhiyun #include <asm/arch/kw88f6281.h> 68*4882a593Smuzhiyun #elif defined (CONFIG_KW88F6192) 69*4882a593Smuzhiyun #include <asm/arch/kw88f6192.h> 70*4882a593Smuzhiyun #else 71*4882a593Smuzhiyun #error "SOC Name not defined" 72*4882a593Smuzhiyun #endif /* CONFIG_KW88F6281 */ 73*4882a593Smuzhiyun #endif /* CONFIG_FEROCEON_88FR131 */ 74*4882a593Smuzhiyun #endif /* _ASM_ARCH_KIRKWOOD_H */ 75