1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2013,2014 Renesas Electronics Corporation 3*4882a593Smuzhiyun * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __EHCI_RMOBILE_H__ 9*4882a593Smuzhiyun #define __EHCI_RMOBILE_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Register offset */ 12*4882a593Smuzhiyun #define OHCI_OFFSET 0x00 13*4882a593Smuzhiyun #define OHCI_SIZE 0x1000 14*4882a593Smuzhiyun #define EHCI_OFFSET 0x1000 15*4882a593Smuzhiyun #define EHCI_SIZE 0x1000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define EHCI_USBCMD (EHCI_OFFSET + 0x0020) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* USBCTR */ 20*4882a593Smuzhiyun #define DIRPD (1 << 8) 21*4882a593Smuzhiyun #define PLL_RST (1 << 2) 22*4882a593Smuzhiyun #define PCICLK_MASK (1 << 1) 23*4882a593Smuzhiyun #define USBH_RST (1 << 0) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* CMND_STS */ 26*4882a593Smuzhiyun #define SERREN (1 << 8) 27*4882a593Smuzhiyun #define PERREN (1 << 6) 28*4882a593Smuzhiyun #define MASTEREN (1 << 2) 29*4882a593Smuzhiyun #define MEMEN (1 << 1) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* PCIAHB_WIN1_CTR and PCIAHB_WIN2_CTR */ 32*4882a593Smuzhiyun #define PCIAHB_WIN_PREFETCH ((1 << 1)|(1 << 0)) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* AHBPCI_WIN1_CTR */ 35*4882a593Smuzhiyun #define PCIWIN1_PCICMD ((1 << 3)|(1 << 1)) 36*4882a593Smuzhiyun #define AHB_CFG_AHBPCI 0x40000000 37*4882a593Smuzhiyun #define AHB_CFG_HOST 0x80000000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* AHBPCI_WIN2_CTR */ 40*4882a593Smuzhiyun #define PCIWIN2_PCICMD ((1 << 2)|(1 << 1)) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* PCI_INT_ENABLE */ 43*4882a593Smuzhiyun #define USBH_PMEEN (1 << 19) 44*4882a593Smuzhiyun #define USBH_INTBEN (1 << 17) 45*4882a593Smuzhiyun #define USBH_INTAEN (1 << 16) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* AHB_BUS_CTR */ 48*4882a593Smuzhiyun #define SMODE_READY_CTR (1 << 17) 49*4882a593Smuzhiyun #define SMODE_READ_BURST (1 << 16) 50*4882a593Smuzhiyun #define MMODE_HBUSREQ (1 << 7) 51*4882a593Smuzhiyun #define MMODE_BOUNDARY ((1 << 6)|(1 << 5)) 52*4882a593Smuzhiyun #define MMODE_BURST_WIDTH ((1 << 4)|(1 << 3)) 53*4882a593Smuzhiyun #define MMODE_SINGLE_MODE ((1 << 4)|(1 << 3)) 54*4882a593Smuzhiyun #define MMODE_WR_INCR (1 << 2) 55*4882a593Smuzhiyun #define MMODE_BYTE_BURST (1 << 1) 56*4882a593Smuzhiyun #define MMODE_HTRANS (1 << 0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* PCI_ARBITER_CTR */ 59*4882a593Smuzhiyun #define PCIBUS_PARK_TIMER 0x00FF0000 60*4882a593Smuzhiyun #define PCIBUS_PARK_TIMER_SET 0x00070000 61*4882a593Smuzhiyun #define PCIBP_MODE (1 << 12) 62*4882a593Smuzhiyun #define PCIREQ7 (1 << 7) 63*4882a593Smuzhiyun #define PCIREQ6 (1 << 6) 64*4882a593Smuzhiyun #define PCIREQ5 (1 << 5) 65*4882a593Smuzhiyun #define PCIREQ4 (1 << 4) 66*4882a593Smuzhiyun #define PCIREQ3 (1 << 3) 67*4882a593Smuzhiyun #define PCIREQ2 (1 << 2) 68*4882a593Smuzhiyun #define PCIREQ1 (1 << 1) 69*4882a593Smuzhiyun #define PCIREQ0 (1 << 0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define SMSTPCR7 0xE615014C 72*4882a593Smuzhiyun #define SMSTPCR703 (1 << 3) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Init AHB master and slave functions of the host logic */ 75*4882a593Smuzhiyun #define AHB_BUS_CTR_INIT \ 76*4882a593Smuzhiyun (SMODE_READY_CTR | MMODE_HBUSREQ | MMODE_WR_INCR | \ 77*4882a593Smuzhiyun MMODE_BYTE_BURST | MMODE_HTRANS) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #define USBCTR_WIN_SIZE_1GB 0x800 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* PCI Configuration Registers */ 82*4882a593Smuzhiyun #define PCI_CONF_OHCI_OFFSET 0x10000 83*4882a593Smuzhiyun #define PCI_CONF_EHCI_OFFSET 0x10100 84*4882a593Smuzhiyun struct ahb_pciconf { 85*4882a593Smuzhiyun u32 vid_did; 86*4882a593Smuzhiyun u32 cmnd_sts; 87*4882a593Smuzhiyun u32 rev; 88*4882a593Smuzhiyun u32 cache_line; 89*4882a593Smuzhiyun u32 basead; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* PCI Configuration Registers for AHB-PCI Bridge Registers */ 93*4882a593Smuzhiyun #define PCI_CONF_AHBPCI_OFFSET 0x10000 94*4882a593Smuzhiyun struct ahbconf_pci_bridge { 95*4882a593Smuzhiyun u32 vid_did; /* 0x00 */ 96*4882a593Smuzhiyun u32 cmnd_sts; 97*4882a593Smuzhiyun u32 revid_cc; 98*4882a593Smuzhiyun u32 cls_lt_ht_bist; 99*4882a593Smuzhiyun u32 basead; /* 0x10 */ 100*4882a593Smuzhiyun u32 win1_basead; 101*4882a593Smuzhiyun u32 win2_basead; 102*4882a593Smuzhiyun u32 dummy0[5]; 103*4882a593Smuzhiyun u32 ssvdi_ssid; /* 0x2C */ 104*4882a593Smuzhiyun u32 dummy1[4]; 105*4882a593Smuzhiyun u32 intr_line_pin; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* AHB-PCI Bridge PCI Communication Registers */ 109*4882a593Smuzhiyun #define AHBPCI_OFFSET 0x10800 110*4882a593Smuzhiyun struct ahbcom_pci_bridge { 111*4882a593Smuzhiyun u32 pciahb_win1_ctr; /* 0x00 */ 112*4882a593Smuzhiyun u32 pciahb_win2_ctr; 113*4882a593Smuzhiyun u32 pciahb_dct_ctr; 114*4882a593Smuzhiyun u32 dummy0; 115*4882a593Smuzhiyun u32 ahbpci_win1_ctr; /* 0x10 */ 116*4882a593Smuzhiyun u32 ahbpci_win2_ctr; 117*4882a593Smuzhiyun u32 dummy1; 118*4882a593Smuzhiyun u32 ahbpci_dct_ctr; 119*4882a593Smuzhiyun u32 pci_int_enable; /* 0x20 */ 120*4882a593Smuzhiyun u32 pci_int_status; 121*4882a593Smuzhiyun u32 dummy2[2]; 122*4882a593Smuzhiyun u32 ahb_bus_ctr; /* 0x30 */ 123*4882a593Smuzhiyun u32 usbctr; 124*4882a593Smuzhiyun u32 dummy3[2]; 125*4882a593Smuzhiyun u32 pci_arbiter_ctr; /* 0x40 */ 126*4882a593Smuzhiyun u32 dummy4; 127*4882a593Smuzhiyun u32 pci_unit_rev; /* 0x48 */ 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun struct rmobile_ehci_reg { 131*4882a593Smuzhiyun u32 hciversion; /* hciversion/caplength */ 132*4882a593Smuzhiyun u32 hcsparams; /* hcsparams */ 133*4882a593Smuzhiyun u32 hccparams; /* hccparams */ 134*4882a593Smuzhiyun u32 hcsp_portroute; /* hcsp_portroute */ 135*4882a593Smuzhiyun u32 usbcmd; /* usbcmd */ 136*4882a593Smuzhiyun u32 usbsts; /* usbsts */ 137*4882a593Smuzhiyun u32 usbintr; /* usbintr */ 138*4882a593Smuzhiyun u32 frindex; /* frindex */ 139*4882a593Smuzhiyun u32 ctrldssegment; /* ctrldssegment */ 140*4882a593Smuzhiyun u32 periodiclistbase; /* periodiclistbase */ 141*4882a593Smuzhiyun u32 asynclistaddr; /* asynclistaddr */ 142*4882a593Smuzhiyun u32 dummy[9]; 143*4882a593Smuzhiyun u32 configflag; /* configflag */ 144*4882a593Smuzhiyun u32 portsc; /* portsc */ 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* __EHCI_RMOBILE_H__ */ 148