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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h16 #define CCM_GPR0_OFFSET 0x0
17 #define CCM_OBSERVE0_OFFSET 0x0400
18 #define CCM_SCTRL0_OFFSET 0x0800
19 #define CCM_CCGR0_OFFSET 0x4000
20 #define CCM_ROOT0_TARGET_OFFSET 0x8000
59 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
61 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
66 uint32_t ctrl_24m; /* offset 0x0000 */
70 uint32_t rcosc_config0; /* offset 0x0010 */
74 uint32_t rcosc_config1; /* offset 0x0020 */
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dcavium-mdio.txt15 - #size-cells: Must be <0>. MDIO addresses have no size component.
23 #size-cells = <0>;
24 reg = <0x11800 0x00001800 0x0 0x40>;
26 ethernet-phy@0 {
28 reg = <0>;
58 reg = <0x0b00 0 0 0 0>; /* DEVFN = 0x0b (1:3) */
59 assigned-addresses = <0x03000000 0x87e0 0x05000000 0x0 0x800000>;
60 ranges = <0x87e0 0x05000000 0x03000000 0x87e0 0x05000000 0x0 0x800000>;
65 #size-cells = <0>;
66 reg = <0x87e0 0x05003800 0x0 0x30>;
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-s3c/
H A Dvr1000.h14 #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
28 #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
32 #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
33 #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
35 #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
36 #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
38 #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
39 #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
41 #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
42 #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
[all …]
H A Dbast.h16 #define BAST_CPLD_CTRL1_LRCOFF (0x00)
17 #define BAST_CPLD_CTRL1_LRCADC (0x01)
18 #define BAST_CPLD_CTRL1_LRCDAC (0x02)
19 #define BAST_CPLD_CTRL1_LRCARM (0x03)
20 #define BAST_CPLD_CTRL1_LRMASK (0x03)
24 #define BAST_CPLD_CTRL2_WNAND (0x04)
25 #define BAST_CPLD_CTLR2_IDERST (0x08)
29 #define BAST_CPLD_CTRL3_IDMASK (0x0e)
30 #define BAST_CPLD_CTRL3_ROMWEN (0x01)
34 #define BAST_CPLD_CTRL4_LLAT (0x01)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/ethernet/ibm/emac/
H A Dtah.h52 #define TAH_MR_CVR 0x80000000
53 #define TAH_MR_SR 0x40000000
54 #define TAH_MR_ST_256 0x01000000
55 #define TAH_MR_ST_512 0x02000000
56 #define TAH_MR_ST_768 0x03000000
57 #define TAH_MR_ST_1024 0x04000000
58 #define TAH_MR_ST_1280 0x05000000
59 #define TAH_MR_ST_1536 0x06000000
60 #define TAH_MR_TFS_16KB 0x00000000
61 #define TAH_MR_TFS_2KB 0x00200000
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dexynos-srom.yaml33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
50 typically 0 as this is the start of the bank.
74 Tacp: Page mode access cycle at Page mode (0 - 15)
75 Tcah: Address holding time after CSn (0 - 15)
76 Tcoh: Chip selection hold on OEn (0 - 15)
77 Tacc: Access cycle (0 - 31, the actual time is N + 1)
78 Tcos: Chip selection set-up before OEn (0 - 15)
79 Tacs: Address set-up before CSn (0 - 15)
96 reg = <0x12560000 0x14>;
[all …]
/OK3568_Linux_fs/u-boot/arch/powerpc/include/asm/
H A Dcache.h67 #define CACHECRBA 0x80000823 /* Cache configuration register address */
68 #define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
69 #define L2CACHE_512KB 0x00 /* 512KB */
70 #define L2CACHE_256KB 0x01 /* 256KB */
71 #define L2CACHE_1MB 0x02 /* 1MB */
72 #define L2CACHE_NONE 0x03 /* NONE */
73 #define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
88 #define IDC_ENABLE 0x02000000 /* Cache enable */
89 #define IDC_DISABLE 0x04000000 /* Cache disable */
90 #define IDC_LDLCK 0x06000000 /* Load and lock */
[all …]
/OK3568_Linux_fs/kernel/arch/sh/include/mach-common/mach/
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/OK3568_Linux_fs/kernel/arch/arm/include/asm/
H A Delf.h25 #define EF_ARM_EABI_MASK 0xff000000
26 #define EF_ARM_EABI_UNKNOWN 0x00000000
27 #define EF_ARM_EABI_VER1 0x01000000
28 #define EF_ARM_EABI_VER2 0x02000000
29 #define EF_ARM_EABI_VER3 0x03000000
30 #define EF_ARM_EABI_VER4 0x04000000
31 #define EF_ARM_EABI_VER5 0x05000000
33 #define EF_ARM_BE8 0x00800000 /* ABI 4,5 */
34 #define EF_ARM_LE8 0x00400000 /* ABI 4,5 */
35 #define EF_ARM_MAVERICK_FLOAT 0x00000800 /* ABI 0 */
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/visconti/
H A Dpinctrl-tmpv7700.c15 #define tmpv7700_MAGIC_NUM 0x4932f70e
18 #define REG_KEY_CTRL 0x0000
19 #define REG_KEY_CMD 0x0004
20 #define REG_PINMUX1 0x3000
21 #define REG_PINMUX2 0x3004
22 #define REG_PINMUX3 0x3008
23 #define REG_PINMUX4 0x300c
24 #define REG_PINMUX5 0x3010
25 #define REG_IOSET 0x3014
26 #define REG_IO_VSEL 0x3018
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dgen7_renderstate.c29 0x0000000c,
30 0x00000010,
31 0x00000018,
32 0x000001ec,
37 0x69040000,
38 0x61010008,
39 0x00000000,
40 0x00000001, /* reloc */
41 0x00000001, /* reloc */
42 0x00000000,
[all …]
H A Dgen6_renderstate.c29 0x00000020,
30 0x00000024,
31 0x0000002c,
32 0x000001e0,
33 0x000001e4,
38 0x69040000,
39 0x790d0001,
40 0x00000000,
41 0x00000000,
42 0x78180000,
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
32 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
33 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
34 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
49 #define GICD_BASE 0x06000000
50 #define GICR_BASE 0x06100000
53 #define SMMU_BASE 0x05000000 /* GR0 Base */
70 #define CCI_MN_BASE 0x04000000
[all …]
/OK3568_Linux_fs/kernel/arch/sh/boards/
H A Dboard-urquell.c32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dsym53c8xx.h15 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
17 #define SCNTL1 0x01 /* no reset */
18 #define ISCON 0x10 /* connected to scsi */
19 #define CRST 0x08 /* force reset */
20 #define IARB 0x02 /* immediate arbitration */
22 #define SCNTL2 0x02 /* no disconnect expected */
23 #define SDU 0x80 /* cmd: disconnect will raise error */
24 #define CHM 0x40 /* sta: chained mode */
25 #define WSS 0x08 /* sta: wide scsi send [W]*/
26 #define WSR 0x01 /* sta: wide scsi received [W]*/
[all …]
/OK3568_Linux_fs/buildroot/dl/qt5location/git/src/3rdparty/mapbox-gl-native/deps/boost/1.65.1/include/boost/config/stdlib/
H A Droguewave.hpp25 # define BOOST_RWSTD_VER 0x010000
26 #elif _RWSTD_VER < 0x010000
34 #elif _RWSTD_VER < 0x04010200
45 // Prior to version 2.2.0 the primary template for std::numeric_limits
49 #if BOOST_RWSTD_VER < 0x020200
55 #if BOOST_RWSTD_VER <= 0x020101 && (!defined(__SUNPRO_CC) || (__SUNPRO_CC < 0x550))
69 …LE_DEFAULT_TEMPLATES) || defined(RWSTD_NO_SIMPLE_DEFAULT_TEMPLATES) || (BOOST_RWSTD_VER < 0x020000)
84 #if (BOOST_RWSTD_VER < 0x020000)
119 #if (BOOST_RWSTD_VER < 0x020000) || defined(_RWSTD_NO_CLASS_PARTIAL_SPEC)
127 #if BOOST_RWSTD_VER < 0x020100
[all …]
/OK3568_Linux_fs/u-boot/board/espt/
H A Dlowlevel_init.S169 PACR_A: .long 0xFFEF0000
170 PBCR_A: .long 0xFFEF0002
171 PCCR_A: .long 0xFFEF0004
172 PDCR_A: .long 0xFFEF0006
173 PECR_A: .long 0xFFEF0008
174 PFCR_A: .long 0xFFEF000A
175 PGCR_A: .long 0xFFEF000C
176 PHCR_A: .long 0xFFEF000E
177 PICR_A: .long 0xFFEF0010
178 PJCR_A: .long 0xFFEF0012
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/ti/
H A Dk3-udma.yaml53 for source thread IDs (rx): 0 - 0x7fff
54 for destination thread IDs (tx): 0x8000 - 0xffff
158 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
164 reg = <0x0 0x31150000 0x0 0x100>,
165 <0x0 0x34000000 0x0 0x100000>,
166 <0x0 0x35000000 0x0 0x100000>;
177 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
178 <0x2>; /* TX_CHAN */
179 ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
180 <0x5>; /* RX_CHAN */
[all …]
/OK3568_Linux_fs/kernel/drivers/edac/
H A Dfsl_ddr_edac.c65 return sprintf(data, "0x%08x", in fsl_mc_inject_data_hi_show()
75 return sprintf(data, "0x%08x", in fsl_mc_inject_data_lo_show()
85 return sprintf(data, "0x%08x", in fsl_mc_inject_ctrl_show()
99 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_hi_store()
106 return 0; in fsl_mc_inject_data_hi_store()
119 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_data_lo_store()
126 return 0; in fsl_mc_inject_data_lo_store()
139 rc = kstrtoul(data, 0, &val); in fsl_mc_inject_ctrl_store()
146 return 0; in fsl_mc_inject_ctrl_store()
178 /* [0:31] [32:63] */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dtable.c7 0x800, 0x8020D010,
8 0x804, 0x080112E0,
9 0x808, 0x0E028233,
10 0x80C, 0x12131113,
11 0x810, 0x20101263,
12 0x814, 0x020C3D10,
13 0x818, 0x03A00385,
14 0x820, 0x00000000,
15 0x824, 0x00030FE0,
16 0x828, 0x00000000,
[all …]
/OK3568_Linux_fs/kernel/arch/arm/vdso/
H A Dvdsomunge.c49 ((((x) & 0x00ff) << 8) | \
50 (((x) & 0xff00) >> 8))
53 ((((x) & 0x000000ff) << 24) | \
54 (((x) & 0x0000ff00) << 8) | \
55 (((x) & 0x00ff0000) >> 8) | \
56 (((x) & 0xff000000) >> 24))
68 #define EF_ARM_EABI_VER5 0x05000000
72 #define EF_ARM_ABI_FLOAT_SOFT 0x200
76 #define EF_ARM_ABI_FLOAT_HARD 0x400
130 argv0 = argv[0]; in main()
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dpxa3xx-gcu.c40 #define REG_GCCR 0x00
46 #define REG_GCISCR 0x04
47 #define REG_GCIECR 0x08
48 #define REG_GCRBBR 0x20
49 #define REG_GCRBLR 0x24
50 #define REG_GCRBHR 0x28
51 #define REG_GCRBTR 0x2C
52 #define REG_GCRBEXHR 0x30
54 #define IE_EOB (1 << 0)
56 #define IE_ALL 0xff
[all …]
H A Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
[all …]
/OK3568_Linux_fs/kernel/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]

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