Lines Matching +full:0 +full:x05000000
13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
32 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
33 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
34 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
49 #define GICD_BASE 0x06000000
50 #define GICR_BASE 0x06100000
53 #define SMMU_BASE 0x05000000 /* GR0 Base */
70 #define CCI_MN_BASE 0x04000000
71 #define CCI_MN_RNF_NODEID_LIST 0x180
72 #define CCI_MN_DVM_DOMAIN_CTL 0x200
73 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
75 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
76 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
77 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
78 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
79 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
80 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
82 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
83 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
84 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
85 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
86 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
87 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
89 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
90 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
91 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
93 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
96 #define TZPC_BASE 0x02200000
98 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
99 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
100 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
101 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
102 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
103 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
104 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
105 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
106 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
108 #define DCSR_CGACRE5 0x700070914ULL
109 #define EPU_EPCMPR5 0x700060914ULL
110 #define EPU_EPCCR5 0x700060814ULL
111 #define EPU_EPSMCR5 0x700060228ULL
112 #define EPU_EPECR5 0x700060314ULL
113 #define EPU_EPCTR5 0x700060a14ULL
114 #define EPU_EPGCR 0x700060000ULL
120 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
121 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
122 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
124 #define DCSR_DCFG_SBEESR2 0x20140534
125 #define DCSR_DCFG_MBEESR2 0x20140544
144 #define QE_MURAM_SIZE 0x6000UL
156 #define SMMU_BASE 0x09000000
159 #define GICD_BASE 0x01401000
160 #define GICC_BASE 0x01402000
161 #define GICH_BASE 0x01404000
162 #define GICV_BASE 0x01406000
163 #define GICD_SIZE 0x1000
164 #define GICC_SIZE 0x2000
165 #define GICH_SIZE 0x2000
166 #define GICV_SIZE 0x2000
168 #define GICD_BASE_64K 0x01410000
169 #define GICC_BASE_64K 0x01420000
170 #define GICH_BASE_64K 0x01440000
171 #define GICV_BASE_64K 0x01460000
172 #define GICD_SIZE_64K 0x10000
173 #define GICC_SIZE_64K 0x20000
174 #define GICH_SIZE_64K 0x20000
175 #define GICV_SIZE_64K 0x20000
178 #define DCFG_CCSR_SVR 0x1ee00a4
179 #define REV1_0 0x10
180 #define REV1_1 0x11
182 #define SCFG_GIC400_ALIGN 0x1570188
187 #define GICD_BASE 0x01401000
188 #define GICC_BASE 0x01402000
214 #define SMMU_BASE 0x09000000
217 #define GICD_BASE 0x01410000
218 #define GICC_BASE 0x01420000