1*4882a593Smuzhiyun /************************************************************************** 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas. 4*4882a593Smuzhiyun All Rights Reserved. 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun Permission is hereby granted, free of charge, to any person obtaining a 7*4882a593Smuzhiyun copy of this software and associated documentation files (the 8*4882a593Smuzhiyun "Software"), to deal in the Software without restriction, including 9*4882a593Smuzhiyun without limitation the rights to use, copy, modify, merge, publish, 10*4882a593Smuzhiyun distribute, sub license, and/or sell copies of the Software, and to 11*4882a593Smuzhiyun permit persons to whom the Software is furnished to do so, subject to 12*4882a593Smuzhiyun the following conditions: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun The above copyright notice and this permission notice (including the 15*4882a593Smuzhiyun next paragraph) shall be included in all copies or substantial portions 16*4882a593Smuzhiyun of the Software. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19*4882a593Smuzhiyun OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20*4882a593Smuzhiyun MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21*4882a593Smuzhiyun IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 22*4882a593Smuzhiyun ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23*4882a593Smuzhiyun TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24*4882a593Smuzhiyun SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun **************************************************************************/ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* 29*4882a593Smuzhiyun * Authors: 30*4882a593Smuzhiyun * Kevin E. Martin <kevin@precisioninsight.com> 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* I/O register offsets */ 34*4882a593Smuzhiyun #define SRX VGA_SEQ_I 35*4882a593Smuzhiyun #define GRX VGA_GFX_I 36*4882a593Smuzhiyun #define ARX VGA_ATT_IW 37*4882a593Smuzhiyun #define XRX 0x3D6 38*4882a593Smuzhiyun #define MRX 0x3D2 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* VGA Color Palette Registers */ 41*4882a593Smuzhiyun #define DACMASK 0x3C6 42*4882a593Smuzhiyun #define DACSTATE 0x3C7 43*4882a593Smuzhiyun #define DACRX 0x3C7 44*4882a593Smuzhiyun #define DACWX 0x3C8 45*4882a593Smuzhiyun #define DACDATA 0x3C9 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* CRT Controller Registers (CRX) */ 48*4882a593Smuzhiyun #define START_ADDR_HI 0x0C 49*4882a593Smuzhiyun #define START_ADDR_LO 0x0D 50*4882a593Smuzhiyun #define VERT_SYNC_END 0x11 51*4882a593Smuzhiyun #define EXT_VERT_TOTAL 0x30 52*4882a593Smuzhiyun #define EXT_VERT_DISPLAY 0x31 53*4882a593Smuzhiyun #define EXT_VERT_SYNC_START 0x32 54*4882a593Smuzhiyun #define EXT_VERT_BLANK_START 0x33 55*4882a593Smuzhiyun #define EXT_HORIZ_TOTAL 0x35 56*4882a593Smuzhiyun #define EXT_HORIZ_BLANK 0x39 57*4882a593Smuzhiyun #define EXT_START_ADDR 0x40 58*4882a593Smuzhiyun #define EXT_START_ADDR_ENABLE 0x80 59*4882a593Smuzhiyun #define EXT_OFFSET 0x41 60*4882a593Smuzhiyun #define EXT_START_ADDR_HI 0x42 61*4882a593Smuzhiyun #define INTERLACE_CNTL 0x70 62*4882a593Smuzhiyun #define INTERLACE_ENABLE 0x80 63*4882a593Smuzhiyun #define INTERLACE_DISABLE 0x00 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Miscellaneous Output Register */ 66*4882a593Smuzhiyun #define MSR_R 0x3CC 67*4882a593Smuzhiyun #define MSR_W 0x3C2 68*4882a593Smuzhiyun #define IO_ADDR_SELECT 0x01 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define MDA_BASE 0x3B0 71*4882a593Smuzhiyun #define CGA_BASE 0x3D0 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* System Configuration Extension Registers (XRX) */ 74*4882a593Smuzhiyun #define IO_CTNL 0x09 75*4882a593Smuzhiyun #define EXTENDED_ATTR_CNTL 0x02 76*4882a593Smuzhiyun #define EXTENDED_CRTC_CNTL 0x01 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define ADDRESS_MAPPING 0x0A 79*4882a593Smuzhiyun #define PACKED_MODE_ENABLE 0x04 80*4882a593Smuzhiyun #define LINEAR_MODE_ENABLE 0x02 81*4882a593Smuzhiyun #define PAGE_MAPPING_ENABLE 0x01 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define BITBLT_CNTL 0x20 84*4882a593Smuzhiyun #define COLEXP_MODE 0x30 85*4882a593Smuzhiyun #define COLEXP_8BPP 0x00 86*4882a593Smuzhiyun #define COLEXP_16BPP 0x10 87*4882a593Smuzhiyun #define COLEXP_24BPP 0x20 88*4882a593Smuzhiyun #define COLEXP_RESERVED 0x30 89*4882a593Smuzhiyun #define CHIP_RESET 0x02 90*4882a593Smuzhiyun #define BITBLT_STATUS 0x01 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define DISPLAY_CNTL 0x40 93*4882a593Smuzhiyun #define VGA_WRAP_MODE 0x02 94*4882a593Smuzhiyun #define VGA_WRAP_AT_256KB 0x00 95*4882a593Smuzhiyun #define VGA_NO_WRAP 0x02 96*4882a593Smuzhiyun #define GUI_MODE 0x01 97*4882a593Smuzhiyun #define STANDARD_VGA_MODE 0x00 98*4882a593Smuzhiyun #define HIRES_MODE 0x01 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define DRAM_ROW_TYPE 0x50 101*4882a593Smuzhiyun #define DRAM_ROW_0 0x07 102*4882a593Smuzhiyun #define DRAM_ROW_0_SDRAM 0x00 103*4882a593Smuzhiyun #define DRAM_ROW_0_EMPTY 0x07 104*4882a593Smuzhiyun #define DRAM_ROW_1 0x38 105*4882a593Smuzhiyun #define DRAM_ROW_1_SDRAM 0x00 106*4882a593Smuzhiyun #define DRAM_ROW_1_EMPTY 0x38 107*4882a593Smuzhiyun #define DRAM_ROW_CNTL_LO 0x51 108*4882a593Smuzhiyun #define DRAM_CAS_LATENCY 0x10 109*4882a593Smuzhiyun #define DRAM_RAS_TIMING 0x08 110*4882a593Smuzhiyun #define DRAM_RAS_PRECHARGE 0x04 111*4882a593Smuzhiyun #define DRAM_ROW_CNTL_HI 0x52 112*4882a593Smuzhiyun #define DRAM_EXT_CNTL 0x53 113*4882a593Smuzhiyun #define DRAM_REFRESH_RATE 0x03 114*4882a593Smuzhiyun #define DRAM_REFRESH_DISABLE 0x00 115*4882a593Smuzhiyun #define DRAM_REFRESH_60HZ 0x01 116*4882a593Smuzhiyun #define DRAM_REFRESH_FAST_TEST 0x02 117*4882a593Smuzhiyun #define DRAM_REFRESH_RESERVED 0x03 118*4882a593Smuzhiyun #define DRAM_TIMING 0x54 119*4882a593Smuzhiyun #define DRAM_ROW_BNDRY_0 0x55 120*4882a593Smuzhiyun #define DRAM_ROW_BNDRY_1 0x56 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define DPMS_SYNC_SELECT 0x61 123*4882a593Smuzhiyun #define VSYNC_CNTL 0x08 124*4882a593Smuzhiyun #define VSYNC_ON 0x00 125*4882a593Smuzhiyun #define VSYNC_OFF 0x08 126*4882a593Smuzhiyun #define HSYNC_CNTL 0x02 127*4882a593Smuzhiyun #define HSYNC_ON 0x00 128*4882a593Smuzhiyun #define HSYNC_OFF 0x02 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define PIXPIPE_CONFIG_0 0x80 131*4882a593Smuzhiyun #define DAC_8_BIT 0x80 132*4882a593Smuzhiyun #define DAC_6_BIT 0x00 133*4882a593Smuzhiyun #define HW_CURSOR_ENABLE 0x10 134*4882a593Smuzhiyun #define EXTENDED_PALETTE 0x01 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define PIXPIPE_CONFIG_1 0x81 137*4882a593Smuzhiyun #define DISPLAY_COLOR_MODE 0x0F 138*4882a593Smuzhiyun #define DISPLAY_VGA_MODE 0x00 139*4882a593Smuzhiyun #define DISPLAY_8BPP_MODE 0x02 140*4882a593Smuzhiyun #define DISPLAY_15BPP_MODE 0x04 141*4882a593Smuzhiyun #define DISPLAY_16BPP_MODE 0x05 142*4882a593Smuzhiyun #define DISPLAY_24BPP_MODE 0x06 143*4882a593Smuzhiyun #define DISPLAY_32BPP_MODE 0x07 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define PIXPIPE_CONFIG_2 0x82 146*4882a593Smuzhiyun #define DISPLAY_GAMMA_ENABLE 0x08 147*4882a593Smuzhiyun #define DISPLAY_GAMMA_DISABLE 0x00 148*4882a593Smuzhiyun #define OVERLAY_GAMMA_ENABLE 0x04 149*4882a593Smuzhiyun #define OVERLAY_GAMMA_DISABLE 0x00 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define CURSOR_CONTROL 0xA0 152*4882a593Smuzhiyun #define CURSOR_ORIGIN_SCREEN 0x00 153*4882a593Smuzhiyun #define CURSOR_ORIGIN_DISPLAY 0x10 154*4882a593Smuzhiyun #define CURSOR_MODE 0x07 155*4882a593Smuzhiyun #define CURSOR_MODE_DISABLE 0x00 156*4882a593Smuzhiyun #define CURSOR_MODE_32_4C_AX 0x01 157*4882a593Smuzhiyun #define CURSOR_MODE_128_2C 0x02 158*4882a593Smuzhiyun #define CURSOR_MODE_128_1C 0x03 159*4882a593Smuzhiyun #define CURSOR_MODE_64_3C 0x04 160*4882a593Smuzhiyun #define CURSOR_MODE_64_4C_AX 0x05 161*4882a593Smuzhiyun #define CURSOR_MODE_64_4C 0x06 162*4882a593Smuzhiyun #define CURSOR_MODE_RESERVED 0x07 163*4882a593Smuzhiyun #define CURSOR_BASEADDR_LO 0xA2 164*4882a593Smuzhiyun #define CURSOR_BASEADDR_HI 0xA3 165*4882a593Smuzhiyun #define CURSOR_X_LO 0xA4 166*4882a593Smuzhiyun #define CURSOR_X_HI 0xA5 167*4882a593Smuzhiyun #define CURSOR_X_POS 0x00 168*4882a593Smuzhiyun #define CURSOR_X_NEG 0x80 169*4882a593Smuzhiyun #define CURSOR_Y_LO 0xA6 170*4882a593Smuzhiyun #define CURSOR_Y_HI 0xA7 171*4882a593Smuzhiyun #define CURSOR_Y_POS 0x00 172*4882a593Smuzhiyun #define CURSOR_Y_NEG 0x80 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define VCLK2_VCO_M 0xC8 175*4882a593Smuzhiyun #define VCLK2_VCO_N 0xC9 176*4882a593Smuzhiyun #define VCLK2_VCO_MN_MSBS 0xCA 177*4882a593Smuzhiyun #define VCO_N_MSBS 0x30 178*4882a593Smuzhiyun #define VCO_M_MSBS 0x03 179*4882a593Smuzhiyun #define VCLK2_VCO_DIV_SEL 0xCB 180*4882a593Smuzhiyun #define POST_DIV_SELECT 0x70 181*4882a593Smuzhiyun #define POST_DIV_1 0x00 182*4882a593Smuzhiyun #define POST_DIV_2 0x10 183*4882a593Smuzhiyun #define POST_DIV_4 0x20 184*4882a593Smuzhiyun #define POST_DIV_8 0x30 185*4882a593Smuzhiyun #define POST_DIV_16 0x40 186*4882a593Smuzhiyun #define POST_DIV_32 0x50 187*4882a593Smuzhiyun #define VCO_LOOP_DIV_BY_4M 0x00 188*4882a593Smuzhiyun #define VCO_LOOP_DIV_BY_16M 0x04 189*4882a593Smuzhiyun #define REF_CLK_DIV_BY_5 0x02 190*4882a593Smuzhiyun #define REF_DIV_4 0x00 191*4882a593Smuzhiyun #define REF_DIV_1 0x01 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define PLL_CNTL 0xCE 194*4882a593Smuzhiyun #define PLL_MEMCLK_SEL 0x03 195*4882a593Smuzhiyun #define PLL_MEMCLK__66667KHZ 0x00 196*4882a593Smuzhiyun #define PLL_MEMCLK__75000KHZ 0x01 197*4882a593Smuzhiyun #define PLL_MEMCLK__88889KHZ 0x02 198*4882a593Smuzhiyun #define PLL_MEMCLK_100000KHZ 0x03 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* Multimedia Extension Registers (MRX) */ 201*4882a593Smuzhiyun #define ACQ_CNTL_1 0x02 202*4882a593Smuzhiyun #define ACQ_CNTL_2 0x03 203*4882a593Smuzhiyun #define FRAME_CAP_MODE 0x01 204*4882a593Smuzhiyun #define CONT_CAP_MODE 0x00 205*4882a593Smuzhiyun #define SINGLE_CAP_MODE 0x01 206*4882a593Smuzhiyun #define ACQ_CNTL_3 0x04 207*4882a593Smuzhiyun #define COL_KEY_CNTL_1 0x3C 208*4882a593Smuzhiyun #define BLANK_DISP_OVERLAY 0x20 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* FIFOs */ 211*4882a593Smuzhiyun #define LP_FIFO 0x1000 212*4882a593Smuzhiyun #define HP_FIFO 0x2000 213*4882a593Smuzhiyun #define INSTPNT 0x3040 214*4882a593Smuzhiyun #define LP_FIFO_COUNT 0x3040 215*4882a593Smuzhiyun #define HP_FIFO_COUNT 0x3041 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* FIFO Commands */ 218*4882a593Smuzhiyun #define CLIENT 0xE0000000 219*4882a593Smuzhiyun #define CLIENT_2D 0x60000000 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun /* Command Parser Mode Register */ 222*4882a593Smuzhiyun #define COMPARS 0x3038 223*4882a593Smuzhiyun #define TWO_D_INST_DISABLE 0x08 224*4882a593Smuzhiyun #define THREE_D_INST_DISABLE 0x04 225*4882a593Smuzhiyun #define STATE_VAR_UPDATE_DISABLE 0x02 226*4882a593Smuzhiyun #define PAL_STIP_DISABLE 0x01 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* Interrupt Control Registers */ 229*4882a593Smuzhiyun #define IER 0x3030 230*4882a593Smuzhiyun #define IIR 0x3032 231*4882a593Smuzhiyun #define IMR 0x3034 232*4882a593Smuzhiyun #define ISR 0x3036 233*4882a593Smuzhiyun #define VMIINTB_EVENT 0x2000 234*4882a593Smuzhiyun #define GPIO4_INT 0x1000 235*4882a593Smuzhiyun #define DISP_FLIP_EVENT 0x0800 236*4882a593Smuzhiyun #define DVD_PORT_DMA 0x0400 237*4882a593Smuzhiyun #define DISP_VBLANK 0x0200 238*4882a593Smuzhiyun #define FIFO_EMPTY_DMA_DONE 0x0100 239*4882a593Smuzhiyun #define INST_PARSER_ERROR 0x0080 240*4882a593Smuzhiyun #define USER_DEFINED 0x0040 241*4882a593Smuzhiyun #define BREAKPOINT 0x0020 242*4882a593Smuzhiyun #define DISP_HORIZ_COUNT 0x0010 243*4882a593Smuzhiyun #define DISP_VSYNC 0x0008 244*4882a593Smuzhiyun #define CAPTURE_HORIZ_COUNT 0x0004 245*4882a593Smuzhiyun #define CAPTURE_VSYNC 0x0002 246*4882a593Smuzhiyun #define THREE_D_PIPE_FLUSHED 0x0001 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun /* FIFO Watermark and Burst Length Control Register */ 249*4882a593Smuzhiyun #define FWATER_BLC 0x00006000 250*4882a593Smuzhiyun #define LMI_BURST_LENGTH 0x7F000000 251*4882a593Smuzhiyun #define LMI_FIFO_WATERMARK 0x003F0000 252*4882a593Smuzhiyun #define AGP_BURST_LENGTH 0x00007F00 253*4882a593Smuzhiyun #define AGP_FIFO_WATERMARK 0x0000003F 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* BitBLT Registers */ 256*4882a593Smuzhiyun #define SRC_DST_PITCH 0x00040000 257*4882a593Smuzhiyun #define DST_PITCH 0x1FFF0000 258*4882a593Smuzhiyun #define SRC_PITCH 0x00001FFF 259*4882a593Smuzhiyun #define COLEXP_BG_COLOR 0x00040004 260*4882a593Smuzhiyun #define COLEXP_FG_COLOR 0x00040008 261*4882a593Smuzhiyun #define MONO_SRC_CNTL 0x0004000C 262*4882a593Smuzhiyun #define MONO_USE_COLEXP 0x00000000 263*4882a593Smuzhiyun #define MONO_USE_SRCEXP 0x08000000 264*4882a593Smuzhiyun #define MONO_DATA_ALIGN 0x07000000 265*4882a593Smuzhiyun #define MONO_BIT_ALIGN 0x01000000 266*4882a593Smuzhiyun #define MONO_BYTE_ALIGN 0x02000000 267*4882a593Smuzhiyun #define MONO_WORD_ALIGN 0x03000000 268*4882a593Smuzhiyun #define MONO_DWORD_ALIGN 0x04000000 269*4882a593Smuzhiyun #define MONO_QWORD_ALIGN 0x05000000 270*4882a593Smuzhiyun #define MONO_SRC_INIT_DSCRD 0x003F0000 271*4882a593Smuzhiyun #define MONO_SRC_RIGHT_CLIP 0x00003F00 272*4882a593Smuzhiyun #define MONO_SRC_LEFT_CLIP 0x0000003F 273*4882a593Smuzhiyun #define BITBLT_CONTROL 0x00040010 274*4882a593Smuzhiyun #define BLTR_STATUS 0x80000000 275*4882a593Smuzhiyun #define DYN_DEPTH 0x03000000 276*4882a593Smuzhiyun #define DYN_DEPTH_8BPP 0x00000000 277*4882a593Smuzhiyun #define DYN_DEPTH_16BPP 0x01000000 278*4882a593Smuzhiyun #define DYN_DEPTH_24BPP 0x02000000 279*4882a593Smuzhiyun #define DYN_DEPTH_32BPP 0x03000000 /* Unimplemented on the i740 */ 280*4882a593Smuzhiyun #define DYN_DEPTH_ENABLE 0x00800000 281*4882a593Smuzhiyun #define PAT_VERT_ALIGN 0x00700000 282*4882a593Smuzhiyun #define SOLID_PAT_SELECT 0x00080000 283*4882a593Smuzhiyun #define PAT_IS_IN_COLOR 0x00000000 284*4882a593Smuzhiyun #define PAT_IS_MONO 0x00040000 285*4882a593Smuzhiyun #define MONO_PAT_TRANSP 0x00020000 286*4882a593Smuzhiyun #define COLOR_TRANSP_ROP 0x00000000 287*4882a593Smuzhiyun #define COLOR_TRANSP_DST 0x00008000 288*4882a593Smuzhiyun #define COLOR_TRANSP_EQ 0x00000000 289*4882a593Smuzhiyun #define COLOR_TRANSP_NOT_EQ 0x00010000 290*4882a593Smuzhiyun #define COLOR_TRANSP_ENABLE 0x00004000 291*4882a593Smuzhiyun #define MONO_SRC_TRANSP 0x00002000 292*4882a593Smuzhiyun #define SRC_IS_IN_COLOR 0x00000000 293*4882a593Smuzhiyun #define SRC_IS_MONO 0x00001000 294*4882a593Smuzhiyun #define SRC_USE_SRC_ADDR 0x00000000 295*4882a593Smuzhiyun #define SRC_USE_BLTDATA 0x00000400 296*4882a593Smuzhiyun #define BLT_TOP_TO_BOT 0x00000000 297*4882a593Smuzhiyun #define BLT_BOT_TO_TOP 0x00000200 298*4882a593Smuzhiyun #define BLT_LEFT_TO_RIGHT 0x00000000 299*4882a593Smuzhiyun #define BLT_RIGHT_TO_LEFT 0x00000100 300*4882a593Smuzhiyun #define BLT_ROP 0x000000FF 301*4882a593Smuzhiyun #define BLT_PAT_ADDR 0x00040014 302*4882a593Smuzhiyun #define BLT_SRC_ADDR 0x00040018 303*4882a593Smuzhiyun #define BLT_DST_ADDR 0x0004001C 304*4882a593Smuzhiyun #define BLT_DST_H_W 0x00040020 305*4882a593Smuzhiyun #define BLT_DST_HEIGHT 0x1FFF0000 306*4882a593Smuzhiyun #define BLT_DST_WIDTH 0x00001FFF 307*4882a593Smuzhiyun #define SRCEXP_BG_COLOR 0x00040024 308*4882a593Smuzhiyun #define SRCEXP_FG_COLOR 0x00040028 309*4882a593Smuzhiyun #define BLTDATA 0x00050000 310