1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2003 Simtec Electronics 4*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * VR1000 - CPLD control constants 7*4882a593Smuzhiyun * Machine VR1000 - IRQ Number definitions 8*4882a593Smuzhiyun * Machine VR1000 - Memory map definitions 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __MACH_S3C24XX_VR1000_H 12*4882a593Smuzhiyun #define __MACH_S3C24XX_VR1000_H __FILE__ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* irq numbers to onboard peripherals */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define VR1000_IRQ_USBOC IRQ_EINT19 19*4882a593Smuzhiyun #define VR1000_IRQ_IDE0 IRQ_EINT16 20*4882a593Smuzhiyun #define VR1000_IRQ_IDE1 IRQ_EINT17 21*4882a593Smuzhiyun #define VR1000_IRQ_SERIAL IRQ_EINT12 22*4882a593Smuzhiyun #define VR1000_IRQ_DM9000A IRQ_EINT10 23*4882a593Smuzhiyun #define VR1000_IRQ_DM9000N IRQ_EINT9 24*4882a593Smuzhiyun #define VR1000_IRQ_SMALERT IRQ_EINT8 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* map */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000)) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* we put the CPLD registers next, to get them out of the way */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */ 33*4882a593Smuzhiyun #define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */ 36*4882a593Smuzhiyun #define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */ 39*4882a593Smuzhiyun #define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */ 42*4882a593Smuzhiyun #define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* next, we have the PC104 ISA interrupt registers */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */ 47*4882a593Smuzhiyun #define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */ 50*4882a593Smuzhiyun #define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */ 53*4882a593Smuzhiyun #define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * 0xE0000000 contains the IO space that is split by speed and 57*4882a593Smuzhiyun * whether the access is for 8 or 16bit IO... this ensures that 58*4882a593Smuzhiyun * the correct access is made 59*4882a593Smuzhiyun * 60*4882a593Smuzhiyun * 0x10000000 of space, partitioned as so: 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * 0x00000000 to 0x04000000 8bit, slow 63*4882a593Smuzhiyun * 0x04000000 to 0x08000000 16bit, slow 64*4882a593Smuzhiyun * 0x08000000 to 0x0C000000 16bit, net 65*4882a593Smuzhiyun * 0x0C000000 to 0x10000000 16bit, fast 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * each of these spaces has the following in: 68*4882a593Smuzhiyun * 69*4882a593Smuzhiyun * 0x02000000 to 0x02100000 1MB IDE primary channel 70*4882a593Smuzhiyun * 0x02100000 to 0x02200000 1MB IDE primary channel aux 71*4882a593Smuzhiyun * 0x02200000 to 0x02400000 1MB IDE secondary channel 72*4882a593Smuzhiyun * 0x02300000 to 0x02400000 1MB IDE secondary channel aux 73*4882a593Smuzhiyun * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers 74*4882a593Smuzhiyun * 0x02600000 to 0x02700000 1MB 75*4882a593Smuzhiyun * 76*4882a593Smuzhiyun * the phyiscal layout of the zones are: 77*4882a593Smuzhiyun * nGCS2 - 8bit, slow 78*4882a593Smuzhiyun * nGCS3 - 16bit, slow 79*4882a593Smuzhiyun * nGCS4 - 16bit, net 80*4882a593Smuzhiyun * nGCS5 - 16bit, fast 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define VR1000_VA_MULTISPACE (0xE0000000) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000) 86*4882a593Smuzhiyun #define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000) 87*4882a593Smuzhiyun #define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000) 88*4882a593Smuzhiyun #define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000) 89*4882a593Smuzhiyun #define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000) 90*4882a593Smuzhiyun #define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000) 91*4882a593Smuzhiyun #define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000) 92*4882a593Smuzhiyun #define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000) 93*4882a593Smuzhiyun #define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000) 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* physical offset addresses for the peripherals */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define VR1000_PA_IDEPRI (0x02000000) 98*4882a593Smuzhiyun #define VR1000_PA_IDEPRIAUX (0x02800000) 99*4882a593Smuzhiyun #define VR1000_PA_IDESEC (0x03000000) 100*4882a593Smuzhiyun #define VR1000_PA_IDESECAUX (0x03800000) 101*4882a593Smuzhiyun #define VR1000_PA_DM9000 (0x05000000) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define VR1000_PA_SERIAL (0x11800000) 104*4882a593Smuzhiyun #define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000)) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* VR1000 ram is in CS1, with A26..A24 = 2_101 */ 107*4882a593Smuzhiyun #define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* some configurations for the peripherals */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define VR1000_DM9000_CS VR1000_VAM_CS4 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #endif /* __MACH_S3C24XX_VR1000_H */ 114