1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Contains register definitions common to PowerPC 8xx CPUs. Notice 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ASM_POWERPC_REG_8xx_H 6*4882a593Smuzhiyun #define _ASM_POWERPC_REG_8xx_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* Cache control on the MPC8xx is provided through some additional 9*4882a593Smuzhiyun * special purpose registers. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #define SPRN_IC_CST 560 /* Instruction cache control/status */ 12*4882a593Smuzhiyun #define SPRN_IC_ADR 561 /* Address needed for some commands */ 13*4882a593Smuzhiyun #define SPRN_IC_DAT 562 /* Read-only data register */ 14*4882a593Smuzhiyun #define SPRN_DC_CST 568 /* Data cache control/status */ 15*4882a593Smuzhiyun #define SPRN_DC_ADR 569 /* Address needed for some commands */ 16*4882a593Smuzhiyun #define SPRN_DC_DAT 570 /* Read-only data register */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Misc Debug */ 19*4882a593Smuzhiyun #define SPRN_DPDR 630 20*4882a593Smuzhiyun #define SPRN_MI_CAM 816 21*4882a593Smuzhiyun #define SPRN_MI_RAM0 817 22*4882a593Smuzhiyun #define SPRN_MI_RAM1 818 23*4882a593Smuzhiyun #define SPRN_MD_CAM 824 24*4882a593Smuzhiyun #define SPRN_MD_RAM0 825 25*4882a593Smuzhiyun #define SPRN_MD_RAM1 826 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Special MSR manipulation registers */ 28*4882a593Smuzhiyun #define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */ 29*4882a593Smuzhiyun #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ 30*4882a593Smuzhiyun #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Debug registers */ 33*4882a593Smuzhiyun #define SPRN_CMPA 144 34*4882a593Smuzhiyun #define SPRN_COUNTA 150 35*4882a593Smuzhiyun #define SPRN_CMPE 152 36*4882a593Smuzhiyun #define SPRN_CMPF 153 37*4882a593Smuzhiyun #define SPRN_LCTRL1 156 38*4882a593Smuzhiyun #define LCTRL1_CTE_GT 0xc0000000 39*4882a593Smuzhiyun #define LCTRL1_CTF_LT 0x14000000 40*4882a593Smuzhiyun #define LCTRL1_CRWE_RW 0x00000000 41*4882a593Smuzhiyun #define LCTRL1_CRWE_RO 0x00040000 42*4882a593Smuzhiyun #define LCTRL1_CRWE_WO 0x000c0000 43*4882a593Smuzhiyun #define LCTRL1_CRWF_RW 0x00000000 44*4882a593Smuzhiyun #define LCTRL1_CRWF_RO 0x00010000 45*4882a593Smuzhiyun #define LCTRL1_CRWF_WO 0x00030000 46*4882a593Smuzhiyun #define SPRN_LCTRL2 157 47*4882a593Smuzhiyun #define LCTRL2_LW0EN 0x80000000 48*4882a593Smuzhiyun #define LCTRL2_LW0LA_E 0x00000000 49*4882a593Smuzhiyun #define LCTRL2_LW0LA_F 0x04000000 50*4882a593Smuzhiyun #define LCTRL2_LW0LA_EandF 0x08000000 51*4882a593Smuzhiyun #define LCTRL2_LW0LADC 0x02000000 52*4882a593Smuzhiyun #define LCTRL2_SLW0EN 0x00000002 53*4882a593Smuzhiyun #ifdef CONFIG_PPC_8xx 54*4882a593Smuzhiyun #define SPRN_ICTRL 158 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun #define SPRN_BAR 159 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Commands. Only the first few are available to the instruction cache. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define IDC_ENABLE 0x02000000 /* Cache enable */ 61*4882a593Smuzhiyun #define IDC_DISABLE 0x04000000 /* Cache disable */ 62*4882a593Smuzhiyun #define IDC_LDLCK 0x06000000 /* Load and lock */ 63*4882a593Smuzhiyun #define IDC_UNLINE 0x08000000 /* Unlock line */ 64*4882a593Smuzhiyun #define IDC_UNALL 0x0a000000 /* Unlock all */ 65*4882a593Smuzhiyun #define IDC_INVALL 0x0c000000 /* Invalidate all */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define DC_FLINE 0x0e000000 /* Flush data cache line */ 68*4882a593Smuzhiyun #define DC_SFWT 0x01000000 /* Set forced writethrough mode */ 69*4882a593Smuzhiyun #define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ 70*4882a593Smuzhiyun #define DC_SLES 0x05000000 /* Set little endian swap mode */ 71*4882a593Smuzhiyun #define DC_CLES 0x07000000 /* Clear little endian swap mode */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Status. 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define IDC_ENABLED 0x80000000 /* Cache is enabled */ 76*4882a593Smuzhiyun #define IDC_CERR1 0x00200000 /* Cache error 1 */ 77*4882a593Smuzhiyun #define IDC_CERR2 0x00100000 /* Cache error 2 */ 78*4882a593Smuzhiyun #define IDC_CERR3 0x00080000 /* Cache error 3 */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define DC_DFWT 0x40000000 /* Data cache is forced write through */ 81*4882a593Smuzhiyun #define DC_LES 0x20000000 /* Caches are little endian mode */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #endif /* _ASM_POWERPC_REG_8xx_H */ 84