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12

/optee_os/core/arch/arm/plat-rockchip/
H A Dconf.mk17 CFG_TZDRAM_START ?= 0x68400000
18 CFG_TZDRAM_SIZE ?= 0x00200000
19 CFG_SHMEM_START ?= 0x68600000
20 CFG_SHMEM_SIZE ?= 0x00100000
30 include core/arch/arm/cpu/cortex-armv8-0.mk
35 CFG_TZDRAM_START ?= 0x30000000
36 CFG_TZDRAM_SIZE ?= 0x02000000
37 CFG_SHMEM_START ?= 0x32000000
38 CFG_SHMEM_SIZE ?= 0x00400000
48 include core/arch/arm/cpu/cortex-armv8-0.mk
[all …]
/optee_os/core/arch/arm/plat-marvell/
H A Dconf.mk4 include core/arch/arm/cpu/cortex-armv8-0.mk
6 $(call force,CFG_TZDRAM_START,0x04400000)
7 $(call force,CFG_TZDRAM_SIZE,0x00C00000)
8 $(call force,CFG_SHMEM_START,0x05000000)
9 $(call force,CFG_SHMEM_SIZE,0x00400000)
10 $(call force,CFG_TEE_RAM_VA_SIZE,0x00400000)
12 $(call force,CFG_TEE_SDP_MEM_SIZE,0x00400000)
18 include core/arch/arm/cpu/cortex-armv8-0.mk
20 $(call force,CFG_TZDRAM_START,0x04400000)
21 $(call force,CFG_TZDRAM_SIZE,0x00C00000)
[all …]
/optee_os/core/arch/arm/plat-d02/
H A Dconf.mk1 include core/arch/arm/cpu/cortex-armv8-0.mk
26 CFG_TEE_RAM_VA_SIZE ?= 0x00400000
28 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
30 CFG_TZDRAM_START ?= 0x50400000
31 CFG_TZDRAM_SIZE ?= 0x013a00000
32 CFG_SHMEM_START ?= 0x50000000
33 CFG_SHMEM_SIZE ?= 0x00400000
/optee_os/core/arch/arm/plat-k3/
H A Dconf.mk3 CFG_CONSOLE_UART ?= 0
8 CFG_CONSOLE_RUNTIME_LOG_LEVEL ?= 0
11 CFG_TZDRAM_START ?= 0x80200000
12 CFG_TZDRAM_SIZE ?= 0x00400000 # 20MB
15 CFG_TZDRAM_START ?= 0x9e800000
16 CFG_TZDRAM_SIZE ?= 0x01400000 # 20MB
21 CFG_SHMEM_SIZE ?= 0x00400000 # 4MB
49 include core/arch/arm/cpu/cortex-armv8-0.mk
/optee_os/core/arch/arm/plat-hisilicon/
H A Dconf.mk6 include core/arch/arm/cpu/cortex-armv8-0.mk
10 $(call force,CFG_CORE_CLUSTER_SHIFT,0)
20 CFG_NS_ENTRY_ADDR ?= 0x22008000
29 # 0x4000_0000 [DRAM_LIMIT]
32 # 0x3360_0000 -
34 # 0x32a0_0000 -
38 # 0x3260_0000 [TZDRAM_BASE, TEE_LOAD_ADDR] -
42 # 0x32607_0000 -
44 # 0x3260_0000 [TZDRAM_BASE, TZSRAM_BASE, TEE_LOAD_ADDR]
46 # 0x3240_0000
[all …]
/optee_os/lib/libutils/isoc/arch/arm/softfloat/source/8086-SSE/
H A Ds_propagateNaNF32UI.c59 if ( isSigNaNA ) return uiA | 0x00400000; in softfloat_propagateNaNF32UI()
61 return (isNaNF32UI( uiA ) ? uiA : uiB) | 0x00400000; in softfloat_propagateNaNF32UI()
/optee_os/core/arch/arm/dts/
H A Dhikey.dts10 #size-cells = <0>;
19 reg = <0x3E800000 0x00400000>;
H A Dsama5d2.dtsi28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
47 reg = <0x740000 0x1000>;
63 reg = <0x73c000 0x1000>;
79 reg = <0x20000000 0x20000000>;
85 #clock-cells = <0>;
86 clock-frequency = <0>;
91 #clock-cells = <0>;
[all …]
/optee_os/core/arch/arm/plat-rpi5/
H A Dconf.mk1 include core/arch/arm/cpu/cortex-armv8-0.mk
9 CFG_SHMEM_START ?= 0x08000000
10 CFG_SHMEM_SIZE ?= 0x00400000
11 CFG_TZDRAM_START ?= 0x1D000000
12 CFG_TZDRAM_SIZE ?= 0x02000000
13 CFG_TEE_RAM_VA_SIZE ?= 0x00700000
15 CFG_DTB_MAX_SIZE ?= 0x20000
/optee_os/core/arch/arm/plat-synquacer/
H A Dconf.mk7 include core/arch/arm/cpu/cortex-armv8-0.mk
10 CFG_TZDRAM_START ?= 0xfc000000
11 CFG_TZDRAM_SIZE ?= 0x03c00000
12 CFG_SHMEM_START ?= 0xffc00000
13 CFG_SHMEM_SIZE ?= 0x00400000
/optee_os/core/arch/arm/plat-poplar/
H A Dconf.mk1 include core/arch/arm/cpu/cortex-armv8-0.mk
26 CFG_TEE_SDP_MEM_BASE ?= 0x02800000
27 CFG_TEE_SDP_MEM_SIZE ?= 0x00400000
/optee_os/core/arch/arm/plat-rzn1/
H A Dconf.mk19 CFG_TZDRAM_START ?= 0x88000000
20 CFG_TZDRAM_SIZE ?= 0x00A00000
21 CFG_SHMEM_START ?= 0x87C00000
22 CFG_SHMEM_SIZE ?= 0x00400000
23 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
26 CFG_NS_ENTRY_ADDR ?= 0x87A00000
/optee_os/core/arch/arm/plat-rpi3/
H A Dconf.mk1 include core/arch/arm/cpu/cortex-armv8-0.mk
5 CFG_SHMEM_START ?= 0x08000000
6 CFG_SHMEM_SIZE ?= 0x00400000
7 CFG_TZDRAM_START ?= 0x10100000
8 CFG_TZDRAM_SIZE ?= 0x00F00000
9 CFG_TEE_RAM_VA_SIZE ?= 0x00700000
/optee_os/core/arch/arm/plat-sunxi/
H A Dconf.mk19 CFG_NS_ENTRY_ADDR ?= 0x42000000
23 CFG_TZDRAM_START ?= 0x5c000000
24 CFG_TZDRAM_SIZE ?= 0x03e00000
25 CFG_SHMEM_START ?= 0x5fe00000
26 CFG_SHMEM_SIZE ?= 0x00200000
30 include core/arch/arm/cpu/cortex-armv8-0.mk
33 CFG_TZDRAM_START ?= 0x40000000
34 CFG_TZDRAM_SIZE ?= 0x2000000
35 CFG_SHMEM_START ?= 0x44000000
36 CFG_SHMEM_SIZE ?= 0x00400000
/optee_os/core/arch/arm/plat-vexpress/
H A Dconf.mk7 include core/arch/arm/cpu/cortex-armv8-0.mk
11 include core/arch/arm/cpu/cortex-armv8-0.mk
24 include core/arch/arm/cpu/cortex-armv8-0.mk
29 include core/arch/arm/cpu/cortex-armv8-0.mk
51 CFG_TPM_LOG_BASE_ADDR ?= 0x402c951
52 CFG_TPM_MAX_LOG_SIZE ?= 0x200
73 CFG_TZDRAM_START ?= 0x06281000
74 CFG_TZDRAM_SIZE ?= 0x01D80000
76 CFG_TZDRAM_START ?= 0x06000000
77 CFG_TZDRAM_SIZE ?= 0x02000000
[all …]
/optee_os/core/arch/arm/plat-automotive_rd/
H A Dconf.mk20 CFG_CORE_THREAD_SHIFT := 0
27 CFG_CORE_HEAP_SIZE ?= 0x32000
30 CFG_TZDRAM_SIZE ?= 0x00400000
31 CFG_TZDRAM_START ?= 0xFFC00000
/optee_os/core/arch/arm/plat-hikey/
H A Dconf.mk3 include core/arch/arm/cpu/cortex-armv8-0.mk
35 CFG_TEE_SDP_MEM_BASE ?= 0x3E800000
36 CFG_TEE_SDP_MEM_SIZE ?= 0x00400000
48 CFG_ASAN_SHADOW_OFFSET ?= 0x372E38E0
56 CFG_TZDRAM_START ?= 0x3F000000
57 CFG_TZDRAM_SIZE ?= 0x01000000
58 CFG_SHMEM_START ?= 0x3EE00000
59 CFG_SHMEM_SIZE ?= 0x00200000
60 CFG_TEE_RAM_VA_SIZE ?= 0x00200000
61 CFG_DRAM1_BASE ?= 0x40000000
/optee_os/lib/libutils/isoc/arch/arm/softfloat/source/8086/
H A Ds_propagateNaNF32UI.c64 uiNonsigA = uiA | 0x00400000; in softfloat_propagateNaNF32UI()
65 uiNonsigB = uiB | 0x00400000; in softfloat_propagateNaNF32UI()
78 uiMagA = uiNonsigA & 0x7FFFFFFF; in softfloat_propagateNaNF32UI()
79 uiMagB = uiNonsigB & 0x7FFFFFFF; in softfloat_propagateNaNF32UI()
/optee_os/core/arch/riscv/plat-spike/
H A Dconf.mk9 $(call force,CFG_TEE_TA_LOG_LEVEL,0)
37 $(call force,CFG_CORE_THREAD_SHIFT,0)
73 CFG_TDDRAM_START ?= 0xbdb00000
74 CFG_TDDRAM_SIZE ?= 0x00f00000
75 CFG_SHMEM_START ?= 0x7fe00000
76 CFG_SHMEM_SIZE ?= 0x00200000
77 CFG_TEE_RAM_VA_SIZE ?= 0x00400000
/optee_os/core/lib/libefi/include/efi/
H A Defi_types.h21 #define BOOT_WITH_FULL_CONFIGURATION 0x00
22 #define BOOT_WITH_MINIMAL_CONFIGURATION 0x01
23 #define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02
24 #define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03
25 #define BOOT_WITH_DEFAULT_SETTINGS 0x04
26 #define BOOT_ON_S4_RESUME 0x05
27 #define BOOT_ON_S5_RESUME 0x06
28 #define BOOT_WITH_MFG_MODE_SETTINGS 0x07
29 #define BOOT_ON_S2_RESUME 0x10
30 #define BOOT_ON_S3_RESUME 0x11
[all …]
/optee_os/core/arch/arm/plat-imx/
H A Da9_plat_init.S67 * register is encoded as CP15 c15 0 c0 1.
70 * MRC p15,0,rt,c15,c0,1
71 * ORR rt,rt,#0x00400000
72 * MCR p15,0,rt,c15,c0,1
88 * Disallow NSec to mask FIQ [bit4: FW=0]
90 * Imprecise Abort trapped to Abort Mode [bit3: EA=0]
91 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0]
92 * IRQ always trapped to IRQ Mode [bit1: IRQ=0]
93 * Secure World [bit0: NS=0]
101 * SCTLR = 0x00004000
[all …]
/optee_os/lib/libmbedtls/mbedtls/library/
H A Ddes.c33 0x01010400, 0x00000000, 0x00010000, 0x01010404,
34 0x01010004, 0x00010404, 0x00000004, 0x00010000,
35 0x00000400, 0x01010400, 0x01010404, 0x00000400,
36 0x01000404, 0x01010004, 0x01000000, 0x00000004,
37 0x00000404, 0x01000400, 0x01000400, 0x00010400,
38 0x00010400, 0x01010000, 0x01010000, 0x01000404,
39 0x00010004, 0x01000004, 0x01000004, 0x00010004,
40 0x00000000, 0x00000404, 0x00010404, 0x01000000,
41 0x00010000, 0x01010404, 0x00000004, 0x01010000,
42 0x01010400, 0x01000000, 0x01000000, 0x00000400,
[all …]
/optee_os/core/arch/arm/plat-sam/
H A Dsama7g5.h20 #define GIC_DISTRIBUTOR_BASE 0xE8C11000 /* Base for GIC distributor interface */
21 #define GIC_INTERFACE_BASE 0xE8C12000 /* Base address for GIC CPU interface */
22 #define GICC_SIZE 0x1000
23 #define GICD_SIZE 0x1000
28 #define ID_DWDT_SW 0 /* Dual Watchdog Timer, Secure World (DWDT_SW) */
38 #define ID_PIOA 11 /* For PIO 0 to 31 (PIOA) */
48 #define ID_XDMAC0 22 /* DMA 0, mem to periph, 32 Channels (XDMAC0) */
62 #define ID_FLEXCOM0 38 /* Flexcom 0 (FLEXCOM0) */
80 #define ID_I2SMCC0 57 /* Inter-IC Sound Controller 0 (I2SMCC0) */
83 #define ID_MCAN0 61 /* Master CAN 0 (MCAN0) */
[all …]
H A Dsama5d2.h34 #define AT91C_ID_FIQ 0 /* FIQ Interrupt ID */
40 #define AT91C_ID_XDMAC0 6 /* DMA Controller 0 */
63 #define AT91C_ID_TWI0 29 /* Two-wire Interface 0 */
65 #define AT91C_ID_SDMMC0 31 /* SDMMC Controller 0 */
67 #define AT91C_ID_SPI0 33 /* Serial Peripheral Interface 0 */
69 #define AT91C_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
72 #define AT91C_ID_PWM 38 /* PWM Controller0 (ch. 0,1,2,3) */
77 #define AT91C_ID_SSC0 43 /* Serial Synchronous Controller 0 */
88 #define AT91C_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
90 #define AT91C_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
[all …]
/optee_os/.github/workflows/
H A Dci.yml17 fetch-depth: 0 # full history so checkpatch can check commit IDs in commit messages
195 _make PLATFORM=versal CFG_VERSAL_FPGA_DDR_ADDR=0x40000000
228 function download_scp_firmware() { git clone --single-branch https://git.gitlab.arm.com/firmware/SCP-firmware.git $HOME/scp-firmware && git -C $HOME/scp-firmware checkout 0d48080449e3bd3e5218a31c5f24a6068004c5af || (rm -rf $HOME/scp-firmware ; echo Nervermind); }
265 _make PLATFORM=vexpress-qemu_armv8a CFG_TEE_CORE_LOG_LEVEL=0 CFG_TEE_CORE_DEBUG=n CFG_TEE_TA_LOG_LEVEL=0 CFG_DEBUG_INFO=n
266 _make PLATFORM=vexpress-qemu_armv8a CFG_TEE_CORE_LOG_LEVEL=4 CFG_TEE_CORE_DEBUG=y CFG_TEE_TA_LOG_LEVEL=4 CFG_CC_OPT_LEVEL=0 CFG_DEBUG_INFO=y
267 _make PLATFORM=vexpress-qemu_armv8a CFG_TEE_CORE_LOG_LEVEL=0 CFG_TEE_CORE_DEBUG=n CFG_TEE_TA_LOG_LEVEL=0 CFG_DEBUG_INFO=n COMPILER=clang
277 _make PLATFORM=vexpress-qemu_armv8a CFG_CORE_SEL2_SPMC=y CFG_CORE_PHYS_RELOCATABLE=y CFG_TZDRAM_START=0x0d304000 CFG_TZDRAM_SIZE=0x00cfc00
[all...]

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