core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y

Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and
simplify the platforms conf.mk accordingly.

Signed-off-by: Jerome

core: arm.mk: set CFG_ARM32_core=y when CFG_ARM34_core != y

Updates core/arch/arm/arm.mk to assume 32-bit mode when not 64-bit and
simplify the platforms conf.mk accordingly.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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core: remove the unused PM stubs

Removes the PM stubs and all references to CFG_PM_STUBS.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.o

core: remove the unused PM stubs

Removes the PM stubs and all references to CFG_PM_STUBS.

Reviewed-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Move CFG_WITH_STACK_CANARIES to global config file

All platforms but one (bcm-ns3) set CFG_WITH_STACK_CANARIES ?= y in
their configuration files. Move this flag to the global mk/config.mk
instead. N

Move CFG_WITH_STACK_CANARIES to global config file

All platforms but one (bcm-ns3) set CFG_WITH_STACK_CANARIES ?= y in
their configuration files. Move this flag to the global mk/config.mk
instead. Not sure it matters much, but in order to avoid any functional
change, CFG_WITH_STACK_CANARIES ?= n is added to plat-bcm/conf.mk.

Signed-off-by: Jerome Forissier <jerome@forissier.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: make generic boot mandatory

The OP-TEE booting has since quite some time been unified in the sense
that all platforms use CFG_GENERIC_BOOT=y. Make this configuration option
mandatory and remov

core: make generic boot mandatory

The OP-TEE booting has since quite some time been unified in the sense
that all platforms use CFG_GENERIC_BOOT=y. Make this configuration option
mandatory and remove the CFG_GENERIC_BOOT flag.

Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome@forissier.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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Factor out ta-targets from platform config

Platforms use the same basic pattern again and again:

ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif

Let's move this p

Factor out ta-targets from platform config

Platforms use the same basic pattern again and again:

ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif

Let's move this pattern to core/arch/arm/arm.mk, make it the default, and
cleanup the platform configuration files.

Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>

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plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depend

plat-*/conf.mk: use $(call force, ...) to set CFG_TEE_CORE_NB_CORE

Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etien

plat-d02: support generic RAM layout

Move default secure and non-secure Optee memory locations from
platform_config.h to conf.mk using the generic_ram_layout.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (D02)

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core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ confi

core: move CFG_TEE_CORE_NB_CORE to conf.mk for various platforms

Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.

These platforms no more defines CFG_ configuration directives as
NB_CORE was the last remaining one.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>

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core: arm32: enable NEON with .fpu directive rather than compile flag

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU CF

core: arm32: enable NEON with .fpu directive rather than compile flag

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU CFG_WITH_VFP=y)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32 {,pager})
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xt

plat-d02: enable 64-bit paging

Allow CFG_WITH_PAGER=y when building for D02 in 64-bit mode. In this
case, set CFG_CORE_TZSRAM_EMUL_SIZE to 640 KiB to get reasonable
performance.

| time xtest 4002 (s)
---------+--------------------
512 KiB | 16
544 KiB | 6
640 KiB | 0.07

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: Use LPAE, increase pager TZSRAM size to 512K and TEE_RAM to 2M

Fixes a boot error when CFG_WITH_PAGER=y:

INFO: TEE-CORE:
INFO: TEE-CORE: Pager is enabled. Hashes: 512 bytes
INFO:

plat-d02: Use LPAE, increase pager TZSRAM size to 512K and TEE_RAM to 2M

Fixes a boot error when CFG_WITH_PAGER=y:

INFO: TEE-CORE:
INFO: TEE-CORE: Pager is enabled. Hashes: 512 bytes
INFO: TEE-CORE: OP-TEE version: 2.4.0-136-g4ec2358 #25 Tue Jun 13 13:32:21 UTC 2017 arm
INFO: TEE-CORE: Shared memory address range: 50500000, 50f00000
ERROR: TEE-CORE: Panic at core/lib/libtomcrypt/src/tee_ltc_provider.c:500 <get_mpa_scratch_memory_pool>

Panic occurs because tee_pager_alloc() fails to allocate memory from
tee_mm_vcore. Fix this by increasing CFG_TEE_RAM_VA_SIZE from 1 to
2 MiB. This implies to enable LPAE, otherwise the TEE core panics with:

ERROR: TEE-CORE: Panic 'Unsupported page size in translation table' at core/arch/arm/mm/tee_pager.c:219 <set_alias_area>

Finally, CFG_CORE_TZSRAM_EMUL_SIZE has to be increased to at least
416 KiB to avoid:

LD out/arm-plat-d02/core/tee.elf
/usr/bin/arm-linux-gnueabihf-ld: OP-TEE can't fit init part into available physical memory

We choose 512 KiB because smaller values cause horrible performance.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: factorize cpu support

Create core/arch/arm/cpu/<cpu-name>.mk to store CPU generic configurations
settings. Update supported platforms to rely on the generic CPU support.

Platform shall still

core: factorize cpu support

Create core/arch/arm/cpu/<cpu-name>.mk to store CPU generic configurations
settings. Update supported platforms to rely on the generic CPU support.

Platform shall still specify whether they support or not the NEON
extension.

Cortex-A53 and Cortex-A57 are all ARMv8.0 compliant. For ARMv8 core,
we will use ARMv8-A architecture minor version configuration files.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: enable write-implies-execute-never when applicable

HW may or may not support STCLR "WXN" configuration field.
CFG_HWSUPP_MEM_PERM_WXN reflects this state. AArch64 is assumed to
always support

core: enable write-implies-execute-never when applicable

HW may or may not support STCLR "WXN" configuration field.
CFG_HWSUPP_MEM_PERM_WXN reflects this state. AArch64 is assumed to
always support this field.

Enable the "WXN" (and UWXN) bits in STCLR upon configuration directive
CFG_CORE_RWDATA_NOEXEC.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most

core: Add default CFG_CORE_HEAP_SIZE

Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most of the previous values at 24 kB or just above.

Platforms with a previous heap size defined larger than 64 kB overrides
the mk/config.mk setting with a $(platform-dir)/conf.mk setting using the
previous value.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey pager)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Aarch32 pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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core: add default CFG_CORE_TZSRAM_EMUL_SIZE

Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly
defined in TZSRAM_SIZE in each platform_config.h. Default value is
defined in core/

core: add default CFG_CORE_TZSRAM_EMUL_SIZE

Adds a CFG_CORE_TZSRAM_EMUL_SIZE replacing the previous value directly
defined in TZSRAM_SIZE in each platform_config.h. Default value is
defined in core/arch/arm/arm.mk as 300 kB. This is larger than most of
the previous values.

Platforms with TZSRAM_SIZE defined larger than 200 kB overrides the
core/arch/arm/arm.mk setting with a $(platform-dir)/conf.mk setting
using the previous value.

Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

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plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.o

plat-d02: enable hardware RNG

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
Reviewed-by: etienne carriere <etienne.carriere@linaro.org>

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Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57

Add support for Hisilicon D02 (PLATFORM=d02)

D02 is a server-class development board equipped with a Hisilicon
Phosphor V660 processor (also called PV660, P660 or hip05).
The chip has 16 Cortex-A57 cores @ 2.1 GHz.

Note: '-mcpu=cortex-a57' causes the following warning, which doesn't
seem to have any adverse effect on OP-TEE and is registered as a
compiler bug [1]:

CC out/arm-plat-d02/core/lib/libtomcrypt/src/encauth/ccm/ccm_add_nonce.o
{standard input}: Assembler messages:
{standard input}:634: IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8

[1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67591

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>

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