Lines Matching +full:0 +full:x00400000
28 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
42 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
47 reg = <0x740000 0x1000>;
63 reg = <0x73c000 0x1000>;
79 reg = <0x20000000 0x20000000>;
85 #clock-cells = <0>;
86 clock-frequency = <0>;
91 #clock-cells = <0>;
92 clock-frequency = <0>;
98 reg = <0x00200000 0x20000>;
101 ranges = <0 0x00200000 0x20000>;
115 reg = <0x00100000 0x2400>;
118 ranges = <0 0x00100000 0x2400>;
124 reg = <0x00300000 0x100000
125 0xfc02c000 0x400>;
137 reg = <0x00400000 0x100000>;
149 reg = <0x00500000 0x100000>;
161 reg = <0x00a00000 0x1000>;
172 reg = <0x10000000 0x10000000
173 0x60000000 0x30000000>;
174 ranges = <0x0 0x0 0x10000000 0x10000000
175 0x1 0x0 0x60000000 0x10000000
176 0x2 0x0 0x70000000 0x10000000
177 0x3 0x0 0x80000000 0x10000000>;
195 reg = <0xa0000000 0x300>;
196 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
207 reg = <0xb0000000 0x300>;
208 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
219 reg = <0xc0000000 0x8000000>;
230 reg = <0xf0000000 0x2000>;
231 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
239 #size-cells = <0>;
241 port@0 {
243 #size-cells = <0>;
244 reg = <0>;
256 reg = <0xf0008000 0x4000>;
260 #clock-cells = <0>;
267 reg = <0xf000c000 0x200>;
274 reg = <0xf0010000 0x1000>;
275 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
284 reg = <0xf0004000 0x1000>;
285 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
293 reg = <0xf0014000 0x160>;
304 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
309 #size-cells = <0>;
315 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
320 #size-cells = <0>;
326 reg = <0xf0028000 0x100>;
327 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
329 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
339 reg = <0xf002c000 0x100>;
340 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
342 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
345 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
355 reg = <0xf8000000 0x100>;
358 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
361 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
368 #size-cells = <0>;
374 reg = <0xf8004000 0x4000>;
377 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
380 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
390 reg = <0xf8008000 0x1000>;
391 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
395 #size-cells = <0>;
404 #size-cells = <0>;
405 reg = <0xf800c000 0x100>;
406 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
414 #size-cells = <0>;
415 reg = <0xf8010000 0x100>;
416 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
425 reg = <0xf8014000 0x1000>;
434 reg = <0xf8014070 0x490>,
435 <0xf8014500 0x100>;
441 reg = <0xf8018000 0x124>;
444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
454 reg = <0xf801c000 0x100>;
457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
460 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
470 reg = <0xf8020000 0x100>;
473 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
476 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
486 reg = <0xf8024000 0x100>;
489 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
492 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
502 reg = <0xf8028000 0x100>;
505 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
506 AT91_XDMAC_DT_PERID(0))>,
508 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
512 #size-cells = <0>;
520 reg = <0xf802c000 0x4000>;
529 reg = <0xf8030000 0x98>;
536 reg = <0xf8034000 0x200>;
540 ranges = <0x0 0xf8034000 0x800>;
545 reg = <0x200 0x200>;
550 (AT91_XDMAC_DT_MEM_IF(0) |
554 (AT91_XDMAC_DT_MEM_IF(0) |
564 reg = <0x400 0x200>;
567 #size-cells = <0>;
571 (AT91_XDMAC_DT_MEM_IF(0) |
575 (AT91_XDMAC_DT_MEM_IF(0) |
585 reg = <0x600 0x200>;
588 #size-cells = <0>;
591 (AT91_XDMAC_DT_MEM_IF(0) |
595 (AT91_XDMAC_DT_MEM_IF(0) |
606 reg = <0xf8038000 0x200>;
610 ranges = <0x0 0xf8038000 0x800>;
615 reg = <0x200 0x200>;
620 (AT91_XDMAC_DT_MEM_IF(0) |
624 (AT91_XDMAC_DT_MEM_IF(0) |
634 reg = <0x400 0x200>;
637 #size-cells = <0>;
641 (AT91_XDMAC_DT_MEM_IF(0) |
645 (AT91_XDMAC_DT_MEM_IF(0) |
655 reg = <0x600 0x200>;
658 #size-cells = <0>;
661 (AT91_XDMAC_DT_MEM_IF(0) |
665 (AT91_XDMAC_DT_MEM_IF(0) |
676 reg = <0xf8044000 0x1420>;
681 ranges = <0 0xf8044000 0x1420>;
688 reg = <0xf8048000 0x10>;
696 reg = <0xf8048010 0x10>;
699 #size-cells = <0>;
707 reg = <0xf8048030 0x10>;
714 reg = <0xf8048040 0x10>;
723 reg = <0xf8048050 0x4>;
726 #clock-cells = <0>;
733 reg = <0xf80480b0 0x30>;
742 reg = <0xf804c000 0x64>;
750 reg = <0x20 0x20>;
754 reg = <0x24 0x20>;
772 reg = <0xf8050000 0x100>;
775 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
778 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
790 reg = <0xf8054000 0x4000>, <0x210000 0x1c00>;
800 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
806 reg = <0xfc000000 0x100>;
809 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
812 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
819 #size-cells = <0>;
825 reg = <0xfc008000 0x100>;
828 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
831 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
841 reg = <0xfc00c000 0x100>;
843 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
846 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
857 reg = <0xfc010000 0x200>;
861 ranges = <0x0 0xfc010000 0x800>;
866 reg = <0x200 0x200>;
871 (AT91_XDMAC_DT_MEM_IF(0) |
875 (AT91_XDMAC_DT_MEM_IF(0) |
885 reg = <0x400 0x200>;
888 #size-cells = <0>;
892 (AT91_XDMAC_DT_MEM_IF(0) |
896 (AT91_XDMAC_DT_MEM_IF(0) |
906 reg = <0x600 0x200>;
909 #size-cells = <0>;
912 (AT91_XDMAC_DT_MEM_IF(0) |
916 (AT91_XDMAC_DT_MEM_IF(0) |
927 reg = <0xfc014000 0x200>;
931 ranges = <0x0 0xfc014000 0x800>;
936 reg = <0x200 0x200>;
941 (AT91_XDMAC_DT_MEM_IF(0) |
945 (AT91_XDMAC_DT_MEM_IF(0) |
955 reg = <0x400 0x200>;
958 #size-cells = <0>;
962 (AT91_XDMAC_DT_MEM_IF(0) |
966 (AT91_XDMAC_DT_MEM_IF(0) |
976 reg = <0x600 0x200>;
979 #size-cells = <0>;
982 (AT91_XDMAC_DT_MEM_IF(0) |
986 (AT91_XDMAC_DT_MEM_IF(0) |
998 reg = <0xfc018000 0x200>;
1002 ranges = <0x0 0xfc018000 0x800>;
1007 reg = <0x200 0x200>;
1012 (AT91_XDMAC_DT_MEM_IF(0) |
1016 (AT91_XDMAC_DT_MEM_IF(0) |
1026 reg = <0x400 0x200>;
1029 #size-cells = <0>;
1033 (AT91_XDMAC_DT_MEM_IF(0) |
1037 (AT91_XDMAC_DT_MEM_IF(0) |
1047 reg = <0x600 0x200>;
1050 #size-cells = <0>;
1053 (AT91_XDMAC_DT_MEM_IF(0) |
1057 (AT91_XDMAC_DT_MEM_IF(0) |
1068 reg = <0xfc01c000 0x100>;
1069 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1079 reg = <0xfc020000 0x200>;
1087 reg = <0xf803c000 0x200>;
1095 reg = <0xfc028000 0x100>;
1098 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1105 #size-cells = <0>;
1113 reg = <0xfc030000 0x100>;
1117 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1139 reg = <0xfc039000 0x600>;
1155 reg = <0xfc040000 0x100>;
1165 reg = <0xfc044000 0x100>;
1166 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1168 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1171 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1181 reg = <0xfc048000 0x100>;
1184 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1194 reg = <0xfc04c000 0x100>;
1197 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1200 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1212 reg = <0xfc050000 0x4000>, <0x210000 0x3800>;
1222 bosch,mram-cfg = <0x1c00 0 0 64 0 0 32 32>;
1228 reg = <0xfc05c000 0x20>;
1233 reg = <0xfc069000 0x8>;