Lines Matching +full:0 +full:x00400000
34 #define AT91C_ID_FIQ 0 /* FIQ Interrupt ID */
40 #define AT91C_ID_XDMAC0 6 /* DMA Controller 0 */
63 #define AT91C_ID_TWI0 29 /* Two-wire Interface 0 */
65 #define AT91C_ID_SDMMC0 31 /* SDMMC Controller 0 */
67 #define AT91C_ID_SPI0 33 /* Serial Peripheral Interface 0 */
69 #define AT91C_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
72 #define AT91C_ID_PWM 38 /* PWM Controller0 (ch. 0,1,2,3) */
77 #define AT91C_ID_SSC0 43 /* Serial Synchronous Controller 0 */
88 #define AT91C_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
90 #define AT91C_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
98 #define AT91C_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */
119 #define AT91C_BASE_LCDC 0xf0000000
120 #define AT91C_BASE_XDMAC1 0xf0004000
121 #define AT91C_BASE_HXISI 0xf0008000
122 #define AT91C_BASE_MPDDRC 0xf000c000
123 #define AT91C_BASE_XDMAC0 0xf0010000
124 #define AT91C_BASE_PMC 0xf0014000
125 #define AT91C_BASE_MATRIX64 0xf0018000 /* MATRIX0 */
126 #define AT91C_BASE_AESB 0xf001c000
127 #define AT91C_BASE_QSPI0 0xf0020000
128 #define AT91C_BASE_QSPI1 0xf0024000
129 #define AT91C_BASE_SHA 0xf0028000
130 #define AT91C_BASE_AES 0xf002c000
132 #define AT91C_BASE_SPI0 0xf8000000
133 #define AT91C_BASE_SSC0 0xf8004000
134 #define AT91C_BASE_GMAC 0xf8008000
135 #define AT91C_BASE_TC0 0xf800c000
136 #define AT91C_BASE_TC1 0xf8010000
137 #define AT91C_BASE_HSMC 0xf8014000
138 #define AT91C_BASE_PDMIC 0xf8018000
139 #define AT91C_BASE_UART0 0xf801c000
140 #define AT91C_BASE_UART1 0xf8020000
141 #define AT91C_BASE_UART2 0xf8024000
142 #define AT91C_BASE_TWI0 0xf8028000
143 #define AT91C_BASE_PWMC 0xf802c000
144 #define AT91C_BASE_SFR 0xf8030000
145 #define AT91C_BASE_FLEXCOM0 0xf8034000
146 #define AT91C_BASE_FLEXCOM1 0xf8038000
147 #define AT91C_BASE_SAIC 0xf803c000
148 #define AT91C_BASE_ICM 0xf8040000
149 #define AT91C_BASE_SECURAM 0xf8044000
150 #define AT91C_BASE_SYSC 0xf8048000
151 #define AT91C_BASE_ACC 0xf804a000
152 #define AT91C_BASE_RXLP 0xf8049000
153 #define AT91C_BASE_SFC 0xf804c000
154 #define AT91C_BASE_I2SC0 0xf8050000
155 #define AT91C_BASE_CAN0 0xf8054000
157 #define AT91C_BASE_SPI1 0xfc000000
158 #define AT91C_BASE_SSC1 0xfc004000
159 #define AT91C_BASE_UART3 0xfc008000
160 #define AT91C_BASE_UART4 0xfc00c000
161 #define AT91C_BASE_FLEXCOM2 0xfc010000
162 #define AT91C_BASE_FLEXCOM3 0xfc014000
163 #define AT91C_BASE_FLEXCOM4 0xfc018000
164 #define AT91C_BASE_TRNG 0xfc01c000
165 #define AT91C_BASE_AIC 0xfc020000
166 #define AT91C_BASE_TWI1 0xfc028000
167 #define AT91C_BASE_UDPHS 0xfc02c000
168 #define AT91C_BASE_ADC 0xfc030000
170 #define AT91C_BASE_PIOA 0xfc038000
171 #define AT91C_BASE_MATRIX32 0xfc03c000 /* MATRIX1 */
172 #define AT91C_BASE_SECUMOD 0xfc040000
173 #define AT91C_BASE_TDES 0xfc044000
174 #define AT91C_BASE_CLASSD 0xfc048000
175 #define AT91C_BASE_I2SC1 0xfc04c000
176 #define AT91C_BASE_CAN1 0xfc050000
177 #define AT91C_BASE_SFRBU 0xfc05c000
178 #define AT91C_BASE_CHIPID 0xfc069000
183 #define AT91C_BASE_INTERNAL_MEM 0x00000000
184 #define AT91C_BASE_CS0 0x10000000
185 #define AT91C_BASE_DDRCS 0x20000000
186 #define AT91C_BASE_DDRCS_AES 0x40000000
187 #define AT91C_BASE_CS1 0x60000000
188 #define AT91C_BASE_CS2 0x70000000
189 #define AT91C_BASE_CS3 0x80000000
190 #define AT91C_BASE_QSPI0_AES_MEM 0x90000000
191 #define AT91C_BASE_QSPI1_AES_MEM 0x98000000
192 #define AT91C_BASE_SDHC0 0xa0000000
193 #define AT91C_BASE_SDHC1 0xb0000000
194 #define AT91C_BASE_NFC_CMD_REG 0xc0000000
195 #define AT91C_BASE_QSPI0_MEM 0xd0000000
196 #define AT91C_BASE_QSPI1_MEM 0xd8000000
197 #define AT91C_BASE_PERIPH 0xf0000000
202 #define AT91C_BASE_ROM 0x00000000 /* ROM */
203 #define AT91C_BASE_ECC_ROM 0x00060000 /* ECC ROM */
204 #define AT91C_BASE_NFC_SRAM 0x00100000 /* NFC SRAM */
205 #define AT91C_BASE_SRAM0 0x00200000 /* SRAM0 */
206 #define AT91C_BASE_SRAM1 0x00220000 /* SRAM1 */
207 #define AT91C_BASE_UDPHS_SRAM 0x00300000 /* UDPHS RAM */
208 #define AT91C_BASE_UHP_OHCI 0x00400000 /* UHP OHCI */
209 #define AT91C_BASE_UHP_EHCI 0x00500000 /* UHP EHCI */
210 #define AT91C_BASE_AXI_MATRIX 0x00600000 /* AXI Maxtrix */
211 #define AT91C_BASE_DAP 0x00700000 /* DAP */
212 #define AT91C_BASE_PTC 0x00800000 /* PTC */
213 #define AT91C_BASE_L2CC 0x00A00000 /* L2CC */
218 #define AT91C_BASE_PMECC (AT91C_BASE_HSMC + 0x70)
219 #define AT91C_BASE_PMERRLOC (AT91C_BASE_HSMC + 0x500)
224 #define AT91C_BASE_PIOB (AT91C_BASE_PIOA + 0x40)
225 #define AT91C_BASE_PIOC (AT91C_BASE_PIOB + 0x40)
226 #define AT91C_BASE_PIOD (AT91C_BASE_PIOC + 0x40)
230 #define AT91C_BASE_SHDC (AT91C_BASE_SYSC + 0x10)
231 #define AT91C_BASE_PITC (AT91C_BASE_SYSC + 0x30)
232 #define AT91C_BASE_WDT (AT91C_BASE_SYSC + 0x40)
233 #define AT91C_BASE_SCKCR (AT91C_BASE_SYSC + 0x50)
234 #define AT91C_BASE_RTCC (AT91C_BASE_SYSC + 0xb0)
236 #define ATMEL_BASE_SMC (AT91C_BASE_HSMC + 0x700)
242 #define AICREDIR_KEY 0xB6D81C4D
249 #define H64MX_SLAVE_BRIDGE_TO_AXIMX 0
266 #define H32MX_BRIDGE_TO_H64MX 0 /* Bridge from H32MX to H64MX */
267 #define H32MX_PERI_BRIDGE_0 1 /* H32MX Peripheral Bridge 0 */