Lines Matching +full:0 +full:x00400000
20 #define GIC_DISTRIBUTOR_BASE 0xE8C11000 /* Base for GIC distributor interface */
21 #define GIC_INTERFACE_BASE 0xE8C12000 /* Base address for GIC CPU interface */
22 #define GICC_SIZE 0x1000
23 #define GICD_SIZE 0x1000
28 #define ID_DWDT_SW 0 /* Dual Watchdog Timer, Secure World (DWDT_SW) */
38 #define ID_PIOA 11 /* For PIO 0 to 31 (PIOA) */
48 #define ID_XDMAC0 22 /* DMA 0, mem to periph, 32 Channels (XDMAC0) */
62 #define ID_FLEXCOM0 38 /* Flexcom 0 (FLEXCOM0) */
80 #define ID_I2SMCC0 57 /* Inter-IC Sound Controller 0 (I2SMCC0) */
83 #define ID_MCAN0 61 /* Master CAN 0 (MCAN0) */
90 #define ID_PDMC0 68 /* Pulse Density Modulation Controller 0 */
92 #define ID_PIT64B0 70 /* 64-bit Periodic Interval Timer 0 (PIT64B0) */
99 #define ID_QSPI0 78 /* Quad IO Serial Peripheral Interface 0 */
101 #define ID_SDMMC0 80 /* Ultra HS SD Host controller 0 (eMMC 5.1) */
107 #define ID_SSC0 86 /* Synchronous Serial Interface 0 (SSC0) */
109 #define ID_TC0_CHANNEL0 88 /* 32-bit Timer Counter 0 Channel 0 */
110 #define ID_TC0_CHANNEL1 89 /* 32-bit Timer Counter 0 Channel 1 interrupt */
111 #define ID_TC0_CHANNEL2 90 /* 32-bit Timer Counter 0 Channel 2 interrupt */
112 #define ID_TC1_CHANNEL0 91 /* 32-bit Timer Counter 1 Channel 0 */
128 #define ID_XDMAC0_SINT 112 /* DMA 0, mem to periph, 32 CH, Secure INT */
145 #define ID_PIOA_SINT 129 /* For PIO 0 to 31, Secure INTerrupt */
150 #define ID_PIT64B0_SINT 135 /* 64-bit PIT 0, Secure INTerrupt */
156 #define ID_SDMMC0_TIMER 141 /* SD Host controller 0 (eMMC 5.1) Timer int */
160 #define ID_TC0_SINT0 145 /* 32-bit TC 0 Channel 0, Secure INTerrupt */
161 #define ID_TC0_SINT1 146 /* 32-bit TC 0 Channel 1, Secure INTerrupt */
162 #define ID_TC0_SINT2 147 /* 32-bit TC 0 Channel 2 (TC0_SINT2) */
163 #define ID_TC1_SINT0 148 /* 32-bit TC 1 Channel 0, Secure INTerrupt */
176 #define ACC_BASE_ADDRESS 0xe1600000
177 #define ADC_BASE_ADDRESS 0xe1000000
178 #define AES_BASE_ADDRESS 0xe1810000
179 #define ASRC_BASE_ADDRESS 0xe1610000
180 #define BSC_BASE_ADDRESS 0xe001d054
181 #define CHIPID_BASE_ADDRESS 0xe0020000
182 #define CSI_BASE_ADDRESS 0xe1400000
183 #define CPKCC_BASE_ADDRESS 0xe000c000
184 #define CSI2DC_BASE_ADDRESS 0xe1404000
185 #define DDRPUBL_BASE_ADDRESS 0xe3804000
186 #define DWDT_BASE_ADDRESS 0xe001c000
187 #define EIC_BASE_ADDRESS 0xe1628000
188 #define FLEXCOM0_BASE_ADDRESS 0xe1818000
189 #define FLEXCOM1_BASE_ADDRESS 0xe181c000
190 #define FLEXCOM2_BASE_ADDRESS 0xe1820000
191 #define FLEXCOM3_BASE_ADDRESS 0xe1824000
192 #define FLEXCOM4_BASE_ADDRESS 0xe2018000
193 #define FLEXCOM5_BASE_ADDRESS 0xe201c000
194 #define FLEXCOM6_BASE_ADDRESS 0xe2020000
195 #define FLEXCOM7_BASE_ADDRESS 0xe2024000
196 #define FLEXCOM8_BASE_ADDRESS 0xe2818000
197 #define FLEXCOM9_BASE_ADDRESS 0xe281c000
198 #define FLEXCOM10_BASE_ADDRESS 0xe2820000
199 #define FLEXCOM11_BASE_ADDRESS 0xe2824000
200 #define GMAC0_BASE_ADDRESS 0xe2800000
201 #define GMAC1_BASE_ADDRESS 0xe2804000
202 #define GPBR_BASE_ADDRESS 0xe001d060
203 #define I2SMCC0_BASE_ADDRESS 0xe161c000
204 #define I2SMCC1_BASE_ADDRESS 0xe1620000
205 #define ICM_BASE_ADDRESS 0xe081c000
206 #define ISC_BASE_ADDRESS 0xe1408000
207 #define MATRIX_BASE_ADDRESS 0xe0804000
208 #define MCAN0_BASE_ADDRESS 0xe0828000
209 #define MCAN1_BASE_ADDRESS 0xe082c000
210 #define MCAN2_BASE_ADDRESS 0xe0830000
211 #define MCAN3_BASE_ADDRESS 0xe0834000
212 #define MCAN4_BASE_ADDRESS 0xe0838000
213 #define MCAN5_BASE_ADDRESS 0xe083c000
214 #define NICGPV_BASE_ADDRESS 0xe8b00000
215 #define OTPC_BASE_ADDRESS 0xe8c00000
216 #define PDMC0_BASE_ADDRESS 0xe1608000
217 #define PDMC1_BASE_ADDRESS 0xe160c000
218 #define PIO_BASE_ADDRESS 0xe0014000
219 #define PIT64B0_BASE_ADDRESS 0xe1800000
220 #define PIT64B1_BASE_ADDRESS 0xe1804000
221 #define PIT64B2_BASE_ADDRESS 0xe1808000
222 #define PIT64B3_BASE_ADDRESS 0xe2004000
223 #define PIT64B4_BASE_ADDRESS 0xe2008000
224 #define PIT64B5_BASE_ADDRESS 0xe2810000
225 #define PMC_BASE_ADDRESS 0xe0018000
226 #define PWM_BASE_ADDRESS 0xe1604000
227 #define QSPI0_BASE_ADDRESS 0xe080c000
228 #define QSPI1_BASE_ADDRESS 0xe0810000
229 #define RSTC_BASE_ADDRESS 0xe001d000
230 #define RTC_BASE_ADDRESS 0xe001d0a8
231 #define RTT_BASE_ADDRESS 0xe001d020
232 #define SCKC_BASE_ADDRESS 0xe001d050
233 #define SDMMC0_BASE_ADDRESS 0xe1204000
234 #define SDMMC1_BASE_ADDRESS 0xe1208000
235 #define SDMMC2_BASE_ADDRESS 0xe120c000
236 #define SECUMOD_BASE_ADDRESS 0xe0004000
237 #define SFR_BASE_ADDRESS 0xe1624000
238 #define SFRBU_BASE_ADDRESS 0xe0008000
239 #define SHA_BASE_ADDRESS 0xe1814000
240 #define SHDWC_BASE_ADDRESS 0xe001d010
241 #define HSMC_BASE_ADDRESS 0xe0808000
242 #define SPDIFRX_BASE_ADDRESS 0xe1614000
243 #define SPDIFTX_BASE_ADDRESS 0xe1618000
244 #define SSC0_BASE_ADDRESS 0xe180c000
245 #define SSC1_BASE_ADDRESS 0xe200c000
246 #define SYSCWP_BASE_ADDRESS 0xe001d0dc
247 #define TC0_BASE_ADDRESS 0xe2814000
248 #define TC1_BASE_ADDRESS 0xe0800000
249 #define TCPCA_BASE_ADDRESS 0xe0840000
250 #define TCPCB_BASE_ADDRESS 0xe0844000
251 #define TDES_BASE_ADDRESS 0xe2014000
252 #define TRNG_BASE_ADDRESS 0xe2010000
253 #define TZAESBNS_BASE_ADDRESS 0xe0820000
254 #define TZAESBS_BASE_ADDRESS 0xe0824000
255 #define TZAESBASC_BASE_ADDRESS 0xe2000000
256 #define TZC_BASE_ADDRESS 0xe3000000
257 #define TZPM_BASE_ADDRESS 0xe0010000
258 #define DDRUMCTL_BASE_ADDRESS 0xe3800000
259 #define UDPHSA_BASE_ADDRESS 0xe0814000
260 #define UDPHSB_BASE_ADDRESS 0xe0818000
261 #define UHPHS_OHCI_BASE_ADDRESS 0x00400000
262 #define UHPHS_EHCI_BASE_ADDRESS 0x00500000
263 #define XDMAC0_BASE_ADDRESS 0xe2808000
264 #define XDMAC1_BASE_ADDRESS 0xe280c000
265 #define XDMAC2_BASE_ADDRESS 0xe1200000
270 #define IROM_SIZE 0x00014000
271 #define ECC_ROM_SIZE 0x00018000
272 #define CPKCC_ROM_SIZE 0x00010000
273 #define CPKCC_RAM_SIZE 0x00001000
274 #define IRAM_SIZE 0x00020000
275 #define UDPHS_RAMA_SIZE 0x00100000
276 #define UDPHS_RAMB_SIZE 0x00100000
277 #define UHPHS_OHCI_SIZE 0x00001000
278 #define UHPHS_EHCI_SIZE 0x00100000
279 #define NFC_RAM_SIZE 0x00003000
280 #define NFC_SIZE 0x08000000
281 #define QSPIMEM0_SIZE 0x10000000
282 #define QSPIMEM1_SIZE 0x10000000
283 #define EBI_CS0_SIZE 0x08000000
284 #define EBI_CS1_SIZE 0x08000000
285 #define EBI_CS2_SIZE 0x08000000
286 #define EBI_CS3_SIZE 0x08000000
287 #define DDR_CS_SIZE 0x80000000
288 #define SECURAM_SIZE 0x00004000
289 #define SDMMC0_SIZE 0x00004000
290 #define SDMMC1_SIZE 0x00004000
291 #define SDMMC2_SIZE 0x00004000
292 #define APB_DBG_S_SIZE 0x00060000
293 #define APB_DBG_SIZE 0x00001000
294 #define NICGPV_SIZE 0x00100000
295 #define OTPC_SIZE 0x00001000
296 #define CSI2DC_META_SIZE 0x00002000
297 #define ARM_PERIPH_SIZE 0x00008000
298 #define PERIPHERALS_SIZE 0x10000000
300 #define IROM_ADDR 0x00000000
301 #define ECC_ROM_ADDR 0x00020000
302 #define CPKCC_ROM_ADDR 0x00040000
303 #define CPKCC_RAM_ADDR 0x00051000
304 #define IRAM_ADDR 0x00100000
305 #define UDPHS_RAMA_ADDR 0x00200000
306 #define UDPHS_RAMB_ADDR 0x00300000
307 #define UHPHS_OHCI_ADDR 0x00400000
308 #define UHPHS_EHCI_ADDR 0x00500000
309 #define NFC_RAM_ADDR 0x00600000
310 #define NFC_ADDR 0x10000000
311 #define QSPIMEM0_ADDR 0x20000000
312 #define QSPIMEM1_ADDR 0x30000000
313 #define EBI_CS0_ADDR 0x40000000
314 #define EBI_CS1_ADDR 0x48000000
315 #define EBI_CS2_ADDR 0x50000000
316 #define EBI_CS3_ADDR 0x58000000
317 #define DDR_CS_ADDR 0x60000000
318 #define SECURAM_ADDR 0xe0000000
319 #define SDMMC0_ADDR 0xe1204000
320 #define SDMMC1_ADDR 0xe1208000
321 #define SDMMC2_ADDR 0xe120c000
322 #define APB_DBG_S_ADDR 0xe8800000
323 #define APB_DBG_ADDR 0xe8900000
324 #define NICGPV_ADDR 0xe8b00000
325 #define OTPC_ADDR 0xe8c00000
326 #define CSI2DC_META_ADDR 0xe8c02000
327 #define ARM_PERIPH_ADDR 0xe8c10000
328 #define PERIPHERALS_ADDR 0xe0000000
333 #define CHIP_JTAGID 0X05B4203F
334 #define CHIP_CIDR 0X80162110
335 #define CHIP_EXID 0X00000000