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/OK3568_Linux_fs/u-boot/arch/m68k/include/asm/coldfire/
H A Dlcd.h15 u32 ssar; /* 0x00 Screen Start Address Register */
16 u32 sr; /* 0x04 LCD Size Register */
17 u32 vpw; /* 0x08 Virtual Page Width Register */
18 u32 cpr; /* 0x0C Cursor Position Register */
19 u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
20 u32 ccmr; /* 0x14 Color Cursor Mapping Register */
21 u32 pcr; /* 0x18 Panel Configuration Register */
22 u32 hcr; /* 0x1C Horizontal Configuration Register */
23 u32 vcr; /* 0x20 Vertical Configuration Register */
24 u32 por; /* 0x24 Panning Offset Register */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath9k/
H A Dreg.h22 #define AR_CR 0x0008
23 #define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h109 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
110 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
115 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
116 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
117 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
118 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
119 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
120 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
121 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
122 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
H A Dsdram.h23 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
30 u32 dram_timing4; /* 0x10 */
35 u32 dram_addrw; /* 0x2c */
36 u32 dram_if_width; /* 0x30 */
40 u32 sbe_count; /* 0x40 */
44 u32 drop_addr; /* 0x50 */
48 u32 ctrl_width; /* 0x60 */
52 u32 rfifo_cmap; /* 0x70 */
56 u32 fpgaport_rst; /* 0x80 */
60 u32 prot_rule_addr; /* 0x90 */
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dtmiofb.c29 #define TMIOFB_ACC_CSADR(x) (0x00000000 | ((x) & 0x001ffffe))
30 #define TMIOFB_ACC_CHPIX(x) (0x01000000 | ((x) & 0x000003ff))
31 #define TMIOFB_ACC_CVPIX(x) (0x02000000 | ((x) & 0x000003ff))
32 #define TMIOFB_ACC_PSADR(x) (0x03000000 | ((x) & 0x00fffffe))
33 #define TMIOFB_ACC_PHPIX(x) (0x04000000 | ((x) & 0x000003ff))
34 #define TMIOFB_ACC_PVPIX(x) (0x05000000 | ((x) & 0x000003ff))
35 #define TMIOFB_ACC_PHOFS(x) (0x06000000 | ((x) & 0x000003ff))
36 #define TMIOFB_ACC_PVOFS(x) (0x07000000 | ((x) & 0x000003ff))
37 #define TMIOFB_ACC_POADR(x) (0x08000000 | ((x) & 0x00fffffe))
38 #define TMIOFB_ACC_RSTR(x) (0x09000000 | ((x) & 0x000000ff))
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_default.h26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/ath/ath5k/
H A Dreg.h46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/OK3568_Linux_fs/u-boot/board/freescale/mx6qarm2/
H A Dimximage.cfg35 DATA 4 0x020C4018 0x60324
37 DATA 4 0x020E05a8 0x00003038
38 DATA 4 0x020E05b0 0x00003038
39 DATA 4 0x020E0524 0x00003038
40 DATA 4 0x020E051c 0x00003038
42 DATA 4 0x020E0518 0x00003038
43 DATA 4 0x020E050c 0x00003038
44 DATA 4 0x020E05b8 0x00003038
45 DATA 4 0x020E05c0 0x00003038
47 DATA 4 0x020E05ac 0x00000038
[all …]
/OK3568_Linux_fs/u-boot/board/aristainetos/
H A Dclocks.cfg18 DATA 4, CCM_CCGR0, 0x00c03f3f
19 DATA 4, CCM_CCGR1, 0x0030fcff
20 DATA 4, CCM_CCGR2, 0x0fffcfc0
21 DATA 4, CCM_CCGR3, 0x3ff0300f
22 DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
23 DATA 4, CCM_CCGR5, 0x0f0000c3
24 DATA 4, CCM_CCGR6, 0x000003ff
/OK3568_Linux_fs/u-boot/board/advantech/dms-ba16/
H A Dclocks.cfg2 DATA 4, CCM_CCGR0, 0x00C03F3F
3 DATA 4, CCM_CCGR1, 0x0030FC03
4 DATA 4, CCM_CCGR2, 0x0FFFC000
5 DATA 4, CCM_CCGR3, 0x3FF00000
6 DATA 4, CCM_CCGR4, 0x00FFF300
7 DATA 4, CCM_CCGR5, 0x0F0000C3
8 DATA 4, CCM_CCGR6, 0x000003FF
11 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
12 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
13 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
/OK3568_Linux_fs/u-boot/board/tqc/tqma6/
H A Dclocks.cfg12 DATA 4, CCM_CCGR0, 0x00C03F3F
13 DATA 4, CCM_CCGR1, 0x0030FC03
14 DATA 4, CCM_CCGR2, 0x0FFFC000
15 DATA 4, CCM_CCGR3, 0x3FF00000
16 DATA 4, CCM_CCGR4, 0x00FFF300
17 DATA 4, CCM_CCGR5, 0x0F0000C3
18 DATA 4, CCM_CCGR6, 0x000003FF
21 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
22 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
23 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
/OK3568_Linux_fs/u-boot/board/boundary/nitrogen6x/
H A Dclocks.cfg18 DATA 4, CCM_CCGR0, 0x00C03F3F
19 DATA 4, CCM_CCGR1, 0x0030FC03
20 DATA 4, CCM_CCGR2, 0x0FFFC000
21 DATA 4, CCM_CCGR3, 0x3FF00000
22 DATA 4, CCM_CCGR4, 0x00FFF300
23 DATA 4, CCM_CCGR5, 0x0F0000C3
24 DATA 4, CCM_CCGR6, 0x000003FF
27 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
29 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
/OK3568_Linux_fs/u-boot/board/toradex/apalis_imx6/
H A Dclocks.cfg19 DATA 4, CCM_CCGR0, 0x00C03F3F
20 DATA 4, CCM_CCGR1, 0x0030FC03
21 DATA 4, CCM_CCGR2, 0x0FFFC000
22 DATA 4, CCM_CCGR3, 0x3FF00000
23 DATA 4, CCM_CCGR4, 0x00FFF300
24 DATA 4, CCM_CCGR5, 0x0F0000C3
25 DATA 4, CCM_CCGR6, 0x000003FF
28 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
29 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
30 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
/OK3568_Linux_fs/u-boot/board/toradex/colibri_imx6/
H A Dclocks.cfg19 DATA 4, CCM_CCGR0, 0x00C03F3F
20 DATA 4, CCM_CCGR1, 0x0030FC03
21 DATA 4, CCM_CCGR2, 0x0FFFC000
22 DATA 4, CCM_CCGR3, 0x3FF00000
23 DATA 4, CCM_CCGR4, 0x00FFF300
24 DATA 4, CCM_CCGR5, 0x0F0000C3
25 DATA 4, CCM_CCGR6, 0x000003FF
28 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
29 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
30 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/
H A Drtw8723d.h20 IQK_ROUND_INVALID = 0xff,
37 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
53 u8 channel_plan; /* 0xb8 */
57 u8 pa_type; /* 0xbc */
58 u8 lna_type_2g[2]; /* 0xbd */
68 u8 rf_antenna_option; /* 0xc9 */
77 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
81 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8))
83 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16))
85 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28))
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c47 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
48 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
49 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
50 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
51 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
52 mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
53 mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
54 mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
55 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
56 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
[all …]
/OK3568_Linux_fs/u-boot/board/barco/platinum/
H A Dplatinum.h69 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
70 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
71 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
72 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
73 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
74 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
75 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
/OK3568_Linux_fs/kernel/drivers/input/touchscreen/
H A Dlpc32xx_ts.c20 #define LPC32XX_TSC_STAT 0x00
21 #define LPC32XX_TSC_SEL 0x04
22 #define LPC32XX_TSC_CON 0x08
23 #define LPC32XX_TSC_FIFO 0x0C
24 #define LPC32XX_TSC_DTR 0x10
25 #define LPC32XX_TSC_RTR 0x14
26 #define LPC32XX_TSC_UTR 0x18
27 #define LPC32XX_TSC_TTR 0x1C
28 #define LPC32XX_TSC_DXP 0x20
29 #define LPC32XX_TSC_MIN_X 0x24
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h6 #define MCDE_IMSCPP 0x00000104
7 #define MCDE_RISPP 0x00000114
8 #define MCDE_MISPP 0x00000124
9 #define MCDE_SISPP 0x00000134
11 #define MCDE_PP_VCMPA BIT(0)
21 #define MCDE_IMSCOVL 0x00000108
22 #define MCDE_RISOVL 0x00000118
23 #define MCDE_MISOVL 0x00000128
24 #define MCDE_SISOVL 0x00000138
27 #define MCDE_IMSCCHNL 0x0000010C
[all …]

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