1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * MPC823 LCD and Video Controller 3*4882a593Smuzhiyun * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __LCDVIDEO_H__ 6*4882a593Smuzhiyun #define __LCDVIDEO_H__ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* LCD Controller Configuration Register. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun #define LCCR_BNUM ((uint)0xfffe0000) 12*4882a593Smuzhiyun #define LCCR_EIEN ((uint)0x00010000) 13*4882a593Smuzhiyun #define LCCR_IEN ((uint)0x00008000) 14*4882a593Smuzhiyun #define LCCR_IRQL ((uint)0x00007000) 15*4882a593Smuzhiyun #define LCCR_CLKP ((uint)0x00000800) 16*4882a593Smuzhiyun #define LCCR_OEP ((uint)0x00000400) 17*4882a593Smuzhiyun #define LCCR_HSP ((uint)0x00000200) 18*4882a593Smuzhiyun #define LCCR_VSP ((uint)0x00000100) 19*4882a593Smuzhiyun #define LCCR_DP ((uint)0x00000080) 20*4882a593Smuzhiyun #define LCCR_BPIX ((uint)0x00000060) 21*4882a593Smuzhiyun #define LCCR_LBW ((uint)0x00000010) 22*4882a593Smuzhiyun #define LCCR_SPLT ((uint)0x00000008) 23*4882a593Smuzhiyun #define LCCR_CLOR ((uint)0x00000004) 24*4882a593Smuzhiyun #define LCCR_TFT ((uint)0x00000002) 25*4882a593Smuzhiyun #define LCCR_PON ((uint)0x00000001) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Define the bit shifts to load values into the register. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun #define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define LCCR_BNUM_BIT ((uint)14) 32*4882a593Smuzhiyun #define LCCR_EIEN_BIT ((uint)15) 33*4882a593Smuzhiyun #define LCCR_IEN_BIT ((uint)16) 34*4882a593Smuzhiyun #define LCCR_IROL_BIT ((uint)19) 35*4882a593Smuzhiyun #define LCCR_CLKP_BIT ((uint)20) 36*4882a593Smuzhiyun #define LCCR_OEP_BIT ((uint)21) 37*4882a593Smuzhiyun #define LCCR_HSP_BIT ((uint)22) 38*4882a593Smuzhiyun #define LCCR_VSP_BIT ((uint)23) 39*4882a593Smuzhiyun #define LCCR_DP_BIT ((uint)24) 40*4882a593Smuzhiyun #define LCCR_BPIX_BIT ((uint)26) 41*4882a593Smuzhiyun #define LCCR_LBW_BIT ((uint)27) 42*4882a593Smuzhiyun #define LCCR_SPLT_BIT ((uint)28) 43*4882a593Smuzhiyun #define LCCR_CLOR_BIT ((uint)29) 44*4882a593Smuzhiyun #define LCCR_TFT_BIT ((uint)30) 45*4882a593Smuzhiyun #define LCCR_PON_BIT ((uint)31) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* LCD Horizontal control register. 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define LCHCR_BO ((uint)0x01000000) 50*4882a593Smuzhiyun #define LCHCR_AT ((uint)0x00e00000) 51*4882a593Smuzhiyun #define LCHCR_HPC ((uint)0x001ffc00) 52*4882a593Smuzhiyun #define LCHCR_WBL ((uint)0x000003ff) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define LCHCR_AT_BIT ((uint)10) 55*4882a593Smuzhiyun #define LCHCR_HPC_BIT ((uint)21) 56*4882a593Smuzhiyun #define LCHCR_WBL_BIT ((uint)31) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* LCD Vertical control register. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define LCVCR_VPW ((uint)0xf0000000) 61*4882a593Smuzhiyun #define LCVCR_LCD_AC ((uint)0x01e00000) 62*4882a593Smuzhiyun #define LCVCR_VPC ((uint)0x001ff800) 63*4882a593Smuzhiyun #define LCVCR_WBF ((uint)0x000003ff) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define LCVCR_VPW_BIT ((uint)3) 66*4882a593Smuzhiyun #define LCVCR_LCD_AC_BIT ((uint)10) 67*4882a593Smuzhiyun #define LCVCR_VPC_BIT ((uint)20) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* __LCDVIDEO_H__ */ 70