1*4882a593Smuzhiyun/* set the default clock gate to save power */ 2*4882a593SmuzhiyunDATA 4, CCM_CCGR0, 0x00C03F3F 3*4882a593SmuzhiyunDATA 4, CCM_CCGR1, 0x0030FC03 4*4882a593SmuzhiyunDATA 4, CCM_CCGR2, 0x0FFFC000 5*4882a593SmuzhiyunDATA 4, CCM_CCGR3, 0x3FF00000 6*4882a593SmuzhiyunDATA 4, CCM_CCGR4, 0x00FFF300 7*4882a593SmuzhiyunDATA 4, CCM_CCGR5, 0x0F0000C3 8*4882a593SmuzhiyunDATA 4, CCM_CCGR6, 0x000003FF 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/* enable AXI cache for VDOA/VPU/IPU */ 11*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 12*4882a593Smuzhiyun/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 13*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 14*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/* 17*4882a593Smuzhiyun * Setup CCM_CCOSR register as follows: 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * cko1_en 1 --> CKO1 enabled 20*4882a593Smuzhiyun * cko1_div 111 --> divide by 8 21*4882a593Smuzhiyun * cko1_sel 1011 --> ahb_clk_root 22*4882a593Smuzhiyun * 23*4882a593Smuzhiyun * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz 24*4882a593Smuzhiyun */ 25*4882a593SmuzhiyunDATA 4, CCM_CCOSR, 0x000000fb 26