1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _PLATINUM_H_ 8*4882a593Smuzhiyun #define _PLATINUM_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <miiphy.h> 11*4882a593Smuzhiyun #include <asm/arch/crm_regs.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Defines */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ 17*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ 18*4882a593Smuzhiyun PAD_CTL_HYS) 19*4882a593Smuzhiyun #define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ 20*4882a593Smuzhiyun PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 21*4882a593Smuzhiyun PAD_CTL_HYS) 22*4882a593Smuzhiyun #define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ 23*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ 24*4882a593Smuzhiyun PAD_CTL_HYS) 25*4882a593Smuzhiyun #define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ 26*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ 27*4882a593Smuzhiyun PAD_CTL_HYS) 28*4882a593Smuzhiyun #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ 29*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ 30*4882a593Smuzhiyun PAD_CTL_HYS) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 36*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 37*4882a593Smuzhiyun PAD_CTL_ODE | PAD_CTL_SRE_FAST) 38*4882a593Smuzhiyun #define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 39*4882a593Smuzhiyun PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 40*4882a593Smuzhiyun PAD_CTL_ODE | PAD_CTL_SRE_SLOW) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 43*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ 44*4882a593Smuzhiyun PAD_CTL_HYS) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 47*4882a593Smuzhiyun PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ 48*4882a593Smuzhiyun PAD_CTL_HYS) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 52*4882a593Smuzhiyun #define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Prototypes */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun int platinum_setup_enet(void); 57*4882a593Smuzhiyun int platinum_setup_i2c(void); 58*4882a593Smuzhiyun int platinum_setup_spi(void); 59*4882a593Smuzhiyun int platinum_setup_uart(void); 60*4882a593Smuzhiyun int platinum_phy_config(struct phy_device *phydev); 61*4882a593Smuzhiyun int platinum_init_gpio(void); 62*4882a593Smuzhiyun int platinum_init_usb(void); 63*4882a593Smuzhiyun int platinum_init_finished(void); 64*4882a593Smuzhiyun ccgr_init(void)65*4882a593Smuzhiyunstatic inline void ccgr_init(void) 66*4882a593Smuzhiyun { 67*4882a593Smuzhiyun struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun writel(0x00C03F3F, &ccm->CCGR0); 70*4882a593Smuzhiyun writel(0x0030FC03, &ccm->CCGR1); 71*4882a593Smuzhiyun writel(0x0FFFC000, &ccm->CCGR2); 72*4882a593Smuzhiyun writel(0x3FF00000, &ccm->CCGR3); 73*4882a593Smuzhiyun writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ 74*4882a593Smuzhiyun writel(0x0F0000C3, &ccm->CCGR5); 75*4882a593Smuzhiyun writel(0x000003FF, &ccm->CCGR6); 76*4882a593Smuzhiyun } 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif /* _PLATINUM_H_ */ 79