1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * LPC32xx built-in touchscreen driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 NXP Semiconductors
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/platform_device.h>
9*4882a593Smuzhiyun #include <linux/input.h>
10*4882a593Smuzhiyun #include <linux/interrupt.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/io.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Touchscreen controller register offsets
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun #define LPC32XX_TSC_STAT 0x00
21*4882a593Smuzhiyun #define LPC32XX_TSC_SEL 0x04
22*4882a593Smuzhiyun #define LPC32XX_TSC_CON 0x08
23*4882a593Smuzhiyun #define LPC32XX_TSC_FIFO 0x0C
24*4882a593Smuzhiyun #define LPC32XX_TSC_DTR 0x10
25*4882a593Smuzhiyun #define LPC32XX_TSC_RTR 0x14
26*4882a593Smuzhiyun #define LPC32XX_TSC_UTR 0x18
27*4882a593Smuzhiyun #define LPC32XX_TSC_TTR 0x1C
28*4882a593Smuzhiyun #define LPC32XX_TSC_DXP 0x20
29*4882a593Smuzhiyun #define LPC32XX_TSC_MIN_X 0x24
30*4882a593Smuzhiyun #define LPC32XX_TSC_MAX_X 0x28
31*4882a593Smuzhiyun #define LPC32XX_TSC_MIN_Y 0x2C
32*4882a593Smuzhiyun #define LPC32XX_TSC_MAX_Y 0x30
33*4882a593Smuzhiyun #define LPC32XX_TSC_AUX_UTR 0x34
34*4882a593Smuzhiyun #define LPC32XX_TSC_AUX_MIN 0x38
35*4882a593Smuzhiyun #define LPC32XX_TSC_AUX_MAX 0x3C
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define LPC32XX_TSC_STAT_FIFO_OVRRN (1 << 8)
38*4882a593Smuzhiyun #define LPC32XX_TSC_STAT_FIFO_EMPTY (1 << 7)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define LPC32XX_TSC_SEL_DEFVAL 0x0284
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 (0x1 << 11)
43*4882a593Smuzhiyun #define LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(s) ((10 - (s)) << 7)
44*4882a593Smuzhiyun #define LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(s) ((10 - (s)) << 4)
45*4882a593Smuzhiyun #define LPC32XX_TSC_ADCCON_POWER_UP (1 << 2)
46*4882a593Smuzhiyun #define LPC32XX_TSC_ADCCON_AUTO_EN (1 << 0)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define LPC32XX_TSC_FIFO_TS_P_LEVEL (1 << 31)
49*4882a593Smuzhiyun #define LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(x) (((x) & 0x03FF0000) >> 16)
50*4882a593Smuzhiyun #define LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(y) ((y) & 0x000003FF)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define LPC32XX_TSC_ADCDAT_VALUE_MASK 0x000003FF
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define LPC32XX_TSC_MIN_XY_VAL 0x0
55*4882a593Smuzhiyun #define LPC32XX_TSC_MAX_XY_VAL 0x3FF
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define MOD_NAME "ts-lpc32xx"
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define tsc_readl(dev, reg) \
60*4882a593Smuzhiyun __raw_readl((dev)->tsc_base + (reg))
61*4882a593Smuzhiyun #define tsc_writel(dev, reg, val) \
62*4882a593Smuzhiyun __raw_writel((val), (dev)->tsc_base + (reg))
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct lpc32xx_tsc {
65*4882a593Smuzhiyun struct input_dev *dev;
66*4882a593Smuzhiyun void __iomem *tsc_base;
67*4882a593Smuzhiyun int irq;
68*4882a593Smuzhiyun struct clk *clk;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
lpc32xx_fifo_clear(struct lpc32xx_tsc * tsc)71*4882a593Smuzhiyun static void lpc32xx_fifo_clear(struct lpc32xx_tsc *tsc)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun while (!(tsc_readl(tsc, LPC32XX_TSC_STAT) &
74*4882a593Smuzhiyun LPC32XX_TSC_STAT_FIFO_EMPTY))
75*4882a593Smuzhiyun tsc_readl(tsc, LPC32XX_TSC_FIFO);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
lpc32xx_ts_interrupt(int irq,void * dev_id)78*4882a593Smuzhiyun static irqreturn_t lpc32xx_ts_interrupt(int irq, void *dev_id)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun u32 tmp, rv[4], xs[4], ys[4];
81*4882a593Smuzhiyun int idx;
82*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = dev_id;
83*4882a593Smuzhiyun struct input_dev *input = tsc->dev;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun tmp = tsc_readl(tsc, LPC32XX_TSC_STAT);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun if (tmp & LPC32XX_TSC_STAT_FIFO_OVRRN) {
88*4882a593Smuzhiyun /* FIFO overflow - throw away samples */
89*4882a593Smuzhiyun lpc32xx_fifo_clear(tsc);
90*4882a593Smuzhiyun return IRQ_HANDLED;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun * Gather and normalize 4 samples. Pen-up events may have less
95*4882a593Smuzhiyun * than 4 samples, but its ok to pop 4 and let the last sample
96*4882a593Smuzhiyun * pen status check drop the samples.
97*4882a593Smuzhiyun */
98*4882a593Smuzhiyun idx = 0;
99*4882a593Smuzhiyun while (idx < 4 &&
100*4882a593Smuzhiyun !(tsc_readl(tsc, LPC32XX_TSC_STAT) &
101*4882a593Smuzhiyun LPC32XX_TSC_STAT_FIFO_EMPTY)) {
102*4882a593Smuzhiyun tmp = tsc_readl(tsc, LPC32XX_TSC_FIFO);
103*4882a593Smuzhiyun xs[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
104*4882a593Smuzhiyun LPC32XX_TSC_FIFO_NORMALIZE_X_VAL(tmp);
105*4882a593Smuzhiyun ys[idx] = LPC32XX_TSC_ADCDAT_VALUE_MASK -
106*4882a593Smuzhiyun LPC32XX_TSC_FIFO_NORMALIZE_Y_VAL(tmp);
107*4882a593Smuzhiyun rv[idx] = tmp;
108*4882a593Smuzhiyun idx++;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Data is only valid if pen is still down in last sample */
112*4882a593Smuzhiyun if (!(rv[3] & LPC32XX_TSC_FIFO_TS_P_LEVEL) && idx == 4) {
113*4882a593Smuzhiyun /* Use average of 2nd and 3rd sample for position */
114*4882a593Smuzhiyun input_report_abs(input, ABS_X, (xs[1] + xs[2]) / 2);
115*4882a593Smuzhiyun input_report_abs(input, ABS_Y, (ys[1] + ys[2]) / 2);
116*4882a593Smuzhiyun input_report_key(input, BTN_TOUCH, 1);
117*4882a593Smuzhiyun } else {
118*4882a593Smuzhiyun input_report_key(input, BTN_TOUCH, 0);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun input_sync(input);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun return IRQ_HANDLED;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
lpc32xx_stop_tsc(struct lpc32xx_tsc * tsc)126*4882a593Smuzhiyun static void lpc32xx_stop_tsc(struct lpc32xx_tsc *tsc)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun /* Disable auto mode */
129*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_CON,
130*4882a593Smuzhiyun tsc_readl(tsc, LPC32XX_TSC_CON) &
131*4882a593Smuzhiyun ~LPC32XX_TSC_ADCCON_AUTO_EN);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun clk_disable_unprepare(tsc->clk);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
lpc32xx_setup_tsc(struct lpc32xx_tsc * tsc)136*4882a593Smuzhiyun static int lpc32xx_setup_tsc(struct lpc32xx_tsc *tsc)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun u32 tmp;
139*4882a593Smuzhiyun int err;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun err = clk_prepare_enable(tsc->clk);
142*4882a593Smuzhiyun if (err)
143*4882a593Smuzhiyun return err;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun tmp = tsc_readl(tsc, LPC32XX_TSC_CON) & ~LPC32XX_TSC_ADCCON_POWER_UP;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Set the TSC FIFO depth to 4 samples @ 10-bits per sample (max) */
148*4882a593Smuzhiyun tmp = LPC32XX_TSC_ADCCON_IRQ_TO_FIFO_4 |
149*4882a593Smuzhiyun LPC32XX_TSC_ADCCON_X_SAMPLE_SIZE(10) |
150*4882a593Smuzhiyun LPC32XX_TSC_ADCCON_Y_SAMPLE_SIZE(10);
151*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_CON, tmp);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* These values are all preset */
154*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_SEL, LPC32XX_TSC_SEL_DEFVAL);
155*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_MIN_X, LPC32XX_TSC_MIN_XY_VAL);
156*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_MAX_X, LPC32XX_TSC_MAX_XY_VAL);
157*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_MIN_Y, LPC32XX_TSC_MIN_XY_VAL);
158*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_MAX_Y, LPC32XX_TSC_MAX_XY_VAL);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /* Aux support is not used */
161*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_AUX_UTR, 0);
162*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_AUX_MIN, 0);
163*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_AUX_MAX, 0);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * Set sample rate to about 240Hz per X/Y pair. A single measurement
167*4882a593Smuzhiyun * consists of 4 pairs which gives about a 60Hz sample rate based on
168*4882a593Smuzhiyun * a stable 32768Hz clock source. Values are in clocks.
169*4882a593Smuzhiyun * Rate is (32768 / (RTR + XCONV + RTR + YCONV + DXP + TTR + UTR) / 4
170*4882a593Smuzhiyun */
171*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_RTR, 0x2);
172*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_DTR, 0x2);
173*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_TTR, 0x10);
174*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_DXP, 0x4);
175*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_UTR, 88);
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun lpc32xx_fifo_clear(tsc);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* Enable automatic ts event capture */
180*4882a593Smuzhiyun tsc_writel(tsc, LPC32XX_TSC_CON, tmp | LPC32XX_TSC_ADCCON_AUTO_EN);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
lpc32xx_ts_open(struct input_dev * dev)185*4882a593Smuzhiyun static int lpc32xx_ts_open(struct input_dev *dev)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return lpc32xx_setup_tsc(tsc);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
lpc32xx_ts_close(struct input_dev * dev)192*4882a593Smuzhiyun static void lpc32xx_ts_close(struct input_dev *dev)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = input_get_drvdata(dev);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun lpc32xx_stop_tsc(tsc);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
lpc32xx_ts_probe(struct platform_device * pdev)199*4882a593Smuzhiyun static int lpc32xx_ts_probe(struct platform_device *pdev)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct lpc32xx_tsc *tsc;
202*4882a593Smuzhiyun struct input_dev *input;
203*4882a593Smuzhiyun struct resource *res;
204*4882a593Smuzhiyun resource_size_t size;
205*4882a593Smuzhiyun int irq;
206*4882a593Smuzhiyun int error;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
209*4882a593Smuzhiyun if (!res) {
210*4882a593Smuzhiyun dev_err(&pdev->dev, "Can't get memory resource\n");
211*4882a593Smuzhiyun return -ENOENT;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
215*4882a593Smuzhiyun if (irq < 0)
216*4882a593Smuzhiyun return irq;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun tsc = kzalloc(sizeof(*tsc), GFP_KERNEL);
219*4882a593Smuzhiyun input = input_allocate_device();
220*4882a593Smuzhiyun if (!tsc || !input) {
221*4882a593Smuzhiyun dev_err(&pdev->dev, "failed allocating memory\n");
222*4882a593Smuzhiyun error = -ENOMEM;
223*4882a593Smuzhiyun goto err_free_mem;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun tsc->dev = input;
227*4882a593Smuzhiyun tsc->irq = irq;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun size = resource_size(res);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (!request_mem_region(res->start, size, pdev->name)) {
232*4882a593Smuzhiyun dev_err(&pdev->dev, "TSC registers are not free\n");
233*4882a593Smuzhiyun error = -EBUSY;
234*4882a593Smuzhiyun goto err_free_mem;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun tsc->tsc_base = ioremap(res->start, size);
238*4882a593Smuzhiyun if (!tsc->tsc_base) {
239*4882a593Smuzhiyun dev_err(&pdev->dev, "Can't map memory\n");
240*4882a593Smuzhiyun error = -ENOMEM;
241*4882a593Smuzhiyun goto err_release_mem;
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun tsc->clk = clk_get(&pdev->dev, NULL);
245*4882a593Smuzhiyun if (IS_ERR(tsc->clk)) {
246*4882a593Smuzhiyun dev_err(&pdev->dev, "failed getting clock\n");
247*4882a593Smuzhiyun error = PTR_ERR(tsc->clk);
248*4882a593Smuzhiyun goto err_unmap;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun input->name = MOD_NAME;
252*4882a593Smuzhiyun input->phys = "lpc32xx/input0";
253*4882a593Smuzhiyun input->id.bustype = BUS_HOST;
254*4882a593Smuzhiyun input->id.vendor = 0x0001;
255*4882a593Smuzhiyun input->id.product = 0x0002;
256*4882a593Smuzhiyun input->id.version = 0x0100;
257*4882a593Smuzhiyun input->dev.parent = &pdev->dev;
258*4882a593Smuzhiyun input->open = lpc32xx_ts_open;
259*4882a593Smuzhiyun input->close = lpc32xx_ts_close;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
262*4882a593Smuzhiyun input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
263*4882a593Smuzhiyun input_set_abs_params(input, ABS_X, LPC32XX_TSC_MIN_XY_VAL,
264*4882a593Smuzhiyun LPC32XX_TSC_MAX_XY_VAL, 0, 0);
265*4882a593Smuzhiyun input_set_abs_params(input, ABS_Y, LPC32XX_TSC_MIN_XY_VAL,
266*4882a593Smuzhiyun LPC32XX_TSC_MAX_XY_VAL, 0, 0);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun input_set_drvdata(input, tsc);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun error = request_irq(tsc->irq, lpc32xx_ts_interrupt,
271*4882a593Smuzhiyun 0, pdev->name, tsc);
272*4882a593Smuzhiyun if (error) {
273*4882a593Smuzhiyun dev_err(&pdev->dev, "failed requesting interrupt\n");
274*4882a593Smuzhiyun goto err_put_clock;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun error = input_register_device(input);
278*4882a593Smuzhiyun if (error) {
279*4882a593Smuzhiyun dev_err(&pdev->dev, "failed registering input device\n");
280*4882a593Smuzhiyun goto err_free_irq;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun platform_set_drvdata(pdev, tsc);
284*4882a593Smuzhiyun device_init_wakeup(&pdev->dev, 1);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun return 0;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun err_free_irq:
289*4882a593Smuzhiyun free_irq(tsc->irq, tsc);
290*4882a593Smuzhiyun err_put_clock:
291*4882a593Smuzhiyun clk_put(tsc->clk);
292*4882a593Smuzhiyun err_unmap:
293*4882a593Smuzhiyun iounmap(tsc->tsc_base);
294*4882a593Smuzhiyun err_release_mem:
295*4882a593Smuzhiyun release_mem_region(res->start, size);
296*4882a593Smuzhiyun err_free_mem:
297*4882a593Smuzhiyun input_free_device(input);
298*4882a593Smuzhiyun kfree(tsc);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return error;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
lpc32xx_ts_remove(struct platform_device * pdev)303*4882a593Smuzhiyun static int lpc32xx_ts_remove(struct platform_device *pdev)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = platform_get_drvdata(pdev);
306*4882a593Smuzhiyun struct resource *res;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun free_irq(tsc->irq, tsc);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun input_unregister_device(tsc->dev);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun clk_put(tsc->clk);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun iounmap(tsc->tsc_base);
315*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316*4882a593Smuzhiyun release_mem_region(res->start, resource_size(res));
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun kfree(tsc);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun #ifdef CONFIG_PM
lpc32xx_ts_suspend(struct device * dev)324*4882a593Smuzhiyun static int lpc32xx_ts_suspend(struct device *dev)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
327*4882a593Smuzhiyun struct input_dev *input = tsc->dev;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun /*
330*4882a593Smuzhiyun * Suspend and resume can be called when the device hasn't been
331*4882a593Smuzhiyun * enabled. If there are no users that have the device open, then
332*4882a593Smuzhiyun * avoid calling the TSC stop and start functions as the TSC
333*4882a593Smuzhiyun * isn't yet clocked.
334*4882a593Smuzhiyun */
335*4882a593Smuzhiyun mutex_lock(&input->mutex);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun if (input->users) {
338*4882a593Smuzhiyun if (device_may_wakeup(dev))
339*4882a593Smuzhiyun enable_irq_wake(tsc->irq);
340*4882a593Smuzhiyun else
341*4882a593Smuzhiyun lpc32xx_stop_tsc(tsc);
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun mutex_unlock(&input->mutex);
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
lpc32xx_ts_resume(struct device * dev)349*4882a593Smuzhiyun static int lpc32xx_ts_resume(struct device *dev)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct lpc32xx_tsc *tsc = dev_get_drvdata(dev);
352*4882a593Smuzhiyun struct input_dev *input = tsc->dev;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun mutex_lock(&input->mutex);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (input->users) {
357*4882a593Smuzhiyun if (device_may_wakeup(dev))
358*4882a593Smuzhiyun disable_irq_wake(tsc->irq);
359*4882a593Smuzhiyun else
360*4882a593Smuzhiyun lpc32xx_setup_tsc(tsc);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun mutex_unlock(&input->mutex);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun return 0;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun static const struct dev_pm_ops lpc32xx_ts_pm_ops = {
369*4882a593Smuzhiyun .suspend = lpc32xx_ts_suspend,
370*4882a593Smuzhiyun .resume = lpc32xx_ts_resume,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun #define LPC32XX_TS_PM_OPS (&lpc32xx_ts_pm_ops)
373*4882a593Smuzhiyun #else
374*4882a593Smuzhiyun #define LPC32XX_TS_PM_OPS NULL
375*4882a593Smuzhiyun #endif
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun #ifdef CONFIG_OF
378*4882a593Smuzhiyun static const struct of_device_id lpc32xx_tsc_of_match[] = {
379*4882a593Smuzhiyun { .compatible = "nxp,lpc3220-tsc", },
380*4882a593Smuzhiyun { },
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, lpc32xx_tsc_of_match);
383*4882a593Smuzhiyun #endif
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun static struct platform_driver lpc32xx_ts_driver = {
386*4882a593Smuzhiyun .probe = lpc32xx_ts_probe,
387*4882a593Smuzhiyun .remove = lpc32xx_ts_remove,
388*4882a593Smuzhiyun .driver = {
389*4882a593Smuzhiyun .name = MOD_NAME,
390*4882a593Smuzhiyun .pm = LPC32XX_TS_PM_OPS,
391*4882a593Smuzhiyun .of_match_table = of_match_ptr(lpc32xx_tsc_of_match),
392*4882a593Smuzhiyun },
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun module_platform_driver(lpc32xx_ts_driver);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com");
397*4882a593Smuzhiyun MODULE_DESCRIPTION("LPC32XX TSC Driver");
398*4882a593Smuzhiyun MODULE_LICENSE("GPL");
399*4882a593Smuzhiyun MODULE_ALIAS("platform:lpc32xx_ts");
400