1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices 3*4882a593Smuzhiyun * Copyright (C) 2014-2016, Toradex AG 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Device Configuration Data (DCD) 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Each entry must have the format: 10*4882a593Smuzhiyun * Addr-type Address Value 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * where: 13*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 14*4882a593Smuzhiyun * Address absolute address of the register 15*4882a593Smuzhiyun * value value to be stored in the register 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun/* set the default clock gate to save power */ 19*4882a593SmuzhiyunDATA 4, CCM_CCGR0, 0x00C03F3F 20*4882a593SmuzhiyunDATA 4, CCM_CCGR1, 0x0030FC03 21*4882a593SmuzhiyunDATA 4, CCM_CCGR2, 0x0FFFC000 22*4882a593SmuzhiyunDATA 4, CCM_CCGR3, 0x3FF00000 23*4882a593SmuzhiyunDATA 4, CCM_CCGR4, 0x00FFF300 24*4882a593SmuzhiyunDATA 4, CCM_CCGR5, 0x0F0000C3 25*4882a593SmuzhiyunDATA 4, CCM_CCGR6, 0x000003FF 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun/* enable AXI cache for VDOA/VPU/IPU */ 28*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 29*4882a593Smuzhiyun/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 30*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 31*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun/* 34*4882a593Smuzhiyun * Setup CCM_CCOSR register as follows: 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * cko1_en = 1 --> CKO1 enabled 37*4882a593Smuzhiyun * cko1_div = 111 --> divide by 8 38*4882a593Smuzhiyun * cko1_sel = 1011 --> ahb_clk_root 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz 41*4882a593Smuzhiyun */ 42*4882a593SmuzhiyunDATA 4, CCM_CCOSR, 0x000000fb 43