| 96b9f0a7 | 21-Sep-2017 |
Vasily Khoruzhick <anarsoul@gmail.com> |
UPSTREAM: video: add anx6345 DM driver
This is a eDP bridge similar to ANX9804, it allows to connect eDP panels
to the chips that can output only parallel signal
Change-Id: I35dbe3ea1c8868420fce582
UPSTREAM: video: add anx6345 DM driver
This is a eDP bridge similar to ANX9804, it allows to connect eDP panels
to the chips that can output only parallel signal
Change-Id: I35dbe3ea1c8868420fce58279e877a0641903b94
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
[agust: fixed most checkpatch errors/warnings]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(cherry-picked from 491041c74965275defd2749db0e2248b2a7e317a)
show more ...
|
| 7587ed89 | 06-Nov-2018 |
Vasily Khoruzhick <anarsoul@gmail.com> |
UPSTREAM: dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing
Both GPIOs are optional, so we shouldn't fail if any is missing.
Without this fix reset is not deasserted
UPSTREAM: dm: video: bridge: don't fail to activate bridge if reset or sleep GPIO is missing
Both GPIOs are optional, so we shouldn't fail if any is missing.
Without this fix reset is not deasserted if sleep GPIO is missing.
Change-Id: I25f2d11d7df96a4a93fcd844bcf34c3fb5109336
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
(cherry-picked from 8336a43792a103c13d939b3925cb75322911f7fb)
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| 048dba01 | 03-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: video: Add support for the NXP PTN3460 bridge
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). There is no setu
dm: video: Add support for the NXP PTN3460 bridge
This chip provides an eDP to LVDS bridge which is useful for SoCs that don't
support LVDS displays (or it would waste scarce pins). There is no setup
required by this chip, other than to adjust power-down and reset pins, and
those are managed by the uclass.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 5eaeadaa | 03-Aug-2015 |
Simon Glass <sjg@chromium.org> |
video: Work around lack of pinctrl
We haven't quite got pinctrl ready to apply to mainline. We don't want to
GPIO pull-up/down support to the driver model GPIO layer either. So work
around this for
video: Work around lack of pinctrl
We haven't quite got pinctrl ready to apply to mainline. We don't want to
GPIO pull-up/down support to the driver model GPIO layer either. So work
around this for now.
We can address this when pinctrl is complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|