xref: /rk3399_rockchip-uboot/arch/arm/dts/rk3308-u-boot.dtsi (revision 75eb6fceb584d246c2b7cfac79b4fe43d0ec0ecd) 
1/*
2 * (C) Copyright 2018 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8
9	chosen {
10		stdout-path = &uart2;
11		u-boot,spl-boot-order = &nandc, &emmc;
12	};
13};
14
15&dmc {
16	u-boot,dm-pre-reloc;
17};
18
19&cru {
20	u-boot,dm-pre-reloc;
21};
22
23&emmc {
24	u-boot,dm-pre-reloc;
25};
26
27&grf {
28	u-boot,dm-pre-reloc;
29};
30
31&nandc {
32	u-boot,dm-pre-reloc;
33	status = "okay";
34	#address-cells = <1>;
35	#size-cells = <0>;
36
37	nand@0 {
38		u-boot,dm-spl;
39		reg = <0>;
40		nand-ecc-mode = "hw_syndrome";
41		nand-ecc-strength = <16>;
42		nand-ecc-step-size = <1024>;
43	};
44};
45
46&sfc {
47	u-boot,dm-pre-reloc;
48	status = "okay";
49};
50
51&saradc {
52	u-boot,dm-pre-reloc;
53	status = "okay";
54};
55
56&secure_otp {
57	u-boot,dm-pre-reloc;
58};
59
60&uart0 {
61	u-boot,dm-pre-reloc;
62};
63
64&uart1 {
65	u-boot,dm-pre-reloc;
66};
67
68&uart2 {
69	u-boot,dm-pre-reloc;
70	clock-frequency = <24000000>;
71	status = "okay";
72};
73
74&uart3 {
75	u-boot,dm-pre-reloc;
76};
77
78&uart4 {
79	u-boot,dm-pre-reloc;
80};
81
82&usb2phy_grf {
83	u-boot,dm-pre-reloc;
84};
85
86&u2phy {
87	u-boot,dm-pre-reloc;
88	status = "okay";
89};
90
91&u2phy_otg {
92	u-boot,dm-pre-reloc;
93	status = "okay";
94};
95
96&usb20_otg {
97	u-boot,dm-pre-reloc;
98	status = "okay";
99};
100
101&route_rgb {
102	status = "disabled";
103};
104