1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "sfc_nor.h" 12 #include "rkflash_debug.h" 13 #include "rkflash_blk.h" 14 15 static struct flash_info spi_flash_tbl[] = { 16 /* GD25Q32B */ 17 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 18 /* GD25Q64B */ 19 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 20 /* GD25Q127C and GD25Q128C*/ 21 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 22 /* GD25Q256B/C/D */ 23 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 24 /* GD25Q512MC */ 25 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 26 /* 25Q64JVSSIQ */ 27 { 0xef4017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 28 /* 25Q128FV and 25Q128JV*/ 29 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 30 /* 25Q256FV */ 31 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 32 /* 25Q64FWSSIG */ 33 { 0xef6017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 34 /* MX25L6433F */ 35 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 36 /* MX25L12835E/F MX25L12833FMI-10G */ 37 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 38 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 39 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 40 /* MX25L51245GMI */ 41 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 42 /* XM25QH32C */ 43 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 44 /* XM25QH64B */ 45 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 46 /* XM25QH128B */ 47 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 48 /* XM25QH(QU)256B */ 49 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 50 /* XM25QH64A */ 51 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 52 /* XT25F128A XM25QH128A */ 53 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0 }, 54 /* XT25F128BSSIGU */ 55 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 56 /* EN25QH128A */ 57 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 58 /* EN25S32A */ 59 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 60 /* EN25S64A */ 61 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 62 /* P25Q64H */ 63 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 64 }; 65 66 static const u8 sfnor_dev_code[] = { 67 0x11, 68 0x12, 69 0x13, 70 0x14, 71 0x15, 72 0x16, 73 0x17, 74 0x18, 75 0x19 76 }; 77 78 static const u32 sfnor_capacity[] = { 79 0x20000, /* 128k-byte */ 80 0x40000, /* 256k-byte */ 81 0x80000, /* 512k-byte */ 82 0x100000, /* 1M-byte */ 83 0x200000, /* 2M-byte */ 84 0x400000, /* 4M-byte */ 85 0x800000, /* 8M-byte */ 86 0x1000000, /* 16M-byte */ 87 0x2000000 /* 32M-byte */ 88 }; 89 90 static struct flash_info *g_spi_flash_info; 91 92 static int snor_write_en(void) 93 { 94 int ret; 95 union SFCCMD_DATA sfcmd; 96 97 sfcmd.d32 = 0; 98 sfcmd.b.cmd = CMD_WRITE_EN; 99 100 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 101 102 return ret; 103 } 104 105 static int snor_enter_4byte_mode(void) 106 { 107 int ret; 108 union SFCCMD_DATA sfcmd; 109 110 sfcmd.d32 = 0; 111 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 112 113 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 114 return ret; 115 } 116 117 static int snor_read_status(u32 reg_index, u8 *status) 118 { 119 int ret; 120 union SFCCMD_DATA sfcmd; 121 u8 read_stat_cmd[] = {CMD_READ_STATUS, 122 CMD_READ_STATUS2, CMD_READ_STATUS3}; 123 sfcmd.d32 = 0; 124 sfcmd.b.cmd = read_stat_cmd[reg_index]; 125 sfcmd.b.datasize = 1; 126 127 ret = sfc_request(sfcmd.d32, 0, 0, status); 128 129 return ret; 130 } 131 132 static int snor_wait_busy(int timeout) 133 { 134 int ret; 135 union SFCCMD_DATA sfcmd; 136 int i; 137 u32 status; 138 139 sfcmd.d32 = 0; 140 sfcmd.b.cmd = CMD_READ_STATUS; 141 sfcmd.b.datasize = 1; 142 143 for (i = 0; i < timeout; i++) { 144 ret = sfc_request(sfcmd.d32, 0, 0, &status); 145 if (ret != SFC_OK) 146 return ret; 147 148 if ((status & 0x01) == 0) 149 return SFC_OK; 150 151 sfc_delay(1); 152 } 153 PRINT_SFC_E("%s error %x\n", __func__, timeout); 154 155 return SFC_BUSY_TIMEOUT; 156 } 157 158 static int snor_write_status2(u32 reg_index, u8 status) 159 { 160 int ret; 161 union SFCCMD_DATA sfcmd; 162 u8 status2[2]; 163 u8 read_index; 164 165 status2[reg_index] = status; 166 read_index = (reg_index == 0) ? 2 : 0; 167 ret = snor_read_status(read_index, &status2[read_index]); 168 if (ret != SFC_OK) 169 return ret; 170 171 snor_write_en(); 172 173 sfcmd.d32 = 0; 174 sfcmd.b.cmd = CMD_WRITE_STATUS; 175 sfcmd.b.datasize = 2; 176 sfcmd.b.rw = SFC_WRITE; 177 178 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 179 if (ret != SFC_OK) 180 return ret; 181 182 ret = snor_wait_busy(10000); /* 10ms */ 183 184 return ret; 185 } 186 187 static int snor_write_status1(u32 reg_index, u8 status) 188 { 189 int ret; 190 union SFCCMD_DATA sfcmd; 191 u8 status2[2]; 192 u8 read_index; 193 194 status2[reg_index] = status; 195 read_index = (reg_index == 0) ? 1 : 0; 196 ret = snor_read_status(read_index, &status2[read_index]); 197 if (ret != SFC_OK) 198 return ret; 199 200 snor_write_en(); 201 202 sfcmd.d32 = 0; 203 sfcmd.b.cmd = CMD_WRITE_STATUS; 204 sfcmd.b.datasize = 2; 205 sfcmd.b.rw = SFC_WRITE; 206 207 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 208 if (ret != SFC_OK) 209 return ret; 210 211 ret = snor_wait_busy(10000); /* 10ms */ 212 213 return ret; 214 } 215 216 static int snor_write_status(u32 reg_index, u8 status) 217 { 218 int ret; 219 union SFCCMD_DATA sfcmd; 220 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 221 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 222 snor_write_en(); 223 sfcmd.d32 = 0; 224 sfcmd.b.cmd = write_stat_cmd[reg_index]; 225 sfcmd.b.datasize = 1; 226 sfcmd.b.rw = SFC_WRITE; 227 228 ret = sfc_request(sfcmd.d32, 0, 0, &status); 229 if (ret != SFC_OK) 230 return ret; 231 232 ret = snor_wait_busy(10000); /* 10ms */ 233 234 return ret; 235 } 236 237 static int snor_erase(struct SFNOR_DEV *p_dev, 238 u32 addr, 239 enum NOR_ERASE_TYPE erase_type) 240 { 241 int ret; 242 union SFCCMD_DATA sfcmd; 243 int timeout[] = {400, 2000, 40000}; /* ms */ 244 245 if (erase_type > ERASE_CHIP) 246 return SFC_PARAM_ERR; 247 248 sfcmd.d32 = 0; 249 if (erase_type == ERASE_BLOCK64K) 250 sfcmd.b.cmd = p_dev->blk_erase_cmd; 251 else if (erase_type == ERASE_SECTOR) 252 sfcmd.b.cmd = p_dev->sec_erase_cmd; 253 else 254 sfcmd.b.cmd = CMD_CHIP_ERASE; 255 256 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 257 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 258 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 259 sfcmd.b.addrbits = SFC_ADDR_32BITS; 260 261 snor_write_en(); 262 263 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 264 if (ret != SFC_OK) 265 return ret; 266 267 ret = snor_wait_busy(timeout[erase_type] * 1000); 268 return ret; 269 } 270 271 static int snor_prog_page(struct SFNOR_DEV *p_dev, 272 u32 addr, 273 void *p_data, 274 u32 size) 275 { 276 int ret; 277 union SFCCMD_DATA sfcmd; 278 union SFCCTRL_DATA sfctrl; 279 280 sfcmd.d32 = 0; 281 sfcmd.b.cmd = p_dev->prog_cmd; 282 sfcmd.b.addrbits = SFC_ADDR_24BITS; 283 sfcmd.b.datasize = size; 284 sfcmd.b.rw = SFC_WRITE; 285 286 sfctrl.d32 = 0; 287 sfctrl.b.datalines = p_dev->prog_lines; 288 sfctrl.b.enbledma = 0; 289 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 290 sfctrl.b.addrlines = SFC_4BITS_LINE; 291 292 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 293 sfcmd.b.addrbits = SFC_ADDR_32BITS; 294 295 snor_write_en(); 296 297 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 298 if (ret != SFC_OK) 299 return ret; 300 301 ret = snor_wait_busy(10000); 302 303 return ret; 304 } 305 306 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 307 { 308 int ret = SFC_OK; 309 u32 page_size, len; 310 u8 *p_buf = (u8 *)p_data; 311 312 page_size = NOR_PAGE_SIZE; 313 while (size) { 314 len = page_size < size ? page_size : size; 315 ret = snor_prog_page(p_dev, addr, p_buf, len); 316 if (ret != SFC_OK) 317 return ret; 318 319 size -= len; 320 addr += len; 321 p_buf += len; 322 } 323 324 return ret; 325 } 326 327 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 328 { 329 int ret = SFC_OK; 330 int reg_index; 331 int bit_offset; 332 u8 status; 333 334 if (p_dev->manufacturer == MID_GIGADEV || 335 p_dev->manufacturer == MID_WINBOND || 336 p_dev->manufacturer == MID_XTX || 337 p_dev->manufacturer == MID_MACRONIX || 338 p_dev->manufacturer == MID_PUYA || 339 p_dev->manufacturer == MID_XMC) { 340 reg_index = p_dev->QE_bits >> 3; 341 bit_offset = p_dev->QE_bits & 0x7; 342 ret = snor_read_status(reg_index, &status); 343 if (ret != SFC_OK) 344 return ret; 345 346 if (status & (1 << bit_offset)) /* is QE bit set */ 347 return SFC_OK; 348 349 status |= (1 << bit_offset); 350 return p_dev->write_status(reg_index, status); 351 } 352 353 return ret; 354 } 355 356 #if (SNOR_4BIT_DATA_DETECT_EN) 357 static int snor_set_dlines(struct SFNOR_DEV *p_dev, enum SFC_DATA_LINES lines) 358 { 359 int ret; 360 u8 read_cmd[] = {CMD_FAST_READ_X1, CMD_FAST_READ_X2, CMD_FAST_READ_X4}; 361 362 if (lines == DATA_LINES_X4) { 363 ret = snor_enable_QE(p_dev); 364 if (ret != SFC_OK) 365 return ret; 366 } 367 368 p_dev->read_lines = lines; 369 p_dev->read_cmd = read_cmd[lines]; 370 371 if (p_dev->manufacturer == MID_GIGADEV || 372 p_dev->manufacturer == MID_WINBOND || 373 p_dev->manufacturer == MID_MACRONIX) { 374 p_dev->prog_lines = (lines != DATA_LINES_X2) ? 375 lines : DATA_LINES_X1; 376 if (lines == DATA_LINES_X1) { 377 p_dev->prog_cmd = CMD_PAGE_PROG; 378 } else { 379 if (p_dev->manufacturer == MID_GIGADEV || 380 p_dev->manufacturer == MID_WINBOND) 381 p_dev->prog_cmd = CMD_PAGE_PROG_X4; 382 else 383 p_dev->prog_cmd = CMD_PAGE_PROG_A4; 384 } 385 } 386 387 return SFC_OK; 388 } 389 #endif 390 391 static int snor_read_data(struct SFNOR_DEV *p_dev, 392 u32 addr, 393 void *p_data, 394 u32 size) 395 { 396 int ret; 397 union SFCCMD_DATA sfcmd; 398 union SFCCTRL_DATA sfctrl; 399 400 sfcmd.d32 = 0; 401 sfcmd.b.cmd = p_dev->read_cmd; 402 sfcmd.b.datasize = size; 403 sfcmd.b.addrbits = SFC_ADDR_24BITS; 404 405 sfctrl.d32 = 0; 406 sfctrl.b.datalines = p_dev->read_lines; 407 if (!(size & 0x3) && size >= 4) 408 sfctrl.b.enbledma = 0; 409 410 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 411 p_dev->read_cmd == CMD_FAST_READ_X4 || 412 p_dev->read_cmd == CMD_FAST_READ_X2 || 413 p_dev->read_cmd == CMD_FAST_4READ_X4) { 414 sfcmd.b.dummybits = 8; 415 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 416 sfcmd.b.addrbits = SFC_ADDR_32BITS; 417 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 418 sfcmd.b.dummybits = 4; 419 sfctrl.b.addrlines = SFC_4BITS_LINE; 420 } 421 422 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 423 sfcmd.b.addrbits = SFC_ADDR_32BITS; 424 425 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 426 427 return ret; 428 } 429 430 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 431 { 432 int ret = SFC_OK; 433 u32 addr, size, len; 434 u8 *p_buf = (u8 *)p_data; 435 436 if ((sec + n_sec) > p_dev->capacity) 437 return SFC_PARAM_ERR; 438 439 mutex_lock(&p_dev->lock); 440 addr = sec << 9; 441 size = n_sec << 9; 442 while (size) { 443 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 444 ret = snor_read_data(p_dev, addr, p_buf, len); 445 if (ret != SFC_OK) { 446 PRINT_SFC_E("snor_read_data %x ret= %x\n", 447 addr >> 9, ret); 448 goto out; 449 } 450 451 size -= len; 452 addr += len; 453 p_buf += len; 454 } 455 out: 456 mutex_unlock(&p_dev->lock); 457 if (!ret) 458 ret = n_sec; 459 460 return ret; 461 } 462 463 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data) 464 { 465 int ret = SFC_OK; 466 u32 len, blk_size, offset; 467 u8 *p_buf = (u8 *)p_data; 468 u32 total_sec = n_sec; 469 470 if ((sec + n_sec) > p_dev->capacity) 471 return SFC_PARAM_ERR; 472 473 mutex_lock(&p_dev->lock); 474 while (n_sec) { 475 if (sec < 512 || sec >= p_dev->capacity - 512) 476 blk_size = 8; 477 else 478 blk_size = p_dev->blk_size; 479 480 offset = (sec & (blk_size - 1)); 481 if (!offset) { 482 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 483 ERASE_SECTOR : ERASE_BLOCK64K); 484 if (ret != SFC_OK) { 485 PRINT_SFC_E("snor_erase %x ret= %x\n", 486 sec, ret); 487 goto out; 488 } 489 } 490 len = (blk_size - offset) < n_sec ? 491 (blk_size - offset) : n_sec; 492 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 493 if (ret != SFC_OK) { 494 PRINT_SFC_E("snor_prog %x ret= %x\n", sec, ret); 495 goto out; 496 } 497 n_sec -= len; 498 sec += len; 499 p_buf += len << 9; 500 } 501 out: 502 mutex_unlock(&p_dev->lock); 503 if (!ret) 504 ret = total_sec; 505 506 return ret; 507 } 508 509 static int snor_read_id(u8 *data) 510 { 511 int ret; 512 union SFCCMD_DATA sfcmd; 513 514 sfcmd.d32 = 0; 515 sfcmd.b.cmd = CMD_READ_JEDECID; 516 sfcmd.b.datasize = 3; 517 518 ret = sfc_request(sfcmd.d32, 0, 0, data); 519 520 return ret; 521 } 522 523 static int snor_read_parameter(u32 addr, u8 *data) 524 { 525 int ret; 526 union SFCCMD_DATA sfcmd; 527 528 sfcmd.d32 = 0; 529 sfcmd.b.cmd = CMD_READ_PARAMETER; 530 sfcmd.b.datasize = 1; 531 sfcmd.b.addrbits = SFC_ADDR_24BITS; 532 sfcmd.b.dummybits = 8; 533 534 ret = sfc_request(sfcmd.d32, 0, addr, data); 535 536 return ret; 537 } 538 539 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 540 { 541 return p_dev->capacity; 542 } 543 544 static void snor_print_spi_chip_info(struct SFNOR_DEV *p_dev) 545 { 546 PRINT_SFC_I("addr_mode: %x\n", p_dev->addr_mode); 547 PRINT_SFC_I("read_lines: %x\n", p_dev->read_lines); 548 PRINT_SFC_I("prog_lines: %x\n", p_dev->prog_lines); 549 PRINT_SFC_I("read_cmd: %x\n", p_dev->read_cmd); 550 PRINT_SFC_I("prog_cmd: %x\n", p_dev->prog_cmd); 551 PRINT_SFC_I("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 552 PRINT_SFC_I("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 553 } 554 555 static struct flash_info *snor_get_flash_info(u8 *flash_id) 556 { 557 u32 i; 558 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 559 560 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 561 if (spi_flash_tbl[i].id == id) 562 return &spi_flash_tbl[i]; 563 } 564 return NULL; 565 } 566 567 /* Adjust flash info in ram base on parameter */ 568 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 569 { 570 u32 addr; 571 u8 para_version; 572 573 if (spi_flash_info->id == 0xc84019) { 574 addr = 0x09; 575 snor_read_parameter(addr, ¶_version); 576 if (para_version == 0x06) { 577 spi_flash_info->QE_bits = 9; 578 spi_flash_info->prog_cmd_4 = 0x34; 579 } 580 } 581 return 0; 582 } 583 584 int snor_init(struct SFNOR_DEV *p_dev) 585 { 586 u32 i; 587 u8 id_byte[5]; 588 int err; 589 590 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 591 snor_read_id(id_byte); 592 PRINT_SFC_E("sfc nor id: %x %x %x\n", 593 id_byte[0], id_byte[1], id_byte[2]); 594 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) { 595 err = SFC_ERROR; 596 goto err_out; 597 } 598 599 p_dev->manufacturer = id_byte[0]; 600 p_dev->mem_type = id_byte[1]; 601 602 mutex_init(&p_dev->lock); 603 g_spi_flash_info = snor_get_flash_info(id_byte); 604 if (g_spi_flash_info) { 605 snor_flash_info_adjust(g_spi_flash_info); 606 p_dev->capacity = 1 << g_spi_flash_info->density; 607 p_dev->blk_size = g_spi_flash_info->block_size; 608 p_dev->page_size = NOR_SECS_PAGE; 609 p_dev->read_cmd = g_spi_flash_info->read_cmd; 610 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 611 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 612 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 613 p_dev->prog_lines = DATA_LINES_X1; 614 p_dev->read_lines = DATA_LINES_X1; 615 p_dev->QE_bits = g_spi_flash_info->QE_bits; 616 617 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 618 if (i == 0) 619 p_dev->write_status = snor_write_status; 620 else if (i == 1) 621 p_dev->write_status = snor_write_status1; 622 else if (i == 2) 623 p_dev->write_status = snor_write_status2; 624 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 625 if (snor_enable_QE(p_dev) == SFC_OK) { 626 p_dev->read_lines = DATA_LINES_X4; 627 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 628 } 629 } 630 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 631 p_dev->read_lines == DATA_LINES_X4) { 632 p_dev->prog_lines = DATA_LINES_X4; 633 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 634 } 635 636 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 637 p_dev->addr_mode = ADDR_MODE_4BYTE; 638 639 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 640 snor_enter_4byte_mode(); 641 642 goto normal_out; 643 } 644 645 for (i = 0; i < sizeof(sfnor_dev_code); i++) { 646 if (id_byte[2] == sfnor_dev_code[i]) { 647 p_dev->capacity = sfnor_capacity[i] >> 9; 648 break; 649 } 650 } 651 652 if (i >= sizeof(sfnor_dev_code)) { 653 err = SFC_ERROR; 654 goto err_out; 655 } 656 657 p_dev->QE_bits = 9; 658 p_dev->blk_size = NOR_SECS_BLK; 659 p_dev->page_size = NOR_SECS_PAGE; 660 p_dev->read_cmd = CMD_READ_DATA; 661 p_dev->prog_cmd = CMD_PAGE_PROG; 662 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 663 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 664 p_dev->write_status = snor_write_status2; 665 #if (SNOR_4BIT_DATA_DETECT_EN) 666 snor_set_dlines(p_dev, DATA_LINES_X4); 667 #endif 668 669 normal_out: 670 snor_print_spi_chip_info(p_dev); 671 672 return SFC_OK; 673 674 err_out: 675 return err; 676 } 677 678