1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6 #include <common.h> 7 #include <clk.h> 8 #include <crypto.h> 9 #include <dm.h> 10 #include <asm/io.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/clock.h> 13 #include <rockchip/crypto_v2.h> 14 #include <rockchip/crypto_v2_pka.h> 15 16 struct rockchip_crypto_priv { 17 fdt_addr_t reg; 18 struct clk clk; 19 u32 frequency; 20 char *clocks; 21 u32 *frequencies; 22 u32 nclocks; 23 u32 length; 24 void *hw_ctx; 25 }; 26 27 #define LLI_ADDR_ALIGIN_SIZE 8 28 #define DATA_ADDR_ALIGIN_SIZE 8 29 #define RK_CRYPTO_TIME_OUT 50000 /* max 50ms */ 30 31 #define RK_WHILE_TIME_OUT(condition, timeout, ret) { \ 32 u32 time_out = timeout; \ 33 while (condition) { \ 34 if (time_out-- == 0) { \ 35 printf("[%s] %d: time out!", __func__, \ 36 __LINE__); \ 37 ret = -ETIME; \ 38 break; \ 39 } \ 40 udelay(1); \ 41 } \ 42 ret = 0; \ 43 } while (0) 44 45 typedef u32 paddr_t; 46 #define virt_to_phys(addr) (((unsigned long)addr) & 0xffffffff) 47 #define phys_to_virt(addr, area) ((unsigned long)addr) 48 49 static const u8 null_hash_sha1_value[] = { 50 0xda, 0x39, 0xa3, 0xee, 0x5e, 0x6b, 0x4b, 0x0d, 51 0x32, 0x55, 0xbf, 0xef, 0x95, 0x60, 0x18, 0x90, 52 0xaf, 0xd8, 0x07, 0x09 53 }; 54 55 static const u8 null_hash_md5_value[] = { 56 0xd4, 0x1d, 0x8c, 0xd9, 0x8f, 0x00, 0xb2, 0x04, 57 0xe9, 0x80, 0x09, 0x98, 0xec, 0xf8, 0x42, 0x7e 58 }; 59 60 static const u8 null_hash_sha256_value[] = { 61 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14, 62 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24, 63 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c, 64 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55 65 }; 66 67 static const u8 null_hash_sha512_value[] = { 68 0xcf, 0x83, 0xe1, 0x35, 0x7e, 0xef, 0xb8, 0xbd, 69 0xf1, 0x54, 0x28, 0x50, 0xd6, 0x6d, 0x80, 0x07, 70 0xd6, 0x20, 0xe4, 0x05, 0x0b, 0x57, 0x15, 0xdc, 71 0x83, 0xf4, 0xa9, 0x21, 0xd3, 0x6c, 0xe9, 0xce, 72 0x47, 0xd0, 0xd1, 0x3c, 0x5d, 0x85, 0xf2, 0xb0, 73 0xff, 0x83, 0x18, 0xd2, 0x87, 0x7e, 0xec, 0x2f, 74 0x63, 0xb9, 0x31, 0xbd, 0x47, 0x41, 0x7a, 0x81, 75 0xa5, 0x38, 0x32, 0x7a, 0xf9, 0x27, 0xda, 0x3e 76 }; 77 78 fdt_addr_t crypto_base; 79 80 static void word2byte(u32 word, u8 *ch, u32 endian) 81 { 82 /* 0: Big-Endian 1: Little-Endian */ 83 if (endian == BIG_ENDIAN) { 84 ch[0] = (word >> 24) & 0xff; 85 ch[1] = (word >> 16) & 0xff; 86 ch[2] = (word >> 8) & 0xff; 87 ch[3] = (word >> 0) & 0xff; 88 } else if (endian == LITTLE_ENDIAN) { 89 ch[0] = (word >> 0) & 0xff; 90 ch[1] = (word >> 8) & 0xff; 91 ch[2] = (word >> 16) & 0xff; 92 ch[3] = (word >> 24) & 0xff; 93 } else { 94 ch[0] = 0; 95 ch[1] = 0; 96 ch[2] = 0; 97 ch[3] = 0; 98 } 99 } 100 101 static inline void clear_hash_out_reg(void) 102 { 103 int i; 104 105 /*clear out register*/ 106 for (i = 0; i < 16; i++) 107 crypto_write(0, CRYPTO_HASH_DOUT_0 + 4 * i); 108 } 109 110 static int hw_crypto_reset(void) 111 { 112 u32 tmp = 0, tmp_mask = 0; 113 int ret; 114 115 tmp = CRYPTO_SW_PKA_RESET | CRYPTO_SW_CC_RESET; 116 tmp_mask = tmp << CRYPTO_WRITE_MASK_SHIFT; 117 118 /* reset pka and crypto modules*/ 119 crypto_write(tmp | tmp_mask, CRYPTO_RST_CTL); 120 121 /* wait reset compelete */ 122 RK_WHILE_TIME_OUT(crypto_read(CRYPTO_RST_CTL), 123 RK_CRYPTO_TIME_OUT, ret); 124 return ret; 125 } 126 127 static void hw_hash_common_clean_ctx(struct rk_hash_ctx *ctx) 128 { 129 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 130 131 if (ctx->free_data_lli) 132 free(ctx->free_data_lli); 133 134 if (ctx->cur_data_lli) 135 free(ctx->cur_data_lli); 136 137 if (ctx->vir_src_addr) 138 free(ctx->vir_src_addr); 139 memset(ctx, 0x00, sizeof(*ctx)); 140 } 141 142 static void hw_hash_clean_ctx(struct rk_hash_ctx *ctx) 143 { 144 /* clear hash status */ 145 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 146 147 /* free tmp buff */ 148 if (ctx && ctx->magic == RK_HASH_CTX_MAGIC) 149 hw_hash_common_clean_ctx(ctx); 150 } 151 152 int rk_hash_init(void *hw_ctx, u32 algo) 153 { 154 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)hw_ctx; 155 u32 reg_ctrl = 0; 156 int ret; 157 158 if (!tmp_ctx) 159 return -EINVAL; 160 161 memset(tmp_ctx, 0x00, sizeof(*tmp_ctx)); 162 163 tmp_ctx->algo = algo; 164 switch (algo) { 165 case CRYPTO_MD5: 166 reg_ctrl |= CRYPTO_MODE_MD5; 167 tmp_ctx->digest_size = 16; 168 tmp_ctx->null_hash = null_hash_md5_value; 169 break; 170 case CRYPTO_SHA1: 171 reg_ctrl |= CRYPTO_MODE_SHA1; 172 tmp_ctx->digest_size = 20; 173 tmp_ctx->null_hash = null_hash_sha1_value; 174 break; 175 case CRYPTO_SHA256: 176 reg_ctrl |= CRYPTO_MODE_SHA256; 177 tmp_ctx->digest_size = 32; 178 tmp_ctx->null_hash = null_hash_sha256_value; 179 break; 180 case CRYPTO_SHA512: 181 reg_ctrl |= CRYPTO_MODE_SHA512; 182 tmp_ctx->digest_size = 64; 183 tmp_ctx->null_hash = null_hash_sha512_value; 184 break; 185 186 default: 187 ret = -EINVAL; 188 goto exit; 189 } 190 191 clear_hash_out_reg(); 192 193 /* enable hardware padding */ 194 reg_ctrl |= CRYPTO_HW_PAD_ENABLE; 195 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_HASH_CTL); 196 197 /* FIFO input and output data byte swap */ 198 /* such as B0, B1, B2, B3 -> B3, B2, B1, B0 */ 199 reg_ctrl = CRYPTO_DOUT_BYTESWAP | CRYPTO_DOIN_BYTESWAP; 200 crypto_write(reg_ctrl | CRYPTO_WRITE_MASK_ALL, CRYPTO_FIFO_CTL); 201 202 /* disable all interrupt */ 203 crypto_write(0x0, CRYPTO_DMA_INT_EN); 204 205 tmp_ctx->magic = RK_HASH_CTX_MAGIC; 206 207 return 0; 208 exit: 209 /* clear hash setting if init failed */ 210 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 211 212 return ret; 213 } 214 215 int rk_hash_update(void *ctx, const u8 *data, u32 data_len) 216 { 217 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 218 struct crypto_lli_desc *free_lli_desp = NULL; 219 struct crypto_lli_desc *lli_desp = NULL; 220 u32 tmp, temp_data_len = 0; 221 u8 *vir_src_addr = NULL; 222 int ret = -EINVAL; 223 224 if (!tmp_ctx || !data) 225 goto error; 226 227 if (tmp_ctx->digest_size == 0 || tmp_ctx->magic != RK_HASH_CTX_MAGIC) 228 goto error; 229 230 /* update will keep cache one calculate request in memmory */ 231 /* because last calculate request should calculate in final */ 232 if (!tmp_ctx->cur_data_lli) { 233 lli_desp = (struct crypto_lli_desc *) 234 memalign(DATA_ADDR_ALIGIN_SIZE, 235 sizeof(struct crypto_lli_desc)); 236 if (!lli_desp) 237 goto error; 238 239 free_lli_desp = (struct crypto_lli_desc *) 240 memalign(DATA_ADDR_ALIGIN_SIZE, 241 sizeof(struct crypto_lli_desc)); 242 if (!free_lli_desp) { 243 free(lli_desp); 244 goto error; 245 } 246 247 memset(lli_desp, 0x00, sizeof(*lli_desp)); 248 vir_src_addr = (u8 *)memalign(DATA_ADDR_ALIGIN_SIZE, 249 HASH_MAX_SIZE); 250 if (!vir_src_addr) { 251 free(lli_desp); 252 free(free_lli_desp); 253 printf("[%s] %d: memalign fail!", __func__, __LINE__); 254 goto error; 255 } 256 257 lli_desp->src_addr = (u32)virt_to_phys(vir_src_addr); 258 lli_desp->user_define = LLI_USER_CPIHER_START | 259 LLI_USER_STRING_START; 260 tmp_ctx->cur_data_lli = lli_desp; 261 tmp_ctx->free_data_lli = free_lli_desp; 262 tmp_ctx->vir_src_addr = vir_src_addr; 263 264 /* write first lli dma address to reg */ 265 crypto_write((u32)virt_to_phys(tmp_ctx->cur_data_lli), 266 CRYPTO_DMA_LLI_ADDR); 267 } 268 269 ret = 0; 270 while (data_len) { 271 lli_desp = (struct crypto_lli_desc *)tmp_ctx->cur_data_lli; 272 vir_src_addr = (u8 *)phys_to_virt((paddr_t)lli_desp->src_addr, 273 MEM_AREA_TEE_RAM); 274 if (data_len + lli_desp->src_len > HASH_MAX_SIZE) { 275 temp_data_len = HASH_MAX_SIZE - lli_desp->src_len; 276 memcpy(vir_src_addr + lli_desp->src_len, data, 277 temp_data_len); 278 data_len -= temp_data_len; 279 data += temp_data_len; 280 281 free_lli_desp = tmp_ctx->free_data_lli; 282 283 memset(free_lli_desp, 0x00, sizeof(*free_lli_desp)); 284 lli_desp->src_len = HASH_MAX_SIZE; 285 lli_desp->next_addr = (u32)virt_to_phys(free_lli_desp); 286 /* item done and pause */ 287 lli_desp->dma_ctrl = LLI_DMA_CTRL_PAUSE | 288 LLI_DMA_CTRL_SRC_DONE; 289 290 if (tmp_ctx->dma_started == 0) { 291 /* start calculate */ 292 crypto_write((CRYPTO_HASH_ENABLE << 293 CRYPTO_WRITE_MASK_SHIFT) | 294 CRYPTO_HASH_ENABLE, 295 CRYPTO_HASH_CTL); 296 tmp = CRYPTO_DMA_START; 297 tmp_ctx->dma_started = 1; 298 } else { 299 /* restart calculate */ 300 tmp = CRYPTO_DMA_RESTART; 301 } 302 303 /* flush cache */ 304 cache_op_inner(DCACHE_AREA_CLEAN, lli_desp, 305 sizeof(*lli_desp)); 306 cache_op_inner(DCACHE_AREA_CLEAN, vir_src_addr, 307 lli_desp->src_len); 308 309 /* start calculate */ 310 crypto_write(tmp << CRYPTO_WRITE_MASK_SHIFT | tmp, 311 CRYPTO_DMA_CTL); 312 313 /* wait calc ok */ 314 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 315 RK_CRYPTO_TIME_OUT, ret); 316 317 /* clear interrupt status */ 318 tmp = crypto_read(CRYPTO_DMA_INT_ST); 319 crypto_write(tmp, CRYPTO_DMA_INT_ST); 320 321 if (tmp != CRYPTO_SRC_ITEM_DONE_INT_ST && 322 tmp != CRYPTO_ZERO_LEN_INT_ST) { 323 printf("[%s] %d: CRYPTO_DMA_INT_ST = 0x%x", 324 __func__, __LINE__, tmp); 325 goto error; 326 } 327 328 /* after calc one block, swap free lli and cur lli */ 329 free_lli_desp->src_addr = lli_desp->src_addr; 330 tmp_ctx->free_data_lli = tmp_ctx->cur_data_lli; 331 tmp_ctx->cur_data_lli = free_lli_desp; 332 free_lli_desp = NULL; 333 } else { 334 /* cache first calculate request to buff */ 335 memcpy(vir_src_addr + lli_desp->src_len, 336 data, data_len); 337 lli_desp->src_len += data_len; 338 data_len = 0; 339 } 340 } 341 342 return ret; 343 344 error: 345 /* free lli list */ 346 hw_hash_clean_ctx(tmp_ctx); 347 348 return ret; 349 } 350 351 int rk_hash_final(void *ctx, u8 *digest, size_t len) 352 { 353 struct rk_hash_ctx *tmp_ctx = (struct rk_hash_ctx *)ctx; 354 struct crypto_lli_desc *lli_desp = NULL; 355 int ret = -EINVAL; 356 u32 i, tmp; 357 358 if (!digest) 359 goto exit; 360 361 if (!tmp_ctx || 362 !tmp_ctx->cur_data_lli || 363 tmp_ctx->digest_size == 0 || 364 len > tmp_ctx->digest_size || 365 tmp_ctx->magic != RK_HASH_CTX_MAGIC) { 366 goto exit; 367 } 368 369 /* to find the last block */ 370 lli_desp = (struct crypto_lli_desc *)tmp_ctx->cur_data_lli; 371 if (lli_desp->next_addr != 0) 372 goto exit; 373 374 /* if data len is zero, return null hash value immediately*/ 375 if (tmp_ctx->dma_started == 0 && 376 lli_desp->src_len == 0 && 377 !tmp_ctx->null_hash) { 378 memcpy(digest, tmp_ctx->null_hash, len); 379 ret = 0; 380 goto exit; 381 } 382 383 /* set LLI_USER_STRING_LAST to tell crypto this block is last one */ 384 lli_desp->user_define |= LLI_USER_STRING_LAST; 385 lli_desp->dma_ctrl = LLI_DMA_CTRL_LIST_DONE | LLI_DMA_CTRL_LAST; 386 cache_op_inner(DCACHE_AREA_CLEAN, lli_desp, sizeof(*lli_desp)); 387 cache_op_inner(DCACHE_AREA_CLEAN, tmp_ctx->vir_src_addr, 388 lli_desp->src_len); 389 390 if (tmp_ctx->dma_started == 0) { 391 crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) | 392 CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL); 393 crypto_write((CRYPTO_DMA_START << CRYPTO_WRITE_MASK_SHIFT) | 394 CRYPTO_DMA_START, CRYPTO_DMA_CTL); 395 } else { 396 crypto_write((CRYPTO_DMA_RESTART << CRYPTO_WRITE_MASK_SHIFT) | 397 CRYPTO_DMA_RESTART, CRYPTO_DMA_CTL); 398 tmp_ctx->dma_started = 1; 399 } 400 401 /* wait dma trans ok */ 402 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_DMA_INT_ST), 403 RK_CRYPTO_TIME_OUT, ret); 404 405 /* clear interrupt status */ 406 tmp = crypto_read(CRYPTO_DMA_INT_ST); 407 crypto_write(tmp, CRYPTO_DMA_INT_ST); 408 409 if (tmp != CRYPTO_LIST_DONE_INT_ST) { 410 ret = -EIO; 411 goto exit; 412 } 413 414 /* wait hash value ok */ 415 RK_WHILE_TIME_OUT(!crypto_read(CRYPTO_HASH_VALID), 416 RK_CRYPTO_TIME_OUT, ret); 417 418 for (i = 0; i < len / 4; i++) 419 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 420 digest + i * 4, BIG_ENDIAN); 421 422 if (len % 4) { 423 u8 tmp_buf[4]; 424 425 word2byte(crypto_read(CRYPTO_HASH_DOUT_0 + i * 4), 426 tmp_buf, BIG_ENDIAN); 427 memcpy(digest + i * 4, tmp_buf, len % 4); 428 } 429 430 /* clear hash status */ 431 crypto_write(CRYPTO_HASH_IS_VALID, CRYPTO_HASH_VALID); 432 crypto_write(CRYPTO_WRITE_MASK_ALL | 0, CRYPTO_HASH_CTL); 433 434 exit: 435 /* free lli list */ 436 hw_hash_clean_ctx(tmp_ctx); 437 438 return ret; 439 } 440 441 static u32 rockchip_crypto_capability(struct udevice *dev) 442 { 443 return CRYPTO_MD5 | 444 CRYPTO_SHA1 | 445 CRYPTO_SHA256 | 446 CRYPTO_SHA512 | 447 CRYPTO_RSA512 | 448 CRYPTO_RSA1024 | 449 CRYPTO_RSA2048 | 450 CRYPTO_RSA3072 | 451 CRYPTO_RSA4096; 452 } 453 454 static int rockchip_crypto_sha_init(struct udevice *dev, sha_context *ctx) 455 { 456 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 457 458 if (!ctx) 459 return -EINVAL; 460 461 priv->hw_ctx = malloc(sizeof(struct rk_hash_ctx)); 462 if (!priv->hw_ctx) 463 return -ENOMEM; 464 465 memset(priv->hw_ctx, 0x00, sizeof(struct rk_hash_ctx)); 466 467 return rk_hash_init(priv->hw_ctx, ctx->algo); 468 } 469 470 static int rockchip_crypto_sha_update(struct udevice *dev, 471 u32 *input, u32 len) 472 { 473 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 474 475 if (!len) 476 return -EINVAL; 477 478 return rk_hash_update(priv->hw_ctx, (u8 *)input, len); 479 } 480 481 static int rockchip_crypto_sha_final(struct udevice *dev, 482 sha_context *ctx, u8 *output) 483 { 484 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 485 u32 nbits; 486 int ret; 487 488 nbits = crypto_algo_nbits(ctx->algo); 489 490 ret = rk_hash_final(priv->hw_ctx, (u8 *)output, BITS2BYTE(nbits)); 491 if (priv->hw_ctx) { 492 free(priv->hw_ctx); 493 priv->hw_ctx = 0; 494 } 495 496 return ret; 497 } 498 499 static int rockchip_crypto_rsa_verify(struct udevice *dev, rsa_key *ctx, 500 u8 *sign, u8 *output) 501 { 502 struct mpa_num *mpa_m = NULL, *mpa_e = NULL, *mpa_n = NULL; 503 struct mpa_num *mpa_c = NULL, *mpa_result = NULL; 504 u32 n_bits, n_words; 505 u32 *rsa_result; 506 int ret; 507 508 if (!ctx) 509 return -EINVAL; 510 511 if (ctx->algo != CRYPTO_RSA512 && 512 ctx->algo != CRYPTO_RSA1024 && 513 ctx->algo != CRYPTO_RSA2048 && 514 ctx->algo != CRYPTO_RSA3072 && 515 ctx->algo != CRYPTO_RSA4096) 516 return -EINVAL; 517 518 n_bits = crypto_algo_nbits(ctx->algo); 519 n_words = BITS2WORD(n_bits); 520 521 rsa_result = malloc(BITS2BYTE(n_bits)); 522 if (!rsa_result) 523 return -ENOMEM; 524 525 memset(rsa_result, 0x00, BITS2BYTE(n_bits)); 526 527 ret = rk_mpa_alloc(&mpa_m); 528 ret |= rk_mpa_alloc(&mpa_e); 529 ret |= rk_mpa_alloc(&mpa_n); 530 ret |= rk_mpa_alloc(&mpa_c); 531 ret |= rk_mpa_alloc(&mpa_result); 532 if (ret) 533 goto exit; 534 535 mpa_m->d = (void *)sign; 536 mpa_e->d = (void *)ctx->e; 537 mpa_n->d = (void *)ctx->n; 538 mpa_c->d = (void *)ctx->c; 539 mpa_result->d = (void *)rsa_result; 540 541 mpa_m->size = n_words; 542 mpa_e->size = n_words; 543 mpa_n->size = n_words; 544 mpa_c->size = n_words; 545 mpa_result->size = n_words; 546 547 ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result); 548 if (!ret) 549 memcpy(output, rsa_result, BITS2BYTE(n_bits)); 550 551 exit: 552 free(rsa_result); 553 rk_mpa_free(&mpa_m); 554 rk_mpa_free(&mpa_e); 555 rk_mpa_free(&mpa_n); 556 rk_mpa_free(&mpa_c); 557 rk_mpa_free(&mpa_result); 558 559 return ret; 560 } 561 562 static const struct dm_crypto_ops rockchip_crypto_ops = { 563 .capability = rockchip_crypto_capability, 564 .sha_init = rockchip_crypto_sha_init, 565 .sha_update = rockchip_crypto_sha_update, 566 .sha_final = rockchip_crypto_sha_final, 567 .rsa_verify = rockchip_crypto_rsa_verify, 568 }; 569 570 /* 571 * Only use "clocks" to parse crypto clock id and use rockchip_get_clk(). 572 * Because we always add crypto node in U-Boot dts, when kernel dtb enabled : 573 * 574 * 1. There is cru phandle mismatch between U-Boot and kernel dtb; 575 * 2. CONFIG_OF_SPL_REMOVE_PROPS removes clock property; 576 */ 577 static int rockchip_crypto_ofdata_to_platdata(struct udevice *dev) 578 { 579 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 580 int len, ret = -EINVAL; 581 582 if (!dev_read_prop(dev, "clocks", &len)) { 583 printf("Can't find \"clocks\" property\n"); 584 return -EINVAL; 585 } 586 587 memset(priv, 0x00, sizeof(*priv)); 588 priv->clocks = malloc(len); 589 if (!priv->clocks) 590 return -ENOMEM; 591 592 priv->nclocks = len / sizeof(u32); 593 if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks, 594 priv->nclocks)) { 595 printf("Can't read \"clocks\" property\n"); 596 ret = -EINVAL; 597 goto exit; 598 } 599 600 if (!dev_read_prop(dev, "clock-frequency", &len)) { 601 printf("Can't find \"clock-frequency\" property\n"); 602 ret = -EINVAL; 603 goto exit; 604 } 605 606 priv->frequencies = malloc(len); 607 if (!priv->frequencies) { 608 ret = -ENOMEM; 609 goto exit; 610 } 611 612 priv->nclocks = len / sizeof(u32); 613 if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies, 614 priv->nclocks)) { 615 printf("Can't read \"clock-frequency\" property\n"); 616 ret = -EINVAL; 617 goto exit; 618 } 619 620 priv->reg = (fdt_addr_t)dev_read_addr_ptr(dev); 621 622 crypto_base = priv->reg; 623 624 return 0; 625 exit: 626 if (priv->clocks) 627 free(priv->clocks); 628 629 if (priv->frequencies) 630 free(priv->frequencies); 631 632 return ret; 633 } 634 635 static int rockchip_crypto_probe(struct udevice *dev) 636 { 637 struct rockchip_crypto_priv *priv = dev_get_priv(dev); 638 int i, ret = 0; 639 u32* clocks; 640 641 ret = rockchip_get_clk(&priv->clk.dev); 642 if (ret) { 643 printf("Failed to get clk device, ret=%d\n", ret); 644 return ret; 645 } 646 647 clocks = (u32 *)priv->clocks; 648 for (i = 0; i < priv->nclocks; i++) { 649 priv->clk.id = clocks[i * 2 + 1]; 650 ret = clk_set_rate(&priv->clk, priv->frequencies[i]); 651 if (ret < 0) { 652 printf("%s: Failed to set clk(%ld): ret=%d\n", 653 __func__, priv->clk.id, ret); 654 return ret; 655 } 656 } 657 658 hw_crypto_reset(); 659 660 return 0; 661 } 662 663 static const struct udevice_id rockchip_crypto_ids[] = { 664 { .compatible = "rockchip,px30-crypto" }, 665 { .compatible = "rockchip,rk1808-crypto" }, 666 { } 667 }; 668 669 U_BOOT_DRIVER(rockchip_crypto_v2) = { 670 .name = "rockchip_crypto_v2", 671 .id = UCLASS_CRYPTO, 672 .of_match = rockchip_crypto_ids, 673 .ops = &rockchip_crypto_ops, 674 .probe = rockchip_crypto_probe, 675 .ofdata_to_platdata = rockchip_crypto_ofdata_to_platdata, 676 .priv_auto_alloc_size = sizeof(struct rockchip_crypto_priv), 677 }; 678