1 /* 2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <amp.h> 9 #include <bidram.h> 10 #include <clk.h> 11 #include <console.h> 12 #include <debug_uart.h> 13 #include <dm.h> 14 #include <dvfs.h> 15 #include <io-domain.h> 16 #include <key.h> 17 #include <memblk.h> 18 #include <misc.h> 19 #include <of_live.h> 20 #include <ram.h> 21 #include <rockchip_debugger.h> 22 #include <syscon.h> 23 #include <sysmem.h> 24 #include <video_rockchip.h> 25 #include <asm/io.h> 26 #include <asm/gpio.h> 27 #include <dm/uclass-internal.h> 28 #include <dm/root.h> 29 #include <power/charge_display.h> 30 #include <power/regulator.h> 31 #include <asm/arch/boot_mode.h> 32 #include <asm/arch/clock.h> 33 #include <asm/arch/cpu.h> 34 #include <asm/arch/hotkey.h> 35 #include <asm/arch/param.h> 36 #include <asm/arch/periph.h> 37 #include <asm/arch/resource_img.h> 38 #include <asm/arch/rk_atags.h> 39 #include <asm/arch/vendor.h> 40 41 DECLARE_GLOBAL_DATA_PTR; 42 43 __weak int rk_board_late_init(void) 44 { 45 return 0; 46 } 47 48 __weak int rk_board_fdt_fixup(void *blob) 49 { 50 return 0; 51 } 52 53 __weak int soc_clk_dump(void) 54 { 55 return 0; 56 } 57 58 __weak int set_armclk_rate(void) 59 { 60 return 0; 61 } 62 63 __weak int rk_board_init(void) 64 { 65 return 0; 66 } 67 68 /* 69 * define serialno max length, the max length is 512 Bytes 70 * The remaining bytes are used to ensure that the first 512 bytes 71 * are valid when executing 'env_set("serial#", value)'. 72 */ 73 #define VENDOR_SN_MAX 513 74 #define CPUID_LEN 0x10 75 #define CPUID_OFF 0x07 76 77 static int rockchip_set_ethaddr(void) 78 { 79 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 80 char buf[ARP_HLEN_ASCII + 1]; 81 u8 ethaddr[ARP_HLEN]; 82 int ret; 83 84 ret = vendor_storage_read(VENDOR_LAN_MAC_ID, ethaddr, sizeof(ethaddr)); 85 if (ret > 0 && is_valid_ethaddr(ethaddr)) { 86 sprintf(buf, "%pM", ethaddr); 87 env_set("ethaddr", buf); 88 } 89 #endif 90 return 0; 91 } 92 93 static int rockchip_set_serialno(void) 94 { 95 u8 low[CPUID_LEN / 2], high[CPUID_LEN / 2]; 96 u8 cpuid[CPUID_LEN] = {0}; 97 char serialno_str[VENDOR_SN_MAX]; 98 int ret = 0, i; 99 u64 serialno; 100 101 /* Read serial number from vendor storage part */ 102 memset(serialno_str, 0, VENDOR_SN_MAX); 103 104 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 105 ret = vendor_storage_read(VENDOR_SN_ID, serialno_str, (VENDOR_SN_MAX-1)); 106 if (ret > 0) { 107 env_set("serial#", serialno_str); 108 } else { 109 #endif 110 #ifdef CONFIG_ROCKCHIP_EFUSE 111 struct udevice *dev; 112 113 /* retrieve the device */ 114 ret = uclass_get_device_by_driver(UCLASS_MISC, 115 DM_GET_DRIVER(rockchip_efuse), 116 &dev); 117 if (ret) { 118 printf("%s: could not find efuse device\n", __func__); 119 return ret; 120 } 121 122 /* read the cpu_id range from the efuses */ 123 ret = misc_read(dev, CPUID_OFF, &cpuid, sizeof(cpuid)); 124 if (ret) { 125 printf("%s: read cpuid from efuses failed, ret=%d\n", 126 __func__, ret); 127 return ret; 128 } 129 #else 130 /* generate random cpuid */ 131 for (i = 0; i < CPUID_LEN; i++) 132 cpuid[i] = (u8)(rand()); 133 #endif 134 /* Generate the serial number based on CPU ID */ 135 for (i = 0; i < 8; i++) { 136 low[i] = cpuid[1 + (i << 1)]; 137 high[i] = cpuid[i << 1]; 138 } 139 140 serialno = crc32_no_comp(0, low, 8); 141 serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; 142 snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); 143 144 env_set("serial#", serialno_str); 145 #ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION 146 } 147 #endif 148 149 return ret; 150 } 151 152 #if defined(CONFIG_USB_FUNCTION_FASTBOOT) 153 int fb_set_reboot_flag(void) 154 { 155 printf("Setting reboot to fastboot flag ...\n"); 156 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG); 157 158 return 0; 159 } 160 #endif 161 162 int board_late_init(void) 163 { 164 rockchip_set_ethaddr(); 165 rockchip_set_serialno(); 166 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 167 setup_boot_mode(); 168 #endif 169 #ifdef CONFIG_DM_CHARGE_DISPLAY 170 charge_display(); 171 #endif 172 #ifdef CONFIG_DRM_ROCKCHIP 173 rockchip_show_logo(); 174 #endif 175 soc_clk_dump(); 176 177 return rk_board_late_init(); 178 } 179 180 #ifdef CONFIG_USING_KERNEL_DTB 181 /* Here, only fixup cru phandle, pmucru is not included */ 182 static int phandles_fixup(void *fdt) 183 { 184 const char *props[] = { "clocks", "assigned-clocks" }; 185 struct udevice *dev; 186 struct uclass *uc; 187 const char *comp; 188 u32 id, nclocks; 189 u32 *clocks; 190 int phandle, ncells; 191 int off, offset; 192 int ret, length; 193 int i, j; 194 int first_phandle = -1; 195 196 phandle = -ENODATA; 197 ncells = -ENODATA; 198 199 /* fdt points to kernel dtb, getting cru phandle and "#clock-cells" */ 200 for (offset = fdt_next_node(fdt, 0, NULL); 201 offset >= 0; 202 offset = fdt_next_node(fdt, offset, NULL)) { 203 comp = fdt_getprop(fdt, offset, "compatible", NULL); 204 if (!comp) 205 continue; 206 207 /* Actually, this is not a good method to get cru node */ 208 off = strlen(comp) - strlen("-cru"); 209 if (off > 0 && !strncmp(comp + off, "-cru", 4)) { 210 phandle = fdt_get_phandle(fdt, offset); 211 ncells = fdtdec_get_int(fdt, offset, 212 "#clock-cells", -ENODATA); 213 break; 214 } 215 } 216 217 if (phandle == -ENODATA || ncells == -ENODATA) 218 return 0; 219 220 debug("%s: target cru: clock-cells:%d, phandle:0x%x\n", 221 __func__, ncells, fdt32_to_cpu(phandle)); 222 223 /* Try to fixup all cru phandle from U-Boot dtb nodes */ 224 for (id = 0; id < UCLASS_COUNT; id++) { 225 ret = uclass_get(id, &uc); 226 if (ret) 227 continue; 228 229 if (list_empty(&uc->dev_head)) 230 continue; 231 232 list_for_each_entry(dev, &uc->dev_head, uclass_node) { 233 /* Only U-Boot node go further */ 234 if (!dev_read_bool(dev, "u-boot,dm-pre-reloc")) 235 continue; 236 237 for (i = 0; i < ARRAY_SIZE(props); i++) { 238 if (!dev_read_prop(dev, props[i], &length)) 239 continue; 240 241 clocks = malloc(length); 242 if (!clocks) 243 return -ENOMEM; 244 245 /* Read "props[]" which contains cru phandle */ 246 nclocks = length / sizeof(u32); 247 if (dev_read_u32_array(dev, props[i], 248 clocks, nclocks)) { 249 free(clocks); 250 continue; 251 } 252 253 /* Fixup with kernel cru phandle */ 254 for (j = 0; j < nclocks; j += (ncells + 1)) { 255 /* 256 * Check: update pmucru phandle with cru 257 * phandle by mistake. 258 */ 259 if (first_phandle == -1) 260 first_phandle = clocks[j]; 261 262 if (clocks[j] != first_phandle) { 263 debug("WARN: %s: first cru phandle=%d, this=%d\n", 264 dev_read_name(dev), 265 first_phandle, clocks[j]); 266 continue; 267 } 268 269 clocks[j] = phandle; 270 } 271 272 /* 273 * Override live dt nodes but not fdt nodes, 274 * because all U-Boot nodes has been imported 275 * to live dt nodes, should use "dev_xxx()". 276 */ 277 dev_write_u32_array(dev, props[i], 278 clocks, nclocks); 279 free(clocks); 280 } 281 } 282 } 283 284 return 0; 285 } 286 287 int init_kernel_dtb(void) 288 { 289 ulong fdt_addr; 290 int ret; 291 292 fdt_addr = env_get_ulong("fdt_addr_r", 16, 0); 293 if (!fdt_addr) { 294 printf("No Found FDT Load Address.\n"); 295 return -1; 296 } 297 298 ret = rockchip_read_dtb_file((void *)fdt_addr); 299 if (ret < 0) { 300 printf("Read kernel dtb failed, ret=%d\n", ret); 301 return 0; 302 } 303 304 /* 305 * There is a phandle miss match between U-Boot and kernel dtb node, 306 * the typical is cru phandle, we fixup it in U-Boot live dt nodes. 307 */ 308 phandles_fixup((void *)fdt_addr); 309 310 of_live_build((void *)fdt_addr, (struct device_node **)&gd->of_root); 311 dm_scan_fdt((void *)fdt_addr, false); 312 gd->fdt_blob = (void *)fdt_addr; 313 314 /* Reserve 'reserved-memory' */ 315 ret = boot_fdt_add_sysmem_rsv_regions((void *)gd->fdt_blob); 316 if (ret) 317 return ret; 318 319 return 0; 320 } 321 #endif 322 323 void board_env_fixup(void) 324 { 325 struct memblock mem; 326 ulong u_addr_r; 327 phys_size_t end; 328 char *addr_r; 329 330 #ifdef ENV_MEM_LAYOUT_SETTINGS1 331 const char *env_addr0[] = { 332 "scriptaddr", "pxefile_addr_r", 333 "fdt_addr_r", "kernel_addr_r", "ramdisk_addr_r", 334 }; 335 const char *env_addr1[] = { 336 "scriptaddr1", "pxefile_addr1_r", 337 "fdt_addr1_r", "kernel_addr1_r", "ramdisk_addr1_r", 338 }; 339 int i; 340 341 /* 128M is a typical ram size for most platform, so as default here */ 342 if (gd->ram_size <= SZ_128M) { 343 /* Replace orignal xxx_addr_r */ 344 for (i = 0; i < ARRAY_SIZE(env_addr1); i++) { 345 addr_r = env_get(env_addr1[i]); 346 if (addr_r) 347 env_set(env_addr0[i], addr_r); 348 } 349 } 350 #endif 351 /* If bl32 is disabled, maybe kernel can be load to lower address. */ 352 if (!(gd->flags & GD_FLG_BL32_ENABLED)) { 353 addr_r = env_get("kernel_addr_no_bl32_r"); 354 if (addr_r) 355 env_set("kernel_addr_r", addr_r); 356 /* If bl32 is enlarged, we move ramdisk addr right behind it */ 357 } else { 358 mem = param_parse_optee_mem(); 359 end = mem.base + mem.size; 360 u_addr_r = env_get_ulong("ramdisk_addr_r", 16, 0); 361 if (u_addr_r >= mem.base && u_addr_r < end) 362 env_set_hex("ramdisk_addr_r", end); 363 } 364 } 365 366 static void early_download_init(void) 367 { 368 #if defined(CONFIG_PWRKEY_DNL_TRIGGER_NUM) && \ 369 (CONFIG_PWRKEY_DNL_TRIGGER_NUM > 0) 370 if (pwrkey_download_init()) 371 printf("Pwrkey download init failed\n"); 372 #endif 373 374 if (!tstc()) 375 return; 376 377 gd->console_evt = getc(); 378 if (gd->console_evt <= 0x1a) /* 'z' */ 379 printf("Hotkey: ctrl+%c\n", (gd->console_evt + 'a' - 1)); 380 381 #if (CONFIG_ROCKCHIP_BOOT_MODE_REG > 0) 382 if (is_hotkey(HK_BROM_DNL)) { 383 printf("Enter bootrom download..."); 384 flushc(); 385 writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); 386 do_reset(NULL, 0, 0, NULL); 387 printf("failed!\n"); 388 } 389 #endif 390 } 391 392 int board_init(void) 393 { 394 board_debug_uart_init(); 395 396 #ifdef CONFIG_USING_KERNEL_DTB 397 init_kernel_dtb(); 398 #endif 399 early_download_init(); 400 401 /* 402 * pmucru isn't referenced on some platforms, so pmucru driver can't 403 * probe that the "assigned-clocks" is unused. 404 */ 405 clks_probe(); 406 #ifdef CONFIG_DM_REGULATOR 407 if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR))) 408 debug("%s: Can't enable boot on regulator\n", __func__); 409 #endif 410 411 #ifdef CONFIG_ROCKCHIP_IO_DOMAIN 412 io_domain_init(); 413 #endif 414 415 set_armclk_rate(); 416 417 #ifdef CONFIG_DM_DVFS 418 dvfs_init(true); 419 #endif 420 421 return rk_board_init(); 422 } 423 424 int interrupt_debugger_init(void) 425 { 426 #ifdef CONFIG_ROCKCHIP_DEBUGGER 427 return rockchip_debugger_init(); 428 #else 429 return 0; 430 #endif 431 } 432 433 int board_fdt_fixup(void *blob) 434 { 435 /* Common fixup for DRM */ 436 #ifdef CONFIG_DRM_ROCKCHIP 437 rockchip_display_fixup(blob); 438 #endif 439 440 return rk_board_fdt_fixup(blob); 441 } 442 443 #ifdef CONFIG_ARM64_BOOT_AARCH32 444 /* 445 * Fixup MMU region attr for OP-TEE on ARMv8 CPU: 446 * 447 * What ever U-Boot is 64-bit or 32-bit mode, the OP-TEE is always 64-bit mode. 448 * 449 * Command for OP-TEE: 450 * 64-bit mode: dcache is always enabled; 451 * 32-bit mode: dcache is always disabled(Due to some unknown issue); 452 * 453 * Command for U-Boot: 454 * 64-bit mode: MMU table is static defined in rkxxx.c file, all memory 455 * regions are mapped. That's good to match OP-TEE MMU policy. 456 * 457 * 32-bit mode: MMU table is setup according to gd->bd->bi_dram[..] where 458 * the OP-TEE region has been reserved, so it can not be 459 * mapped(i.e. dcache is disabled). That's also good to match 460 * OP-TEE MMU policy. 461 * 462 * For the data coherence when communication between U-Boot and OP-TEE, U-Boot 463 * should follow OP-TEE MMU policy. 464 * 465 * Here is the special: 466 * When CONFIG_ARM64_BOOT_AARCH32 is enabled, U-Boot is 32-bit mode while 467 * OP-TEE is still 64-bit mode. U-Boot would not map MMU table for OP-TEE 468 * region(but OP-TEE requires it cacheable) so we fixup here. 469 */ 470 int board_initr_caches_fixup(void) 471 { 472 struct memblock mem; 473 474 mem = param_parse_optee_mem(); 475 if (mem.size) 476 mmu_set_region_dcache_behaviour(mem.base, mem.size, 477 DCACHE_WRITEBACK); 478 return 0; 479 } 480 #endif 481 482 void arch_preboot_os(uint32_t bootm_state) 483 { 484 if (bootm_state & BOOTM_STATE_OS_PREP) 485 hotkey_run(HK_CLI_OS_PRE); 486 } 487 488 void board_quiesce_devices(void) 489 { 490 hotkey_run(HK_CMDLINE); 491 hotkey_run(HK_CLI_OS_GO); 492 493 #ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS 494 /* Destroy atags makes next warm boot safer */ 495 atags_destroy(); 496 #endif 497 498 #if defined(CONFIG_CONSOLE_RECORD) 499 /* Print record console data */ 500 console_record_print_purge(); 501 #endif 502 } 503 504 void enable_caches(void) 505 { 506 icache_enable(); 507 dcache_enable(); 508 } 509 510 #ifdef CONFIG_LMB 511 /* 512 * Using last bi_dram[...] to initialize "bootm_low" and "bootm_mapsize". 513 * This makes lmb_alloc_base() always alloc from tail of sdram. 514 * If we don't assign it, bi_dram[0] is used by default and it may cause 515 * lmb_alloc_base() fail when bi_dram[0] range is small. 516 */ 517 void board_lmb_reserve(struct lmb *lmb) 518 { 519 char bootm_mapsize[32]; 520 char bootm_low[32]; 521 u64 start, size; 522 int i; 523 524 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 525 if (!gd->bd->bi_dram[i].size) 526 break; 527 } 528 529 start = gd->bd->bi_dram[i - 1].start; 530 size = gd->bd->bi_dram[i - 1].size; 531 532 /* 533 * 32-bit kernel: ramdisk/fdt shouldn't be loaded to highmem area(768MB+), 534 * otherwise "Unable to handle kernel paging request at virtual address ...". 535 * 536 * So that we hope limit highest address at 768M, but there comes the the 537 * problem: ramdisk is a compressed image and it expands after descompress, 538 * so it accesses 768MB+ and brings the above "Unable to handle kernel ...". 539 * 540 * We make a appointment that the highest memory address is 512MB, it 541 * makes lmb alloc safer. 542 */ 543 #ifndef CONFIG_ARM64 544 if (start >= ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) { 545 start = gd->bd->bi_dram[i - 2].start; 546 size = gd->bd->bi_dram[i - 2].size; 547 } 548 549 if ((start + size) > ((u64)CONFIG_SYS_SDRAM_BASE + SZ_512M)) 550 size = (u64)CONFIG_SYS_SDRAM_BASE + SZ_512M - start; 551 #endif 552 sprintf(bootm_low, "0x%llx", start); 553 sprintf(bootm_mapsize, "0x%llx", size); 554 env_set("bootm_low", bootm_low); 555 env_set("bootm_mapsize", bootm_mapsize); 556 } 557 #endif 558 559 #ifdef CONFIG_BIDRAM 560 int board_bidram_reserve(struct bidram *bidram) 561 { 562 struct memblock mem; 563 int ret; 564 565 /* ATF */ 566 mem = param_parse_atf_mem(); 567 ret = bidram_reserve(MEMBLK_ID_ATF, mem.base, mem.size); 568 if (ret) 569 return ret; 570 571 /* PSTORE/ATAGS/SHM */ 572 mem = param_parse_common_resv_mem(); 573 ret = bidram_reserve(MEMBLK_ID_SHM, mem.base, mem.size); 574 if (ret) 575 return ret; 576 577 /* OP-TEE */ 578 mem = param_parse_optee_mem(); 579 ret = bidram_reserve(MEMBLK_ID_OPTEE, mem.base, mem.size); 580 if (ret) 581 return ret; 582 583 return 0; 584 } 585 586 parse_fn_t board_bidram_parse_fn(void) 587 { 588 return param_parse_ddr_mem; 589 } 590 #endif 591 592 #ifdef CONFIG_ROCKCHIP_AMP 593 void cpu_secondary_init_r(void) 594 { 595 amp_cpus_on(); 596 } 597 #endif 598 599 #if defined(CONFIG_ROCKCHIP_PRELOADER_SERIAL) && \ 600 defined(CONFIG_ROCKCHIP_PRELOADER_ATAGS) 601 int board_init_f_init_serial(void) 602 { 603 struct tag *t = atags_get_tag(ATAG_SERIAL); 604 605 if (t) { 606 gd->serial.using_pre_serial = t->u.serial.enable; 607 gd->serial.addr = t->u.serial.addr; 608 gd->serial.baudrate = t->u.serial.baudrate; 609 gd->serial.id = t->u.serial.id; 610 611 debug("%s: enable=%d, addr=0x%lx, baudrate=%d, id=%d\n", 612 __func__, gd->serial.using_pre_serial, 613 gd->serial.addr, gd->serial.baudrate, 614 gd->serial.id); 615 } 616 617 return 0; 618 } 619 #endif 620 621 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 622 #include <fdt_support.h> 623 #include <usb.h> 624 #include <usb/dwc2_udc.h> 625 626 static struct dwc2_plat_otg_data otg_data = { 627 .rx_fifo_sz = 512, 628 .np_tx_fifo_sz = 16, 629 .tx_fifo_sz = 128, 630 }; 631 632 int board_usb_init(int index, enum usb_init_type init) 633 { 634 const void *blob = gd->fdt_blob; 635 const fdt32_t *reg; 636 fdt_addr_t addr; 637 int node; 638 639 /* find the usb_otg node */ 640 node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2"); 641 642 retry: 643 if (node > 0) { 644 reg = fdt_getprop(blob, node, "reg", NULL); 645 if (!reg) 646 return -EINVAL; 647 648 addr = fdt_translate_address(blob, node, reg); 649 if (addr == OF_BAD_ADDR) { 650 pr_err("Not found usb_otg address\n"); 651 return -EINVAL; 652 } 653 654 #if defined(CONFIG_ROCKCHIP_RK3288) 655 if (addr != 0xff580000) { 656 node = fdt_node_offset_by_compatible(blob, node, 657 "snps,dwc2"); 658 goto retry; 659 } 660 #endif 661 } else { 662 /* 663 * With kernel dtb support, rk3288 dwc2 otg node 664 * use the rockchip legacy dwc2 driver "dwc_otg_310" 665 * with the compatible "rockchip,rk3288_usb20_otg", 666 * and rk3368 also use the "dwc_otg_310" driver with 667 * the compatible "rockchip,rk3368-usb". 668 */ 669 #if defined(CONFIG_ROCKCHIP_RK3288) 670 node = fdt_node_offset_by_compatible(blob, -1, 671 "rockchip,rk3288_usb20_otg"); 672 #elif defined(CONFIG_ROCKCHIP_RK3368) 673 node = fdt_node_offset_by_compatible(blob, -1, 674 "rockchip,rk3368-usb"); 675 #endif 676 if (node > 0) { 677 goto retry; 678 } else { 679 pr_err("Not found usb_otg device\n"); 680 return -ENODEV; 681 } 682 } 683 684 otg_data.regs_otg = (uintptr_t)addr; 685 686 return dwc2_udc_probe(&otg_data); 687 } 688 689 int board_usb_cleanup(int index, enum usb_init_type init) 690 { 691 return 0; 692 } 693 #endif 694