1/* 2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/clock/rk3308-cru.h> 12 13/ { 14 compatible = "rockchip,rk3308"; 15 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 serial0 = &uart0; 22 serial1 = &uart1; 23 serial2 = &uart2; 24 serial3 = &uart3; 25 serial4 = &uart4; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35", "arm,armv8"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 }; 38 39 cpu1: cpu@1 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a35", "arm,armv8"; 42 reg = <0x0 0x1>; 43 enable-method = "psci"; 44 }; 45 46 cpu2: cpu@2 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a35", "arm,armv8"; 49 reg = <0x0 0x2>; 50 enable-method = "psci"; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a35", "arm,armv8"; 56 reg = <0x0 0x3>; 57 enable-method = "psci"; 58 }; 59 }; 60 61 arm-pmu { 62 compatible = "arm,cortex-a53-pmu"; 63 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 67 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 68 }; 69 70 mac_clkin: external-mac-clock { 71 compatible = "fixed-clock"; 72 clock-frequency = <50000000>; 73 clock-output-names = "mac_clkin"; 74 #clock-cells = <0>; 75 }; 76 77 display_subsystem: display-subsystem { 78 compatible = "rockchip,display-subsystem"; 79 ports = <&vop_out>; 80 status = "disabled"; 81 82 route { 83 route_rgb: route-rgb { 84 status = "okay"; 85 logo,uboot = "logo.bmp"; 86 logo,kernel = "logo_kernel.bmp"; 87 logo,mode = "center"; 88 charge_logo,mode = "center"; 89 connect = <&vop_out_rgb>; 90 }; 91 }; 92 }; 93 94 dmc: dmc@20004000 { 95 compatible = "rockchip,rk3308-dmc"; 96 reg = <0x0 0xff010000 0x0 0x10000>; 97 }; 98 99 psci { 100 compatible = "arm,psci-1.0"; 101 method = "smc"; 102 }; 103 104 timer { 105 compatible = "arm,armv8-timer"; 106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 110 clock-frequency = <24000000>; 111 }; 112 113 clocks { 114 xin24m: xin24m { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <24000000>; 118 clock-output-names = "xin24m"; 119 }; 120 }; 121 122 grf: grf@ff000000 { 123 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; 124 reg = <0x0 0xff000000 0x0 0x10000>; 125 }; 126 127 usb2phy_grf: syscon@ff008000 { 128 compatible = "rockchip,rk3308-usb2phy-grf", "syscon", 129 "simple-mfd"; 130 reg = <0x0 0xff008000 0x0 0x4000>; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 134 u2phy: usb2-phy@100 { 135 compatible = "rockchip,rk3308-usb2phy", 136 "rockchip,rk3328-usb2phy"; 137 reg = <0x100 0x10>; 138 clocks = <&cru SCLK_USBPHY_REF>; 139 clock-names = "phyclk"; 140 #clock-cells = <0>; 141 assigned-clocks = <&cru USB480M>; 142 assigned-clock-parents = <&u2phy>; 143 clock-output-names = "usb480m_phy"; 144 status = "disabled"; 145 146 u2phy_host: host-port { 147 #phy-cells = <0>; 148 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 149 interrupt-names = "linestate"; 150 status = "disabled"; 151 }; 152 153 u2phy_otg: otg-port { 154 #phy-cells = <0>; 155 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 158 interrupt-names = "otg-bvalid", "otg-id", 159 "linestate"; 160 status = "disabled"; 161 }; 162 }; 163 }; 164 165 uart0: serial@ff0a0000 { 166 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 167 reg = <0x0 0xff0a0000 0x0 0x100>; 168 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 170 clock-names = "baudclk", "apb_pclk"; 171 reg-shift = <2>; 172 reg-io-width = <4>; 173 status = "disabled"; 174 }; 175 176 uart1: serial@ff0b0000 { 177 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 178 reg = <0x0 0xff0b0000 0x0 0x100>; 179 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 181 clock-names = "baudclk", "apb_pclk"; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart2: serial@ff0c0000 { 188 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 189 reg = <0x0 0xff0c0000 0x0 0x100>; 190 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 192 clock-names = "baudclk", "apb_pclk"; 193 reg-shift = <2>; 194 reg-io-width = <4>; 195 status = "disabled"; 196 }; 197 198 uart3: serial@ff0d0000 { 199 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 200 reg = <0x0 0xff0d0000 0x0 0x100>; 201 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 203 clock-names = "baudclk", "apb_pclk"; 204 reg-shift = <2>; 205 reg-io-width = <4>; 206 status = "disabled"; 207 }; 208 209 uart4: serial@ff0e0000 { 210 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; 211 reg = <0x0 0xff0e0000 0x0 0x100>; 212 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 status = "disabled"; 218 }; 219 220 secure_otp: secure_otp@0xff2a8000 { 221 compatible = "rockchip,rk3308-secure-otp"; 222 reg = <0x0 0xff2a8000 0x0 0x4000>; 223 secure_conf = <0xff2b0004>; 224 mask_addr = <0xff540000>; 225 }; 226 227 vop: vop@ff2e0000 { 228 compatible = "rockchip,rk3308-vop"; 229 reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; 230 reg-names = "regs", "gamma_lut"; 231 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 232 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, 233 <&cru HCLK_VOP>; 234 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 235 status = "disabled"; 236 237 vop_out: port { 238 #address-cells = <1>; 239 #size-cells = <0>; 240 241 vop_out_rgb: endpoint@0 { 242 reg = <0>; 243 remote-endpoint = <&rgb_in_vop>; 244 }; 245 }; 246 }; 247 248 pwm0: pwm@ff180000 { 249 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 250 reg = <0x0 0xff180000 0x0 0x10>; 251 #pwm-cells = <3>; 252 pinctrl-names = "active"; 253 pinctrl-0 = <&pwm0_pin>; 254 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 255 clock-names = "pwm", "pclk"; 256 status = "disabled"; 257 }; 258 259 pwm1: pwm@ff180010 { 260 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 261 reg = <0x0 0xff180010 0x0 0x10>; 262 #pwm-cells = <3>; 263 pinctrl-names = "active"; 264 pinctrl-0 = <&pwm1_pin>; 265 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 266 clock-names = "pwm", "pclk"; 267 status = "disabled"; 268 }; 269 270 pwm2: pwm@ff180020 { 271 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 272 reg = <0x0 0xff180020 0x0 0x10>; 273 #pwm-cells = <3>; 274 pinctrl-names = "active"; 275 pinctrl-0 = <&pwm2_pin>; 276 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 277 clock-names = "pwm", "pclk"; 278 status = "disabled"; 279 }; 280 281 pwm3: pwm@ff180030 { 282 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; 283 reg = <0x0 0xff180030 0x0 0x10>; 284 #pwm-cells = <3>; 285 pinctrl-names = "active"; 286 pinctrl-0 = <&pwm3_pin>; 287 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; 288 clock-names = "pwm", "pclk"; 289 status = "disabled"; 290 }; 291 292 rgb: rgb { 293 compatible = "rockchip,rk3308-rgb"; 294 status = "disabled"; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&lcdc_ctl>; 297 298 ports { 299 #address-cells = <1>; 300 #size-cells = <0>; 301 302 port@0 { 303 reg = <0>; 304 305 #address-cells = <1>; 306 #size-cells = <0>; 307 308 rgb_in_vop: endpoint@0 { 309 reg = <0>; 310 remote-endpoint = <&vop_out_rgb>; 311 }; 312 }; 313 314 }; 315 }; 316 317 saradc: saradc@ff1e0000 { 318 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; 319 reg = <0x0 0xff1e0000 0x0 0x100>; 320 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 321 #io-channel-cells = <1>; 322 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 323 clock-names = "saradc", "apb_pclk"; 324 resets = <&cru SRST_SARADC_P>; 325 reset-names = "saradc-apb"; 326 status = "disabled"; 327 }; 328 329 i2s0: i2s@ff300000 { 330 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 331 reg = <0x0 0xff300000 0x0 0x10000>; 332 }; 333 334 i2s1: i2s@ff310000 { 335 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 336 reg = <0x0 0xff100000 0x0 0x10000>; 337 }; 338 339 i2s2: i2s@ff320000 { 340 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 341 reg = <0x0 0xff320000 0x0 0x10000>; 342 }; 343 344 i2s3: i2s@ff330000 { 345 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; 346 reg = <0x0 0xff330000 0x0 0x10000>; 347 }; 348 349 vad: vad@ff3c0000 { 350 compatible = "rockchip,rk3308-vad", "rockchip,vad"; 351 reg = <0x0 0xff3c0000 0x0 0x10000>, <0x0 0xfff88000 0x0 0x38000>; 352 reg-names = "vad", "vad-memory"; 353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 354 rockchip,audio-src = <0>; 355 rockchip,audio-chnl-num = <8>; 356 rockchip,audio-chnl = <0>; 357 rockchip,mode = <0>; 358 }; 359 360 usb20_otg: usb@ff400000 { 361 compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", 362 "snps,dwc2"; 363 reg = <0x0 0xff400000 0x0 0x40000>; 364 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&cru HCLK_OTG>; 366 clock-names = "otg"; 367 dr_mode = "otg"; 368 g-np-tx-fifo-size = <16>; 369 g-rx-fifo-size = <275>; 370 g-tx-fifo-size = <256 128 128 64 64 32>; 371 g-use-dma; 372 phys = <&u2phy_otg>; 373 phy-names = "usb2-phy"; 374 status = "disabled"; 375 }; 376 377 usb_host0_ehci: usb@ff440000 { 378 compatible = "generic-ehci"; 379 reg = <0x0 0xff440000 0x0 0x10000>; 380 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 382 <&u2phy>; 383 clock-names = "usbhost", "arbiter", "utmi"; 384 phys = <&u2phy_host>; 385 phy-names = "usb"; 386 status = "disabled"; 387 }; 388 389 usb_host0_ohci: usb@ff450000 { 390 compatible = "generic-ohci"; 391 reg = <0x0 0xff450000 0x0 0x10000>; 392 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, 394 <&u2phy>; 395 clock-names = "usbhost", "arbiter", "utmi"; 396 phys = <&u2phy_host>; 397 phy-names = "usb"; 398 }; 399 400 sdmmc: dwmmc@ff480000 { 401 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 402 reg = <0x0 0xff480000 0x0 0x4000>; 403 max-frequency = <150000000>; 404 bus-width = <4>; 405 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 406 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 407 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 408 fifo-depth = <0x100>; 409 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; 412 status = "disabled"; 413 }; 414 415 emmc: dwmmc@ff490000 { 416 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 417 reg = <0x0 0xff490000 0x0 0x4000>; 418 max-frequency = <150000000>; 419 bus-width = <8>; 420 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 421 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 422 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 423 fifo-depth = <0x100>; 424 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 425 status = "disabled"; 426 }; 427 428 sdio: dwmmc@ff4a0000 { 429 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; 430 reg = <0x0 0xff4a0000 0x0 0x4000>; 431 max-frequency = <150000000>; 432 bus-width = <4>; 433 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 434 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 435 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample"; 436 fifo-depth = <0x100>; 437 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 440 status = "disabled"; 441 }; 442 443 nandc: nandc@ff4b0000 { 444 compatible = "rockchip,rk-nandc"; 445 reg = <0x0 0xff4b0000 0x0 0x4000>; 446 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 447 nandc_id = <0>; 448 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; 449 clock-names = "clk_nandc", "hclk_nandc"; 450 status = "disabled"; 451 }; 452 453 454 sfc: sfc@ff4c0000 { 455 compatible = "rockchip,rksfc","rockchip,sfc"; 456 reg = <0x0 0xff4c0000 0x0 0x4000>; 457 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 459 clock-names = "clk_sfc", "hclk_sfc"; 460 status = "disabled"; 461 }; 462 463 mac: ethernet@ff4e0000 { 464 compatible = "rockchip,rk3308-mac"; 465 reg = <0x0 0xff4e0000 0x0 0x10000>; 466 rockchip,grf = <&grf>; 467 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 468 interrupt-names = "macirq"; 469 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, 470 <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, 471 <&cru SCLK_MAC>, <&cru ACLK_MAC>, 472 <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; 473 clock-names = "stmmaceth", "mac_clk_rx", 474 "mac_clk_tx", "clk_mac_ref", 475 "clk_mac_refout", "aclk_mac", 476 "pclk_mac", "clk_mac_speed"; 477 phy-mode = "rmii"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 480 resets = <&cru SRST_MAC_A>; 481 reset-names = "stmmaceth"; 482 status = "disabled"; 483 }; 484 485 cru: clock-controller@ff500000 { 486 compatible = "rockchip,rk3308-cru"; 487 reg = <0x0 0xff500000 0x0 0x1000>; 488 rockchip,grf = <&grf>; 489 #clock-cells = <1>; 490 #reset-cells = <1>; 491 }; 492 493 gic: interrupt-controller@ff580000 { 494 compatible = "arm,gic-400"; 495 #interrupt-cells = <3>; 496 #address-cells = <0>; 497 interrupt-controller; 498 499 reg = <0x0 0xff581000 0x0 0x1000>, 500 <0x0 0xff582000 0x0 0x2000>, 501 <0x0 0xff584000 0x0 0x2000>, 502 <0x0 0xff586000 0x0 0x2000>; 503 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 504 }; 505 506 pinctrl: pinctrl { 507 compatible = "rockchip,rk3308-pinctrl"; 508 rockchip,grf = <&grf>; 509 #address-cells = <2>; 510 #size-cells = <2>; 511 ranges; 512 513 gpio0: gpio0@ff220000 { 514 compatible = "rockchip,gpio-bank"; 515 reg = <0x0 0xff220000 0x0 0x100>; 516 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 517 //clocks = <&cru PCLK_GPIO0>; 518 clocks = <&xin24m>; 519 gpio-controller; 520 #gpio-cells = <2>; 521 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 }; 525 526 gpio1: gpio1@ff230000 { 527 compatible = "rockchip,gpio-bank"; 528 reg = <0x0 0xff230000 0x0 0x100>; 529 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 530 //clocks = <&cru PCLK_GPIO1>; 531 clocks = <&xin24m>; 532 gpio-controller; 533 #gpio-cells = <2>; 534 535 interrupt-controller; 536 #interrupt-cells = <2>; 537 }; 538 539 gpio2: gpio2@ff240000 { 540 compatible = "rockchip,gpio-bank"; 541 reg = <0x0 0xff240000 0x0 0x100>; 542 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 543 //clocks = <&cru PCLK_GPIO2>; 544 clocks = <&xin24m>; 545 gpio-controller; 546 #gpio-cells = <2>; 547 548 interrupt-controller; 549 #interrupt-cells = <2>; 550 }; 551 552 gpio3: gpio3@ff250000 { 553 compatible = "rockchip,gpio-bank"; 554 reg = <0x0 0xff250000 0x0 0x100>; 555 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 556 //clocks = <&cru PCLK_GPIO3>; 557 clocks = <&xin24m>; 558 gpio-controller; 559 #gpio-cells = <2>; 560 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 565 gpio4: gpio4@ff260000 { 566 compatible = "rockchip,gpio-bank"; 567 reg = <0x0 0xff260000 0x0 0x100>; 568 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 569 //clocks = <&cru PCLK_GPIO4>; 570 clocks = <&xin24m>; 571 gpio-controller; 572 #gpio-cells = <2>; 573 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 578 pcfg_pull_up: pcfg-pull-up { 579 bias-pull-up; 580 }; 581 582 pcfg_pull_down: pcfg-pull-down { 583 bias-pull-down; 584 }; 585 586 pcfg_pull_none: pcfg-pull-none { 587 bias-disable; 588 }; 589 590 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 591 bias-disable; 592 drive-strength = <2>; 593 }; 594 595 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 596 bias-pull-up; 597 drive-strength = <2>; 598 }; 599 600 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 601 bias-pull-up; 602 drive-strength = <4>; 603 }; 604 605 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 606 bias-disable; 607 drive-strength = <4>; 608 }; 609 610 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 611 bias-pull-down; 612 drive-strength = <4>; 613 }; 614 615 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 616 bias-disable; 617 drive-strength = <8>; 618 }; 619 620 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 621 bias-pull-up; 622 drive-strength = <8>; 623 }; 624 625 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 626 bias-disable; 627 drive-strength = <12>; 628 }; 629 630 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 631 bias-pull-up; 632 drive-strength = <12>; 633 }; 634 635 pcfg_pull_none_smt: pcfg-pull-none-smt { 636 bias-disable; 637 input-schmitt-enable; 638 }; 639 640 pcfg_output_high: pcfg-output-high { 641 output-high; 642 }; 643 644 pcfg_output_low: pcfg-output-low { 645 output-low; 646 }; 647 648 pcfg_input_high: pcfg-input-high { 649 bias-pull-up; 650 input-enable; 651 }; 652 653 pcfg_input: pcfg-input { 654 input-enable; 655 }; 656 657 i2c0 { 658 i2c0_xfer: i2c0-xfer { 659 rockchip,pins = 660 <1 RK_PD0 2 &pcfg_pull_none_smt>, 661 <1 RK_PD1 2 &pcfg_pull_none_smt>; 662 }; 663 }; 664 665 i2c1 { 666 i2c1_xfer: i2c1-xfer { 667 rockchip,pins = 668 <0 RK_PB3 1 &pcfg_pull_none_smt>, 669 <0 RK_PB4 1 &pcfg_pull_none_smt>; 670 }; 671 }; 672 673 i2c2 { 674 i2c2_xfer: i2c2-xfer { 675 rockchip,pins = 676 <2 RK_PA2 3 &pcfg_pull_none_smt>, 677 <2 RK_PA3 3 &pcfg_pull_none_smt>; 678 }; 679 }; 680 681 i2c3-m0 { 682 i2c3m0_xfer: i2c3m0-xfer { 683 rockchip,pins = 684 <0 RK_PB7 2 &pcfg_pull_none_smt>, 685 <0 RK_PC0 2 &pcfg_pull_none_smt>; 686 }; 687 }; 688 689 i2c3-m1 { 690 i2c3m1_xfer: i2c3m1-xfer { 691 rockchip,pins = 692 <3 RK_PB4 2 &pcfg_pull_none_smt>, 693 <3 RK_PB5 2 &pcfg_pull_none_smt>; 694 }; 695 }; 696 697 tsadc { 698 tsadc_otp_gpio: tsadc-otp-gpio { 699 rockchip,pins = 700 <0 RK_PB2 0 &pcfg_pull_none>; 701 }; 702 703 tsadc_otp_out: tsadc-otp-out { 704 rockchip,pins = 705 <0 RK_PB2 1 &pcfg_pull_none>; 706 }; 707 }; 708 709 uart0 { 710 uart0_xfer: uart0-xfer { 711 rockchip,pins = 712 <2 RK_PA1 1 &pcfg_pull_up>, 713 <2 RK_PA0 1 &pcfg_pull_none>; 714 }; 715 716 uart0_cts: uart0-cts { 717 rockchip,pins = 718 <2 RK_PA2 1 &pcfg_pull_none>; 719 }; 720 721 uart0_rts: uart0-rts { 722 rockchip,pins = 723 <2 RK_PA3 1 &pcfg_pull_none>; 724 }; 725 }; 726 727 uart1 { 728 uart1_xfer: uart1-xfer { 729 rockchip,pins = 730 <1 RK_PD1 1 &pcfg_pull_up>, 731 <1 RK_PD0 1 &pcfg_pull_none>; 732 }; 733 734 uart1_cts: uart1-cts { 735 rockchip,pins = 736 <1 RK_PC6 1 &pcfg_pull_none>; 737 }; 738 739 uart1_rts: uart1-rts { 740 rockchip,pins = 741 <1 RK_PC7 1 &pcfg_pull_none>; 742 }; 743 }; 744 745 uart2-m0 { 746 uart2m0_xfer: uart2m0-xfer { 747 rockchip,pins = 748 <1 RK_PC7 2 &pcfg_pull_up>, 749 <1 RK_PC6 2 &pcfg_pull_none>; 750 }; 751 }; 752 753 uart2-m1 { 754 uart2m1_xfer: uart2m1-xfer { 755 rockchip,pins = 756 <4 RK_PD3 2 &pcfg_pull_up>, 757 <4 RK_PD2 2 &pcfg_pull_none>; 758 }; 759 }; 760 761 uart3 { 762 uart3_xfer: uart3-xfer { 763 rockchip,pins = 764 <3 RK_PB5 4 &pcfg_pull_up>, 765 <3 RK_PB4 4 &pcfg_pull_none>; 766 }; 767 }; 768 769 uart4 { 770 771 uart4_xfer: uart4-xfer { 772 rockchip,pins = 773 <4 RK_PB1 1 &pcfg_pull_up>, 774 <4 RK_PB0 1 &pcfg_pull_none>; 775 }; 776 777 uart4_cts: uart4-cts { 778 rockchip,pins = 779 <4 RK_PA6 1 &pcfg_pull_none>; 780 781 }; 782 783 uart4_rts: uart4-rts { 784 rockchip,pins = 785 <4 RK_PA7 1 &pcfg_pull_none>; 786 }; 787 }; 788 789 spi0 { 790 spi0_clk: spi0-clk { 791 rockchip,pins = 792 <2 RK_PA2 2 &pcfg_pull_up>; 793 }; 794 795 spi0_csn0: spi0-csn0 { 796 rockchip,pins = 797 <2 RK_PA3 2 &pcfg_pull_up>; 798 }; 799 800 spi0_miso: spi0-miso { 801 rockchip,pins = 802 <2 RK_PA0 2 &pcfg_pull_up>; 803 }; 804 805 spi0_mosi: spi0-mosi { 806 rockchip,pins = 807 <2 RK_PA1 2 &pcfg_pull_up>; 808 }; 809 }; 810 811 spi1 { 812 spi1_clk: spi1-clk { 813 rockchip,pins = 814 <3 RK_PB3 3 &pcfg_pull_up>; 815 }; 816 817 spi1_csn0: spi1-csn0 { 818 rockchip,pins = 819 <3 RK_PB5 3 &pcfg_pull_up>; 820 }; 821 822 spi1_miso: spi1-miso { 823 rockchip,pins = 824 <3 RK_PB2 3 &pcfg_pull_up>; 825 }; 826 827 spi1_mosi: spi1-mosi { 828 rockchip,pins = 829 <3 RK_PB4 3 &pcfg_pull_up>; 830 }; 831 }; 832 833 spi2 { 834 spi2_clk: spi2-clk { 835 rockchip,pins = 836 <1 RK_PD0 3 &pcfg_pull_up>; 837 }; 838 839 spi2_csn0: spi2-csn0 { 840 rockchip,pins = 841 <1 RK_PD1 3 &pcfg_pull_up>; 842 }; 843 844 spi2_miso: spi2-miso { 845 rockchip,pins = 846 <1 RK_PC6 3 &pcfg_pull_up>; 847 }; 848 849 spi2_mosi: spi2-mosi { 850 rockchip,pins = 851 <1 RK_PC7 3 &pcfg_pull_up>; 852 }; 853 }; 854 855 sdmmc { 856 sdmmc_clk: sdmmc-clk { 857 rockchip,pins = 858 <4 RK_PD5 1 &pcfg_pull_none_4ma>; 859 }; 860 861 sdmmc_cmd: sdmmc-cmd { 862 rockchip,pins = 863 <4 RK_PD4 1 &pcfg_pull_up_4ma>; 864 }; 865 866 sdmmc_pwren: sdmmc-pwren { 867 rockchip,pins = 868 <4 RK_PD6 1 &pcfg_pull_none_4ma>; 869 }; 870 871 sdmmc_bus1: sdmmc-bus1 { 872 rockchip,pins = 873 <4 RK_PD0 1 &pcfg_pull_up_4ma>; 874 }; 875 876 sdmmc_bus4: sdmmc-bus4 { 877 rockchip,pins = 878 <4 RK_PD0 1 &pcfg_pull_up_4ma>, 879 <4 RK_PD1 1 &pcfg_pull_up_4ma>, 880 <4 RK_PD2 1 &pcfg_pull_up_4ma>, 881 <4 RK_PD3 1 &pcfg_pull_up_4ma>; 882 }; 883 884 sdmmc_gpio: sdmmc-gpio { 885 rockchip,pins = 886 <4 RK_PD0 0 &pcfg_pull_up_4ma>, 887 <4 RK_PD1 0 &pcfg_pull_up_4ma>, 888 <4 RK_PD2 0 &pcfg_pull_up_4ma>, 889 <4 RK_PD3 0 &pcfg_pull_up_4ma>, 890 <4 RK_PD4 0 &pcfg_pull_up_4ma>, 891 <4 RK_PD5 0 &pcfg_pull_up_4ma>, 892 <4 RK_PD6 0 &pcfg_pull_up_4ma>; 893 }; 894 }; 895 896 sdio { 897 sdio_clk: sdio-clk { 898 rockchip,pins = 899 <4 RK_PA5 1 &pcfg_pull_none_8ma>; 900 }; 901 902 sdio_cmd: sdio-cmd { 903 rockchip,pins = 904 <4 RK_PA4 1 &pcfg_pull_up_8ma>; 905 }; 906 907 sdio_pwren: sdio-pwren { 908 rockchip,pins = 909 <0 RK_PA2 1 &pcfg_pull_none_8ma>; 910 }; 911 912 sdio_wrpt: sdio-wrpt { 913 rockchip,pins = 914 <0 RK_PA1 1 &pcfg_pull_none_8ma>; 915 }; 916 917 sdio_intn: sdio-intn { 918 rockchip,pins = 919 <0 RK_PA0 1 &pcfg_pull_none_8ma>; 920 }; 921 922 sdio_bus1: sdio-bus1 { 923 rockchip,pins = 924 <4 RK_PA0 1 &pcfg_pull_up_8ma>; 925 }; 926 927 sdio_bus4: sdio-bus4 { 928 rockchip,pins = 929 <4 RK_PA0 1 &pcfg_pull_up_8ma>, 930 <4 RK_PA1 1 &pcfg_pull_up_8ma>, 931 <4 RK_PA2 1 &pcfg_pull_up_8ma>, 932 <4 RK_PA3 1 &pcfg_pull_up_8ma>; 933 }; 934 935 sdio_gpio: sdio-gpio { 936 rockchip,pins = 937 <4 RK_PA0 0 &pcfg_pull_up_4ma>, 938 <4 RK_PA1 0 &pcfg_pull_up_4ma>, 939 <4 RK_PA2 0 &pcfg_pull_up_4ma>, 940 <4 RK_PA3 0 &pcfg_pull_up_4ma>, 941 <4 RK_PA4 0 &pcfg_pull_up_4ma>, 942 <4 RK_PA5 0 &pcfg_pull_up_4ma>; 943 }; 944 }; 945 946 emmc { 947 emmc_clk: emmc-clk { 948 rockchip,pins = 949 <3 RK_PB1 2 &pcfg_pull_none_8ma>; 950 }; 951 952 emmc_cmd: emmc-cmd { 953 rockchip,pins = 954 <3 RK_PB0 2 &pcfg_pull_up_8ma>; 955 }; 956 957 emmc_pwren: emmc-pwren { 958 rockchip,pins = 959 <3 RK_PB3 2 &pcfg_pull_none>; 960 }; 961 962 emmc_rstn: emmc-rstn { 963 rockchip,pins = 964 <3 RK_PB2 2 &pcfg_pull_none>; 965 }; 966 967 emmc_bus1: emmc-bus1 { 968 rockchip,pins = 969 <3 RK_PA0 2 &pcfg_pull_up_8ma>; 970 }; 971 972 emmc_bus4: emmc-bus4 { 973 rockchip,pins = 974 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 975 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 976 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 977 <3 RK_PA3 2 &pcfg_pull_up_8ma>; 978 }; 979 980 emmc_bus8: emmc-bus8 { 981 rockchip,pins = 982 <3 RK_PA0 2 &pcfg_pull_up_8ma>, 983 <3 RK_PA1 2 &pcfg_pull_up_8ma>, 984 <3 RK_PA2 2 &pcfg_pull_up_8ma>, 985 <3 RK_PA3 2 &pcfg_pull_up_8ma>, 986 <3 RK_PA4 2 &pcfg_pull_up_8ma>, 987 <3 RK_PA5 2 &pcfg_pull_up_8ma>, 988 <3 RK_PA6 2 &pcfg_pull_up_8ma>, 989 <3 RK_PA7 2 &pcfg_pull_up_8ma>; 990 }; 991 }; 992 993 flash { 994 flash_csn0: flash-csn0 { 995 rockchip,pins = 996 <3 RK_PB5 1 &pcfg_pull_none>; 997 }; 998 999 flash_rdy: flash-rdy { 1000 rockchip,pins = 1001 <3 RK_PB4 1 &pcfg_pull_none>; 1002 }; 1003 1004 flash_ale: flash-ale { 1005 rockchip,pins = 1006 <3 RK_PB3 1 &pcfg_pull_none>; 1007 }; 1008 1009 flash_cle: flash-cle { 1010 rockchip,pins = 1011 <3 RK_PB1 1 &pcfg_pull_none>; 1012 }; 1013 1014 flash_wrn: flash-wrn { 1015 rockchip,pins = 1016 <3 RK_PB0 1 &pcfg_pull_none>; 1017 }; 1018 1019 flash_rdn: flash-rdn { 1020 rockchip,pins = 1021 <3 RK_PB2 1 &pcfg_pull_none>; 1022 }; 1023 1024 flash_bus8: flash-bus8 { 1025 rockchip,pins = 1026 <3 RK_PA0 1 &pcfg_pull_up_12ma>, 1027 <3 RK_PA1 1 &pcfg_pull_up_12ma>, 1028 <3 RK_PA2 1 &pcfg_pull_up_12ma>, 1029 <3 RK_PA3 1 &pcfg_pull_up_12ma>, 1030 <3 RK_PA4 1 &pcfg_pull_up_12ma>, 1031 <3 RK_PA5 1 &pcfg_pull_up_12ma>, 1032 <3 RK_PA6 1 &pcfg_pull_up_12ma>, 1033 <3 RK_PA7 1 &pcfg_pull_up_12ma>; 1034 }; 1035 }; 1036 1037 pwm0 { 1038 pwm0_pin: pwm0-pin { 1039 rockchip,pins = 1040 <0 RK_PB5 1 &pcfg_pull_none>; 1041 }; 1042 }; 1043 1044 pwm1 { 1045 pwm1_pin: pwm1-pin { 1046 rockchip,pins = 1047 <0 RK_PB6 1 &pcfg_pull_none>; 1048 }; 1049 }; 1050 1051 pwm2 { 1052 pwm2_pin: pwm2-pin { 1053 rockchip,pins = 1054 <0 RK_PB7 1 &pcfg_pull_none>; 1055 }; 1056 }; 1057 1058 pwm3 { 1059 pwm3_pin: pwm3-pin { 1060 rockchip,pins = 1061 <0 RK_PC0 1 &pcfg_pull_none>; 1062 }; 1063 }; 1064 1065 gmac { 1066 rmii_pins: rmii-pins { 1067 rockchip,pins = 1068 /* mac_txen */ 1069 <1 RK_PC1 3 &pcfg_pull_none_12ma>, 1070 /* mac_txd1 */ 1071 <1 RK_PC3 3 &pcfg_pull_none_12ma>, 1072 /* mac_txd0 */ 1073 <1 RK_PC2 3 &pcfg_pull_none_12ma>, 1074 /* mac_rxd0 */ 1075 <1 RK_PC4 3 &pcfg_pull_none>, 1076 /* mac_rxd1 */ 1077 <1 RK_PC5 3 &pcfg_pull_none>, 1078 /* mac_rxer */ 1079 <1 RK_PB7 3 &pcfg_pull_none>, 1080 /* mac_rxdv */ 1081 <1 RK_PC0 3 &pcfg_pull_none>, 1082 /* mac_mdio */ 1083 <1 RK_PB6 3 &pcfg_pull_none>, 1084 /* mac_mdc */ 1085 <1 RK_PB5 3 &pcfg_pull_none>; 1086 }; 1087 1088 mac_refclk_12ma: mac-refclk-12ma { 1089 rockchip,pins = 1090 <1 RK_PB4 3 &pcfg_pull_none_12ma>; 1091 }; 1092 1093 mac_refclk: mac-refclk { 1094 rockchip,pins = 1095 <1 RK_PB4 3 &pcfg_pull_none>; 1096 }; 1097 1098 }; 1099 1100 lcdc { 1101 lcdc_ctl: lcdc-ctl { 1102 rockchip,pins = 1103 /* dclk */ 1104 <1 RK_PA0 RK_FUNC_1 &pcfg_pull_none>, 1105 /* hsync */ 1106 <1 RK_PA1 RK_FUNC_1 &pcfg_pull_none>, 1107 /* vsync */ 1108 <1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>, 1109 /* den */ 1110 <1 RK_PA3 RK_FUNC_1 &pcfg_pull_none>, 1111 /* d0 */ 1112 <1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>, 1113 /* d1 */ 1114 <1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>, 1115 /* d2 */ 1116 <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none>, 1117 /* d3 */ 1118 <1 RK_PA7 RK_FUNC_1 &pcfg_pull_none>, 1119 /* d4 */ 1120 <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>, 1121 /* d5 */ 1122 <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>, 1123 /* d6 */ 1124 <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>, 1125 /* d7 */ 1126 <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>, 1127 /* d8 */ 1128 <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none>, 1129 /* d9 */ 1130 <1 RK_PB5 RK_FUNC_1 &pcfg_pull_none>, 1131 /* d10 */ 1132 <1 RK_PB6 RK_FUNC_1 &pcfg_pull_none>, 1133 /* d11 */ 1134 <1 RK_PB7 RK_FUNC_1 &pcfg_pull_none>, 1135 /* d12 */ 1136 <1 RK_PC0 RK_FUNC_1 &pcfg_pull_none>, 1137 /* d13 */ 1138 <1 RK_PC1 RK_FUNC_1 &pcfg_pull_none>, 1139 /* d14 */ 1140 <1 RK_PC2 RK_FUNC_1 &pcfg_pull_none>, 1141 /* d15 */ 1142 <1 RK_PC3 RK_FUNC_1 &pcfg_pull_none>, 1143 /* d16 */ 1144 <1 RK_PC4 RK_FUNC_1 &pcfg_pull_none>, 1145 /* d17 */ 1146 <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>; 1147 }; 1148 }; 1149 }; 1150}; 1151
