1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFNOR_H 8 #define _SFNOR_H 9 10 #include "sfc.h" 11 12 /* Four line data transmission detection */ 13 #define SNOR_4BIT_DATA_DETECT_EN 0 14 15 #define NOR_PAGE_SIZE 256 16 #define NOR_BLOCK_SIZE (64 * 1024) 17 #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 18 #define NOR_SECS_PAGE 4 19 20 #define FEA_READ_STATUE_MASK (0x3 << 0) 21 #define FEA_STATUE_MODE1 0 22 #define FEA_STATUE_MODE2 1 23 #define FEA_4BIT_READ BIT(2) 24 #define FEA_4BIT_PROG BIT(3) 25 #define FEA_4BYTE_ADDR BIT(4) 26 #define FEA_4BYTE_ADDR_MODE BIT(5) 27 28 /*Manufactory ID*/ 29 #define MID_WINBOND 0xEF 30 #define MID_GIGADEV 0xC8 31 #define MID_MICRON 0x2C 32 #define MID_MACRONIX 0xC2 33 #define MID_SPANSION 0x01 34 #define MID_EON 0x1C 35 #define MID_ST 0x20 36 #define MID_XTX 0x0B 37 #define MID_PUYA 0x85 38 #define MID_XMC 0x20 39 40 /*Command Set*/ 41 #define CMD_READ_JEDECID (0x9F) 42 #define CMD_READ_DATA (0x03) 43 #define CMD_READ_STATUS (0x05) 44 #define CMD_WRITE_STATUS (0x01) 45 #define CMD_PAGE_PROG (0x02) 46 #define CMD_SECTOR_ERASE (0x20) 47 #define CMD_BLK64K_ERASE (0xD8) 48 #define CMD_BLK32K_ERASE (0x52) 49 #define CMD_CHIP_ERASE (0xC7) 50 #define CMD_WRITE_EN (0x06) 51 #define CMD_WRITE_DIS (0x04) 52 #define CMD_PAGE_READ (0x13) 53 #define CMD_GET_FEATURE (0x0F) 54 #define CMD_SET_FEATURE (0x1F) 55 #define CMD_PROG_LOAD (0x02) 56 #define CMD_PROG_EXEC (0x10) 57 #define CMD_BLOCK_ERASE (0xD8) 58 #define CMD_READ_DATA_X2 (0x3B) 59 #define CMD_READ_DATA_X4 (0x6B) 60 #define CMD_PROG_LOAD_X4 (0x32) 61 #define CMD_READ_STATUS2 (0x35) 62 #define CMD_READ_STATUS3 (0x15) 63 #define CMD_WRITE_STATUS2 (0x31) 64 #define CMD_WRITE_STATUS3 (0x11) 65 /* X1 cmd, X1 addr, X1 data */ 66 #define CMD_FAST_READ_X1 (0x0B) 67 /* X1 cmd, X1 addr, X2 data */ 68 #define CMD_FAST_READ_X2 (0x3B) 69 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 70 #define CMD_FAST_READ_X4 (0x6B) 71 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 72 #define CMD_FAST_4READ_X4 (0x6C) 73 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 74 #define CMD_FAST_READ_A4 (0xEB) 75 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 76 #define CMD_PAGE_PROG_X4 (0x32) 77 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 78 #define CMD_PAGE_PROG_A4 (0x38) 79 #define CMD_RESET_NAND (0xFF) 80 #define CMD_ENTER_4BYTE_MODE (0xB7) 81 #define CMD_EXIT_4BYTE_MODE (0xE9) 82 #define CMD_ENABLE_RESER (0x66) 83 #define CMD_RESET_DEVICE (0x99) 84 #define CMD_READ_PARAMETER (0x5A) 85 86 enum NOR_ERASE_TYPE { 87 ERASE_SECTOR = 0, 88 ERASE_BLOCK64K, 89 ERASE_CHIP 90 }; 91 92 enum SNOR_IO_MODE { 93 IO_MODE_SPI = 0, 94 IO_MODE_QPI 95 }; 96 97 enum SNOR_READ_MODE { 98 READ_MODE_NOMAL = 0, 99 READ_MODE_FAST 100 }; 101 102 enum SNOR_ADDR_MODE { 103 ADDR_MODE_3BYTE = 0, 104 ADDR_MODE_4BYTE 105 }; 106 107 typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 108 109 struct SFNOR_DEV { 110 u32 capacity; 111 u8 manufacturer; 112 u8 mem_type; 113 u16 page_size; 114 u32 blk_size; 115 116 u8 read_cmd; 117 u8 prog_cmd; 118 u8 sec_erase_cmd; 119 u8 blk_erase_cmd; 120 u8 QE_bits; 121 122 enum SNOR_READ_MODE read_mode; 123 enum SNOR_ADDR_MODE addr_mode; 124 enum SNOR_IO_MODE io_mode; 125 126 enum SFC_DATA_LINES read_lines; 127 enum SFC_DATA_LINES prog_lines; 128 129 SNOR_WRITE_STATUS write_status; 130 struct mutex lock; /* to lock this object */ 131 }; 132 133 struct flash_info { 134 u32 id; 135 136 u8 block_size; 137 u8 sector_size; 138 u8 read_cmd; 139 u8 prog_cmd; 140 141 u8 read_cmd_4; 142 u8 prog_cmd_4; 143 u8 sector_erase_cmd; 144 u8 block_erase_cmd; 145 146 u8 feature; 147 u8 density; /* (1 << density) sectors*/ 148 u8 QE_bits; 149 u8 reserved2; 150 }; 151 152 int snor_init(struct SFNOR_DEV *p_dev); 153 u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 154 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 155 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data); 156 157 #endif 158