1 /* 2 * SFC driver for rockchip 3 * 4 * (C) Copyright 2017 Rockchip Electronics Co., Ltd 5 * Yifeng.zhao, Software Engineering, <zhao0116@gmail.com>. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <bouncebuf.h> 12 #include <clk.h> 13 #include <dm.h> 14 #include <dt-structs.h> 15 #include <errno.h> 16 #include <spi.h> 17 #include <linux/errno.h> 18 #include <asm/io.h> 19 #include <asm/arch/clock.h> 20 #include <asm/arch/periph.h> 21 #include <dm/pinctrl.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #ifdef SFC_DEBUG 26 #define SFC_DBG printf 27 #else 28 #define SFC_DBG(args...) 29 #endif 30 31 struct rockchip_sfc_reg { 32 u32 ctrl; 33 u32 imr; 34 u32 iclr; 35 u32 ftlr; 36 u32 rcvr; 37 u32 ax; 38 u32 abit; 39 u32 isr; 40 u32 fsr; 41 u32 sr; 42 u32 risr; 43 u32 reserved[21]; 44 u32 dmatr; 45 u32 dmaaddr; 46 u32 reserved1[30]; 47 u32 cmd; 48 u32 addr; 49 u32 data; 50 }; 51 52 check_member(rockchip_sfc_reg, data, 0x108); 53 54 /*SFC_CTRL*/ 55 #define SFC_DATA_WIDTH_SHIFT 12 56 #define SFC_DATA_WIDTH_MASK GENMASK(13, 12) 57 #define SFC_ADDR_WIDTH_SHIFT 10 58 #define SFC_ADDR_WIDTH_MASK GENMASK(11, 10) 59 #define SFC_CMD_WIDTH_SHIFT 8 60 #define SFC_CMD_WIDTH_MASK GENMASK(9, 8) 61 #define SFC_DATA_SHIFT_NEGETIVE BIT(1) 62 63 /*SFC_CMD*/ 64 #define SFC_DUMMY_BITS_SHIFT 8 65 #define SFC_RW_SHIFT 12 66 #define SFC_WR 1 67 #define SFC_RD 0 68 #define SFC_ADDR_BITS_SHIFT 14 69 #define SFC_ADDR_BITS_MASK GENMASK(15, 14) 70 #define SFC_ADDR_0BITS 0 71 #define SFC_ADDR_24BITS 1 72 #define SFC_ADDR_32BITS 2 73 #define SFC_ADDR_XBITS 3 74 #define SFC_TRB_SHIFT (16) 75 #define SFC_TRB_MASK GENMASK(29, 16) 76 77 /* Dma start trigger signal. Auto cleared after write */ 78 #define SFC_DMA_START BIT(0) 79 80 #define SFC_RESET BIT(0) 81 82 /*SFC_FSR*/ 83 #define SFC_RXLV_SHIFT (16) 84 #define SFC_RXLV_MASK GENMASK(20, 16) 85 #define SFC_TXLV_SHIFT (8) 86 #define SFC_TXLV_MASK GENMASK(12, 8) 87 #define SFC_RX_FULL BIT(3) /* rx fifo full */ 88 #define SFC_RX_EMPTY BIT(2) /* rx fifo empty */ 89 #define SFC_TX_EMPTY BIT(1) /* tx fifo empty */ 90 #define SFC_TX_FULL BIT(0) /* tx fifo full */ 91 92 #define SFC_BUSY BIT(0) /* sfc busy flag */ 93 94 /*SFC_RISR*/ 95 #define DMA_FINISH_INT BIT(7) /* dma interrupt */ 96 #define SPI_ERR_INT BIT(6) /* Nspi error interrupt */ 97 #define AHB_ERR_INT BIT(5) /* Ahb bus error interrupt */ 98 #define TRANS_FINISH_INT BIT(4) /* Transfer finish interrupt */ 99 #define TX_EMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 100 #define TX_OF_INT BIT(2) /* Tx fifo overflow interrupt */ 101 #define RX_UF_INT BIT(1) /* Rx fifo underflow interrupt */ 102 #define RX_FULL_INT BIT(0) /* Rx fifo full interrupt */ 103 104 #define SFC_MAX_TRB (512 * 31) 105 106 enum rockchip_sfc_if_type { 107 IF_TYPE_STD, 108 IF_TYPE_DUAL, 109 IF_TYPE_QUAD, 110 }; 111 112 struct rockchip_sfc_platdata { 113 s32 frequency; 114 void *base; 115 }; 116 117 struct rockchip_sfc { 118 struct rockchip_sfc_reg *regbase; 119 struct clk clk; 120 unsigned int max_freq; 121 unsigned int mode; 122 unsigned int speed_hz; 123 u32 cmd; 124 u32 addr; 125 u8 addr_bits; 126 u8 dummy_bits; 127 u8 rw; 128 u32 trb; 129 }; 130 131 static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus) 132 { 133 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 134 struct rockchip_sfc *sfc = dev_get_priv(bus); 135 ofnode subnode; 136 int ret; 137 138 plat->base = dev_read_addr_ptr(bus); 139 ret = clk_get_by_index(bus, 0, &sfc->clk); 140 if (ret < 0) { 141 printf("Could not get clock for %s: %d\n", bus->name, ret); 142 return ret; 143 } 144 145 subnode = dev_read_first_subnode(bus); 146 if (!ofnode_valid(subnode)) { 147 printf("Error: subnode with SPI flash config missing!\n"); 148 return -ENODEV; 149 } 150 151 plat->frequency = ofnode_read_u32_default(subnode, "spi-max-frequency", 152 100000000); 153 154 return 0; 155 } 156 157 static int rockchip_sfc_probe(struct udevice *bus) 158 { 159 struct rockchip_sfc_platdata *plat = dev_get_platdata(bus); 160 struct rockchip_sfc *sfc = dev_get_priv(bus); 161 162 sfc->regbase = (struct rockchip_sfc_reg *)plat->base; 163 164 return 0; 165 } 166 167 static int rockchip_sfc_reset(struct rockchip_sfc *sfc) 168 { 169 struct rockchip_sfc_reg *regs = sfc->regbase; 170 int tbase = get_timer(0); 171 u32 rcvr; 172 int ret = 0; 173 174 writel(SFC_RESET, ®s->rcvr); 175 do { 176 rcvr = readl(®s->rcvr); 177 if (get_timer(tbase) > 1000) { 178 debug("sfc reset timeout\n"); 179 ret = -ETIMEDOUT; 180 break; 181 } 182 udelay(1); 183 } while (rcvr); 184 185 writel(0xFFFFFFFF, ®s->iclr); 186 187 debug("sfc reset\n"); 188 189 return ret; 190 } 191 192 /* The SFC_CTRL register is a global control register, 193 * when the controller is in busy state(SFC_SR), 194 * SFC_CTRL cannot be set. 195 */ 196 static int rockchip_sfc_wait_idle(struct rockchip_sfc *sfc, 197 u32 timeout_ms) 198 { 199 struct rockchip_sfc_reg *regs = sfc->regbase; 200 unsigned long tbase = get_timer(0); 201 u32 sr, fsr; 202 203 while (1) { 204 sr = readl(®s->sr); 205 fsr = readl(®s->fsr); 206 if ((fsr & SFC_TX_EMPTY) && 207 (fsr & SFC_RX_EMPTY) && 208 !(sr & SFC_BUSY)) 209 break; 210 if (get_timer(tbase) > timeout_ms) { 211 printf("waite sfc idle timeout(sr:0x%08x fsr:0x%08x)\n", 212 sr, fsr); 213 rockchip_sfc_reset(sfc); 214 return -ETIMEDOUT; 215 } 216 udelay(100); 217 } 218 219 return 0; 220 } 221 222 static u8 rockchip_sfc_get_if_type(struct rockchip_sfc *sfc) 223 { 224 int type = IF_TYPE_STD; 225 226 if (sfc->rw == SFC_WR) { 227 if (sfc->mode & SPI_TX_QUAD) 228 type = IF_TYPE_QUAD; 229 else if (sfc->mode & SPI_TX_DUAL) 230 type = IF_TYPE_DUAL; 231 else 232 type = IF_TYPE_STD; 233 } else { 234 if (sfc->mode & SPI_RX_QUAD) 235 type = IF_TYPE_QUAD; 236 else if (sfc->mode & SPI_RX_DUAL) 237 type = IF_TYPE_DUAL; 238 else 239 type = IF_TYPE_STD; 240 } 241 242 return type; 243 } 244 245 static void rockchip_sfc_setup_xfer(struct rockchip_sfc *sfc, u32 trb) 246 { 247 struct rockchip_sfc_reg *regs = sfc->regbase; 248 u32 val = 0x02; 249 u8 data_width = IF_TYPE_STD; 250 251 switch (sfc->addr_bits) { 252 case 0: 253 sfc->addr_bits = SFC_ADDR_0BITS; 254 break; 255 case 8: 256 sfc->addr_bits = SFC_ADDR_XBITS; 257 writel(7, ®s->abit); 258 break; 259 case 16: 260 sfc->addr_bits = SFC_ADDR_XBITS; 261 writel(15, ®s->abit); 262 break; 263 case 24: 264 sfc->addr_bits = SFC_ADDR_24BITS; 265 break; 266 case 32: 267 sfc->addr_bits = SFC_ADDR_32BITS; 268 break; 269 default: 270 pr_err("%s addr-bits error %d\n", __func__, sfc->addr_bits); 271 return; 272 } 273 SFC_DBG("--- sfc.addr_bit %x\n", sfc->addr_bits); 274 275 if (sfc->addr_bits == SFC_ADDR_24BITS || 276 sfc->addr_bits == SFC_ADDR_32BITS) 277 data_width = rockchip_sfc_get_if_type(sfc); 278 279 val |= (data_width << SFC_DATA_WIDTH_SHIFT); 280 281 rockchip_sfc_wait_idle(sfc, 10); 282 283 SFC_DBG("--- sfc.ctrl %x\n", val); 284 writel(val, ®s->ctrl); 285 286 val = sfc->cmd; 287 val |= trb << SFC_TRB_SHIFT; 288 val |= sfc->rw << SFC_RW_SHIFT; 289 val |= sfc->addr_bits << SFC_ADDR_BITS_SHIFT; 290 val |= sfc->dummy_bits << SFC_DUMMY_BITS_SHIFT; 291 292 SFC_DBG("--- sfc.cmd %x\n", val); 293 writel(val, ®s->cmd); 294 295 if (sfc->addr_bits & SFC_ADDR_XBITS) { 296 SFC_DBG("--- sfc.addr %x\n", sfc->addr); 297 writel(sfc->addr, ®s->addr); 298 } 299 } 300 301 static int rockchip_sfc_dma_xfer(struct rockchip_sfc *sfc, void *buffer, size_t trb) 302 { 303 struct rockchip_sfc_reg *regs = sfc->regbase; 304 struct bounce_buffer bb; 305 unsigned int bb_flags; 306 int timeout = 1000; 307 int ret = 0; 308 int risr; 309 unsigned long tbase; 310 311 if (sfc->rw == SFC_WR) 312 bb_flags = GEN_BB_READ; 313 else 314 bb_flags = GEN_BB_WRITE; 315 316 ret = bounce_buffer_start(&bb, buffer, trb, bb_flags); 317 if (ret) 318 return ret; 319 320 rockchip_sfc_setup_xfer(sfc, bb.len_aligned); 321 322 writel(0xFFFFFFFF, ®s->iclr); 323 writel((unsigned long)bb.bounce_buffer, ®s->dmaaddr); 324 writel(SFC_DMA_START, ®s->dmatr); 325 326 tbase = get_timer(0); 327 do { 328 udelay(1); 329 risr = readl(®s->risr); 330 if (get_timer(tbase) > timeout) { 331 debug("dma timeout\n"); 332 ret = -ETIMEDOUT; 333 break; 334 } 335 } while (!(risr & TRANS_FINISH_INT)); 336 337 writel(0xFFFFFFFF, ®s->iclr); 338 339 bounce_buffer_stop(&bb); 340 341 return ret; 342 } 343 344 static int rockchip_sfc_wait_fifo_ready(struct rockchip_sfc *sfc, int rw, 345 u32 timeout) 346 { 347 struct rockchip_sfc_reg *regs = sfc->regbase; 348 unsigned long tbase = get_timer(0); 349 u8 level; 350 u32 fsr; 351 352 do { 353 fsr = readl(®s->fsr); 354 if (rw == SFC_WR) 355 level = (fsr & SFC_TXLV_MASK) >> SFC_TXLV_SHIFT; 356 else 357 level = (fsr & SFC_RXLV_MASK) >> SFC_RXLV_SHIFT; 358 if (get_timer(tbase) > timeout) 359 return -ETIMEDOUT; 360 udelay(1); 361 } while (!level); 362 363 return level; 364 } 365 366 static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 367 { 368 struct rockchip_sfc_reg *regs = sfc->regbase; 369 u32 bytes = len & 0x3; 370 u32 words = len >> 2; 371 int tx_level = 0; 372 u32 val = 0; 373 u8 count; 374 375 while (words) { 376 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 377 if (tx_level <= 0) 378 return tx_level; 379 count = min(words, (u32)tx_level); 380 writesl(®s->data, buf, count); 381 buf += count; 382 words -= count; 383 } 384 385 /* handle the last non 4byte aligned bytes */ 386 if (bytes) { 387 tx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_WR, 1000); 388 if (tx_level <= 0) 389 return tx_level; 390 memcpy(&val, buf, bytes); 391 writel(val, ®s->data); 392 } 393 394 return 0; 395 } 396 397 static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u32 *buf, u32 len) 398 { 399 struct rockchip_sfc_reg *regs = sfc->regbase; 400 u32 bytes = len & 0x3; 401 u32 words = len >> 2; 402 int rx_level = 0; 403 u32 count; 404 u32 val; 405 406 while (words) { 407 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 408 if (rx_level <= 0) 409 return rx_level; 410 count = min(words, (u32)rx_level); 411 readsl(®s->data, buf, count); 412 buf += count; 413 words -= count; 414 } 415 416 /* handle the last non 4 bytes aligned bytes */ 417 if (bytes) { 418 rx_level = rockchip_sfc_wait_fifo_ready(sfc, SFC_RD, 1000); 419 if (rx_level <= 0) 420 return rx_level; 421 val = readl(®s->data); 422 memcpy(buf, &val, bytes); 423 } 424 425 return 0; 426 } 427 428 static int rockchip_sfc_pio_xfer(struct rockchip_sfc *sfc, void *buf, u32 len) 429 { 430 int ret = 0; 431 432 rockchip_sfc_setup_xfer(sfc, len); 433 434 if (len) { 435 if (sfc->rw == SFC_WR) 436 ret = rockchip_sfc_write_fifo(sfc, (u32 *)buf, len); 437 else 438 ret = rockchip_sfc_read_fifo(sfc, (u32 *)buf, len); 439 } 440 441 return ret; 442 } 443 444 static int rockchip_sfc_read(struct rockchip_sfc *sfc, u32 offset, 445 void *buf, size_t len) 446 { 447 u32 dma_trans; 448 u32 trb; 449 u8 bytes; 450 int ret; 451 452 if (len >= ARCH_DMA_MINALIGN) { 453 bytes = len & (ARCH_DMA_MINALIGN - 1); 454 dma_trans = len - bytes; 455 } else { 456 dma_trans = 0; 457 bytes = len; 458 } 459 460 while (dma_trans) { 461 trb = min_t(size_t, dma_trans, SFC_MAX_TRB); 462 ret = rockchip_sfc_dma_xfer(sfc, buf, trb); 463 if (ret < 0) 464 return ret; 465 dma_trans -= trb; 466 sfc->addr += trb; 467 buf += trb; 468 } 469 470 /* 471 * transfer the last non dma anligned byte by pio mode 472 */ 473 if (bytes) 474 ret = rockchip_sfc_pio_xfer(sfc, buf, bytes); 475 476 return 0; 477 } 478 479 static int rockchip_sfc_write(struct rockchip_sfc *sfc, u32 offset, 480 void *buf, size_t len) 481 { 482 if (len > SFC_MAX_TRB) { 483 printf("out of the max sfc trb"); 484 return -EINVAL; 485 } 486 487 if (len && !(len & (ARCH_DMA_MINALIGN - 1))) 488 return rockchip_sfc_dma_xfer(sfc, buf, len); 489 else 490 return rockchip_sfc_pio_xfer(sfc, buf, len); 491 492 return 0; 493 } 494 495 static int rockchip_sfc_do_xfer(struct rockchip_sfc *sfc, void *buf, size_t len) 496 { 497 if (sfc->rw) 498 return rockchip_sfc_write(sfc, sfc->addr, buf, len); 499 else 500 return rockchip_sfc_read(sfc, sfc->addr, buf, len); 501 } 502 503 static int rockchip_sfc_xfer(struct udevice *dev, unsigned int bitlen, 504 const void *dout, void *din, unsigned long flags) 505 { 506 struct udevice *bus = dev->parent; 507 struct rockchip_sfc *sfc = dev_get_priv(bus); 508 int len = bitlen >> 3; 509 u8 *pcmd = (u8 *)dout; 510 void *data_buf; 511 int ret = 0; 512 513 if (flags & SPI_XFER_BEGIN) { 514 sfc->cmd = pcmd[0]; 515 if (len >= 4) { 516 sfc->addr_bits = 24; 517 sfc->dummy_bits = (len - 4) << 3; 518 sfc->addr = pcmd[3] | (pcmd[2] << 8) | (pcmd[1] << 16); 519 } else if (len == 3 && dout) { 520 sfc->addr_bits = 16; 521 sfc->dummy_bits = 0; 522 sfc->addr = pcmd[2] | pcmd[1] << 8; 523 } else if (len == 2 && dout) { 524 sfc->addr_bits = 8; 525 sfc->dummy_bits = 0; 526 sfc->addr = pcmd[1]; 527 } else { 528 sfc->addr_bits = 0; 529 sfc->dummy_bits = 0; 530 sfc->addr = 0; 531 } 532 } 533 534 if (flags & SPI_XFER_END) { 535 if (din) { 536 sfc->rw = SFC_RD; 537 data_buf = din; 538 } else { 539 sfc->rw = SFC_WR; 540 data_buf = (void *)dout; 541 } 542 543 if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) { 544 len = 0; 545 data_buf = NULL; 546 } 547 548 ret = rockchip_sfc_do_xfer(sfc, data_buf, len); 549 } 550 551 return ret; 552 } 553 554 static int rockchip_sfc_set_speed(struct udevice *bus, uint speed) 555 { 556 struct rockchip_sfc *sfc = dev_get_priv(bus); 557 558 if (speed > sfc->max_freq) 559 speed = sfc->max_freq; 560 561 sfc->speed_hz = speed; 562 563 return 0; 564 } 565 566 static int rockchip_sfc_set_mode(struct udevice *bus, uint mode) 567 { 568 struct rockchip_sfc *sfc = dev_get_priv(bus); 569 570 sfc->mode = mode; 571 572 return 0; 573 } 574 575 static const struct dm_spi_ops rockchip_sfc_ops = { 576 .xfer = rockchip_sfc_xfer, 577 .set_speed = rockchip_sfc_set_speed, 578 .set_mode = rockchip_sfc_set_mode, 579 }; 580 581 static const struct udevice_id rockchip_sfc_ids[] = { 582 { .compatible = "rockchip,sfc" }, 583 { } 584 }; 585 586 U_BOOT_DRIVER(rockchip_sfc_driver) = { 587 .name = "rockchip_sfc", 588 .id = UCLASS_SPI, 589 .of_match = rockchip_sfc_ids, 590 .ops = &rockchip_sfc_ops, 591 .ofdata_to_platdata = rockchip_sfc_ofdata_to_platdata, 592 .platdata_auto_alloc_size = sizeof(struct rockchip_sfc_platdata), 593 .priv_auto_alloc_size = sizeof(struct rockchip_sfc), 594 .probe = rockchip_sfc_probe, 595 }; 596