drivers: ram: rv1126: Update loader_params version to 3Let DDR bin tool can modify params of LPDDR4X.Change-Id: I85916fba1aa9d2f7c5e4a630a73c6eaeadf4d11eSigned-off-by: Wesley Yao <wesley.yao@roc
drivers: ram: rv1126: Update loader_params version to 3Let DDR bin tool can modify params of LPDDR4X.Change-Id: I85916fba1aa9d2f7c5e4a630a73c6eaeadf4d11eSigned-off-by: Wesley Yao <wesley.yao@rock-chips.com>
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drivers: ram: rv1126: Detect bus width of DDR3 through read gate, andinit DDR3 againSigned-off-by: Wesley Yao <wesley.yao@rock-chips.com>Change-Id: Ib482a0a1db1df2f638e3642fbfd55d8ca25d7722
drivers: ram: rv1126: add support lpddr4xSigned-off-by: Zhihuan He <huan.he@rock-chips.com>Change-Id: I2470a50551fe0576e56c5ac8121f783b61efd70e
drivers: ram: rv1126: fix lpddr4 phy side odt errThe minimum odt in phy side is 80ohm in VDDQ/2.5Signed-off-by: Zhihuan He <huan.he@rock-chips.com>Change-Id: Iae6cf27906dd0501a167063e9a1f33bef51
drivers: ram: rv1126: fix lpddr4 phy side odt errThe minimum odt in phy side is 80ohm in VDDQ/2.5Signed-off-by: Zhihuan He <huan.he@rock-chips.com>Change-Id: Iae6cf27906dd0501a167063e9a1f33bef51f7866
drivers: ram: rv1126: fix tZQLAT of LPDDR4set t_zq_short_nop(reg ZQCTL0) to tZQLAT for LPDDR4Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>Change-Id: I5fa2e65b642b83529caa60bf5893398bcb84
drivers: ram: rv1126: fix tZQLAT of LPDDR4set t_zq_short_nop(reg ZQCTL0) to tZQLAT for LPDDR4Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>Change-Id: I5fa2e65b642b83529caa60bf5893398bcb84cca5
drivers: ram: rv1126: Support RV1126 DDR3 x8 bus widthsdram_rv1126.c: 22-28 added to ddrconfig calculate.sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4when x8 bus widthsdra
drivers: ram: rv1126: Support RV1126 DDR3 x8 bus widthsdram_rv1126.c: 22-28 added to ddrconfig calculate.sdram_rv1126.c: BurstSize & BurstPenalty in NOC are set to 0x1 & 0x4when x8 bus widthsdram_rv1126.c: When detecting DDR3 capacity, the initial value of buswidth is set to 8. Add detection of x8 bus width through read gatetrainingsdram_common.c: When detecting DDR3 die bus width, dbw = x8 if bw == x8sdram-rv1126-ddr3-detect-xxx.inc: Bus width defaults to x8Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>Change-Id: Ic6a635bcb3a5902f5f7871516dca6ae5de8398fc
drivers: ram: rockchip: add rk3308 sdram driverChange-Id: I96160af2095ba21b440c6d3789349d8cbc4fea75Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
drivers: ram: rv1126: fix the timing about noc and controller1. set the noc ddrtimingc0.b.wrtomwr for LPDDR42. set the noc ddrmode.b.mwrsize for LPDDR43. update the noc ddrmode.b.burstsize4. upd
drivers: ram: rv1126: fix the timing about noc and controller1. set the noc ddrtimingc0.b.wrtomwr for LPDDR42. set the noc ddrmode.b.mwrsize for LPDDR43. update the noc ddrmode.b.burstsize4. update the controller timing for 328MHz5. set ddr4timing to 0 except LPDDR46. calculate ddr4timing using *_L timing for DDR4Change-Id: I9f8fae51a05f8547d64da262d4c69fd4edec79fbSigned-off-by: YouMin Chen <cym@rock-chips.com>
rv1126: ddr: update driver strength and odt strength configChange-Id: Id78273d75ef13cfc6f1f335e475f16862bfaf938Signed-off-by: Tang Yun ping <typ@rock-chips.com>
rv1126: ddr: update drv odt tableChange-Id: Ic20957d02c36fe2d167c1a63b5e016535a181bafSigned-off-by: Tang Yun ping <typ@rock-chips.com>
drivers: ram: rv1126: modify ddr support frequencyModify ddr support frequency to match PLL setting.Change-Id: I1d93b2178933ada04e178bd068a8fec4ef43a4deSigned-off-by: YouMin Chen <cym@rock-chips
drivers: ram: rv1126: modify ddr support frequencyModify ddr support frequency to match PLL setting.Change-Id: I1d93b2178933ada04e178bd068a8fec4ef43a4deSigned-off-by: YouMin Chen <cym@rock-chips.com>
drivers: ram: rv1126: add support DDR3/LPDDR3 1056MHzChange-Id: Ib24e263f1a58861a173b5b566718385b3f67eedcSigned-off-by: YouMin Chen <cym@rock-chips.com>
drivers: ram: rockchip: add rv1126 sdram init codeChange-Id: I0c7ce7f274c396d077a4ae2fe29e382a8e295274Signed-off-by: YouMin Chen <cym@rock-chips.com>