1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 25 /* W25Q64JVSSIQ */ 26 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 27 /* W25Q128FV and W25Q128JV*/ 28 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 29 /* W25Q256F/J */ 30 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 31 /* W25Q256JWEQ*/ 32 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 33 /* W25Q64FWSSIG */ 34 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 35 /* W25Q128JVSIM */ 36 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 37 /* MX25L3233FM2I-08G */ 38 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 39 /* MX25L6433F */ 40 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 41 /* MX25L12835E/F MX25L12833FMI-10G */ 42 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 43 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 44 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 45 /* MX25L51245GMI */ 46 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 47 /* XM25QH32C */ 48 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 49 /* XM25QH64B */ 50 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 51 /* XM25QH128B */ 52 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 53 /* XM25QH(QU)256B */ 54 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 55 /* XM25QH64A */ 56 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 57 /* XT25F128A XM25QH128A */ 58 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 59 /* XT25F64BSSIGU-5 */ 60 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 61 /* XT25F128BSSIGU */ 62 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 63 /* EN25QH64A */ 64 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 65 /* EN25QH128A */ 66 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 67 /* EN25QH32B */ 68 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 69 /* EN25S32A */ 70 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 71 /* EN25S64A */ 72 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 73 /* P25Q64H */ 74 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 75 /* EN25QH256A */ 76 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 77 /* FM25Q64A */ 78 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 79 /* ZB25VQ64 */ 80 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 81 /* ZB25VQ128 */ 82 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 83 /* ZB25LQ128 */ 84 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 85 /* 25Q256JVEM */ 86 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 87 /* BH25Q128AS */ 88 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 15, 9, 0 }, 89 /* BH25Q64BS */ 90 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 14, 9, 0 }, 91 /* FM25Q128A */ 92 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 93 /* FM25Q64-SOB-T-G */ 94 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 95 }; 96 97 static int snor_write_en(void) 98 { 99 int ret; 100 struct rk_sfc_op op; 101 102 op.sfcmd.d32 = 0; 103 op.sfcmd.b.cmd = CMD_WRITE_EN; 104 105 op.sfctrl.d32 = 0; 106 107 ret = sfc_request(&op, 0, NULL, 0); 108 109 return ret; 110 } 111 112 int snor_reset_device(void) 113 { 114 struct rk_sfc_op op; 115 116 op.sfcmd.d32 = 0; 117 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 118 119 op.sfctrl.d32 = 0; 120 sfc_request(&op, 0, NULL, 0); 121 122 op.sfcmd.d32 = 0; 123 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 124 125 op.sfctrl.d32 = 0; 126 sfc_request(&op, 0, NULL, 0); 127 /* tRST=30us , delay 1ms here */ 128 sfc_delay(1000); 129 130 return SFC_OK; 131 } 132 133 static int snor_enter_4byte_mode(void) 134 { 135 int ret; 136 struct rk_sfc_op op; 137 138 op.sfcmd.d32 = 0; 139 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 140 141 op.sfctrl.d32 = 0; 142 143 ret = sfc_request(&op, 0, NULL, 0); 144 return ret; 145 } 146 147 static int snor_read_status(u32 reg_index, u8 *status) 148 { 149 int ret; 150 struct rk_sfc_op op; 151 u8 read_stat_cmd[] = {CMD_READ_STATUS, 152 CMD_READ_STATUS2, CMD_READ_STATUS3}; 153 op.sfcmd.d32 = 0; 154 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 155 156 op.sfctrl.d32 = 0; 157 ret = sfc_request(&op, 0, status, 1); 158 159 return ret; 160 } 161 162 static int snor_wait_busy(int timeout) 163 { 164 int ret; 165 struct rk_sfc_op op; 166 int i; 167 u32 status; 168 169 op.sfcmd.d32 = 0; 170 op.sfcmd.b.cmd = CMD_READ_STATUS; 171 172 op.sfctrl.d32 = 0; 173 174 for (i = 0; i < timeout; i++) { 175 ret = sfc_request(&op, 0, &status, 1); 176 if (ret != SFC_OK) 177 return ret; 178 179 if ((status & 0x01) == 0) 180 return SFC_OK; 181 182 sfc_delay(1); 183 } 184 rkflash_print_error("%s error %x\n", __func__, timeout); 185 186 return SFC_BUSY_TIMEOUT; 187 } 188 189 static int snor_write_status2(u32 reg_index, u8 status) 190 { 191 int ret; 192 struct rk_sfc_op op; 193 u8 status2[2]; 194 195 status2[reg_index] = status; 196 if (reg_index == 0) 197 ret = snor_read_status(2, &status2[1]); 198 else 199 ret = snor_read_status(0, &status2[0]); 200 if (ret != SFC_OK) 201 return ret; 202 203 snor_write_en(); 204 205 op.sfcmd.d32 = 0; 206 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 207 op.sfcmd.b.rw = SFC_WRITE; 208 209 op.sfctrl.d32 = 0; 210 211 ret = sfc_request(&op, 0, &status2[0], 2); 212 if (ret != SFC_OK) 213 return ret; 214 215 ret = snor_wait_busy(10000); /* 10ms */ 216 217 return ret; 218 } 219 220 static int snor_write_status1(u32 reg_index, u8 status) 221 { 222 int ret; 223 struct rk_sfc_op op; 224 u8 status2[2]; 225 u8 read_index; 226 227 status2[reg_index] = status; 228 read_index = (reg_index == 0) ? 1 : 0; 229 ret = snor_read_status(read_index, &status2[read_index]); 230 if (ret != SFC_OK) 231 return ret; 232 233 snor_write_en(); 234 235 op.sfcmd.d32 = 0; 236 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 237 op.sfcmd.b.rw = SFC_WRITE; 238 239 op.sfctrl.d32 = 0; 240 241 ret = sfc_request(&op, 0, &status2[0], 2); 242 if (ret != SFC_OK) 243 return ret; 244 245 ret = snor_wait_busy(10000); /* 10ms */ 246 247 return ret; 248 } 249 250 static int snor_write_status(u32 reg_index, u8 status) 251 { 252 int ret; 253 struct rk_sfc_op op; 254 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 255 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 256 snor_write_en(); 257 op.sfcmd.d32 = 0; 258 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 259 op.sfcmd.b.rw = SFC_WRITE; 260 261 op.sfctrl.d32 = 0; 262 263 ret = sfc_request(&op, 0, &status, 1); 264 if (ret != SFC_OK) 265 return ret; 266 267 ret = snor_wait_busy(10000); /* 10ms */ 268 269 return ret; 270 } 271 272 int snor_erase(struct SFNOR_DEV *p_dev, 273 u32 addr, 274 enum NOR_ERASE_TYPE erase_type) 275 { 276 int ret; 277 struct rk_sfc_op op; 278 int timeout[] = {400, 2000, 40000}; /* ms */ 279 280 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 281 282 if (erase_type > ERASE_CHIP) 283 return SFC_PARAM_ERR; 284 285 op.sfcmd.d32 = 0; 286 if (erase_type == ERASE_BLOCK64K) 287 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 288 else if (erase_type == ERASE_SECTOR) 289 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 290 else 291 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 292 293 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 294 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 295 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 296 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 297 298 op.sfctrl.d32 = 0; 299 300 snor_write_en(); 301 302 ret = sfc_request(&op, addr, NULL, 0); 303 if (ret != SFC_OK) 304 return ret; 305 306 ret = snor_wait_busy(timeout[erase_type] * 1000); 307 return ret; 308 } 309 310 int snor_prog_page(struct SFNOR_DEV *p_dev, 311 u32 addr, 312 void *p_data, 313 u32 size) 314 { 315 int ret; 316 struct rk_sfc_op op; 317 318 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 319 320 op.sfcmd.d32 = 0; 321 op.sfcmd.b.cmd = p_dev->prog_cmd; 322 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 323 op.sfcmd.b.rw = SFC_WRITE; 324 325 op.sfctrl.d32 = 0; 326 op.sfctrl.b.datalines = p_dev->prog_lines; 327 op.sfctrl.b.enbledma = 1; 328 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 329 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 330 331 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 332 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 333 334 snor_write_en(); 335 336 ret = sfc_request(&op, addr, p_data, size); 337 if (ret != SFC_OK) 338 return ret; 339 340 ret = snor_wait_busy(10000); 341 342 return ret; 343 } 344 345 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 346 { 347 int ret = SFC_OK; 348 u32 page_size, len; 349 u8 *p_buf = (u8 *)p_data; 350 351 page_size = NOR_PAGE_SIZE; 352 while (size) { 353 len = page_size < size ? page_size : size; 354 ret = snor_prog_page(p_dev, addr, p_buf, len); 355 if (ret != SFC_OK) 356 return ret; 357 358 size -= len; 359 addr += len; 360 p_buf += len; 361 } 362 363 return ret; 364 } 365 366 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 367 { 368 int ret = SFC_OK; 369 int reg_index; 370 int bit_offset; 371 u8 status; 372 373 reg_index = p_dev->QE_bits >> 3; 374 bit_offset = p_dev->QE_bits & 0x7; 375 ret = snor_read_status(reg_index, &status); 376 if (ret != SFC_OK) 377 return ret; 378 379 if (status & (1 << bit_offset)) /* is QE bit set */ 380 return SFC_OK; 381 382 status |= (1 << bit_offset); 383 384 return p_dev->write_status(reg_index, status); 385 } 386 387 int snor_disable_QE(struct SFNOR_DEV *p_dev) 388 { 389 int ret = SFC_OK; 390 int reg_index; 391 int bit_offset; 392 u8 status; 393 394 reg_index = p_dev->QE_bits >> 3; 395 bit_offset = p_dev->QE_bits & 0x7; 396 ret = snor_read_status(reg_index, &status); 397 if (ret != SFC_OK) 398 return ret; 399 400 if (!(status & (1 << bit_offset))) 401 return SFC_OK; 402 403 status &= ~(1 << bit_offset); 404 405 return p_dev->write_status(reg_index, status); 406 } 407 408 int snor_read_data(struct SFNOR_DEV *p_dev, 409 u32 addr, 410 void *p_data, 411 u32 size) 412 { 413 int ret; 414 struct rk_sfc_op op; 415 416 op.sfcmd.d32 = 0; 417 op.sfcmd.b.cmd = p_dev->read_cmd; 418 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 419 420 op.sfctrl.d32 = 0; 421 op.sfctrl.b.datalines = p_dev->read_lines; 422 if (!(size & 0x3) && size >= 4) 423 op.sfctrl.b.enbledma = 1; 424 425 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 426 p_dev->read_cmd == CMD_FAST_READ_X4 || 427 p_dev->read_cmd == CMD_FAST_READ_X2 || 428 p_dev->read_cmd == CMD_FAST_4READ_X4) { 429 op.sfcmd.b.dummybits = 8; 430 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 431 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 432 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 433 op.sfcmd.b.dummybits = 4; 434 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 435 } 436 437 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 438 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 439 440 ret = sfc_request(&op, addr, p_data, size); 441 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 442 443 return ret; 444 } 445 446 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 447 { 448 int ret = SFC_OK; 449 u32 addr, size, len; 450 u8 *p_buf = (u8 *)p_data; 451 452 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 453 454 if ((sec + n_sec) > p_dev->capacity) 455 return SFC_PARAM_ERR; 456 457 addr = sec << 9; 458 size = n_sec << 9; 459 while (size) { 460 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 461 ret = snor_read_data(p_dev, addr, p_buf, len); 462 if (ret != SFC_OK) { 463 rkflash_print_error("snor_read_data %x ret= %x\n", 464 addr >> 9, ret); 465 goto out; 466 } 467 468 size -= len; 469 addr += len; 470 p_buf += len; 471 } 472 out: 473 if (!ret) 474 ret = n_sec; 475 476 return ret; 477 } 478 479 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 480 { 481 int ret = SFC_OK; 482 u32 len, blk_size, offset; 483 u8 *p_buf = (u8 *)p_data; 484 u32 total_sec = n_sec; 485 486 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 487 488 if ((sec + n_sec) > p_dev->capacity) 489 return SFC_PARAM_ERR; 490 491 while (n_sec) { 492 if (sec < 512 || sec >= p_dev->capacity - 512) 493 blk_size = 8; 494 else 495 blk_size = p_dev->blk_size; 496 497 offset = (sec & (blk_size - 1)); 498 if (!offset) { 499 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 500 ERASE_SECTOR : ERASE_BLOCK64K); 501 if (ret != SFC_OK) { 502 rkflash_print_error("snor_erase %x ret= %x\n", 503 sec, ret); 504 goto out; 505 } 506 } 507 len = (blk_size - offset) < n_sec ? 508 (blk_size - offset) : n_sec; 509 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 510 if (ret != SFC_OK) { 511 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 512 goto out; 513 } 514 n_sec -= len; 515 sec += len; 516 p_buf += len << 9; 517 } 518 out: 519 if (!ret) 520 ret = total_sec; 521 522 return ret; 523 } 524 525 int snor_read_id(u8 *data) 526 { 527 int ret; 528 struct rk_sfc_op op; 529 530 op.sfcmd.d32 = 0; 531 op.sfcmd.b.cmd = CMD_READ_JEDECID; 532 533 op.sfctrl.d32 = 0; 534 535 ret = sfc_request(&op, 0, data, 3); 536 537 return ret; 538 } 539 540 static int snor_read_parameter(u32 addr, u8 *data) 541 { 542 int ret; 543 struct rk_sfc_op op; 544 545 op.sfcmd.d32 = 0; 546 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 547 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 548 op.sfcmd.b.dummybits = 8; 549 550 op.sfctrl.d32 = 0; 551 552 ret = sfc_request(&op, addr, data, 1); 553 554 return ret; 555 } 556 557 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 558 { 559 return p_dev->capacity; 560 } 561 562 static struct flash_info *snor_get_flash_info(u8 *flash_id) 563 { 564 u32 i; 565 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 566 567 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 568 if (spi_flash_tbl[i].id == id) 569 return &spi_flash_tbl[i]; 570 } 571 return NULL; 572 } 573 574 /* Adjust flash info in ram base on parameter */ 575 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 576 { 577 u32 addr; 578 u8 para_version; 579 580 if (spi_flash_info->id == 0xc84019) { 581 addr = 0x09; 582 snor_read_parameter(addr, ¶_version); 583 if (para_version == 0x06) { 584 spi_flash_info->QE_bits = 9; 585 spi_flash_info->prog_cmd_4 = 0x34; 586 } 587 } 588 return 0; 589 } 590 591 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 592 struct flash_info *g_spi_flash_info) 593 { 594 int i, ret; 595 596 if (g_spi_flash_info) { 597 snor_flash_info_adjust(g_spi_flash_info); 598 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 599 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 600 p_dev->capacity = 1 << ((g_spi_flash_info->id & 0xFF) - 9); 601 p_dev->blk_size = g_spi_flash_info->block_size; 602 p_dev->page_size = NOR_SECS_PAGE; 603 p_dev->read_cmd = g_spi_flash_info->read_cmd; 604 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 605 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 606 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 607 p_dev->prog_lines = DATA_LINES_X1; 608 p_dev->read_lines = DATA_LINES_X1; 609 p_dev->QE_bits = g_spi_flash_info->QE_bits; 610 p_dev->addr_mode = ADDR_MODE_3BYTE; 611 612 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 613 if (i == 0) 614 p_dev->write_status = snor_write_status; 615 else if (i == 1) 616 p_dev->write_status = snor_write_status1; 617 else if (i == 2) 618 p_dev->write_status = snor_write_status2; 619 620 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 621 ret = SFC_OK; 622 if (g_spi_flash_info->QE_bits) 623 ret = snor_enable_QE(p_dev); 624 if (ret == SFC_OK) { 625 p_dev->read_lines = DATA_LINES_X4; 626 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 627 } 628 } 629 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 630 p_dev->read_lines == DATA_LINES_X4) { 631 p_dev->prog_lines = DATA_LINES_X4; 632 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 633 } 634 635 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 636 p_dev->addr_mode = ADDR_MODE_4BYTE; 637 638 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 639 snor_enter_4byte_mode(); 640 } 641 642 return SFC_OK; 643 } 644 645 int snor_init(struct SFNOR_DEV *p_dev) 646 { 647 struct flash_info *g_spi_flash_info; 648 u8 id_byte[5]; 649 650 if (!p_dev) 651 return SFC_PARAM_ERR; 652 653 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 654 p_dev->max_iosize = sfc_get_max_iosize(); 655 656 snor_read_id(id_byte); 657 rkflash_print_error("sfc nor id: %x %x %x\n", 658 id_byte[0], id_byte[1], id_byte[2]); 659 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 660 return SFC_ERROR; 661 662 g_spi_flash_info = snor_get_flash_info(id_byte); 663 if (g_spi_flash_info) { 664 snor_parse_flash_table(p_dev, g_spi_flash_info); 665 } else { 666 p_dev->manufacturer = id_byte[0]; 667 p_dev->mem_type = id_byte[1]; 668 p_dev->capacity = 1 << (id_byte[2] - 9); 669 p_dev->QE_bits = 0; 670 p_dev->blk_size = NOR_SECS_BLK; 671 p_dev->page_size = NOR_SECS_PAGE; 672 p_dev->read_cmd = CMD_READ_DATA; 673 p_dev->prog_cmd = CMD_PAGE_PROG; 674 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 675 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 676 p_dev->prog_lines = DATA_LINES_X1; 677 p_dev->read_lines = DATA_LINES_X1; 678 p_dev->write_status = snor_write_status; 679 snor_reset_device(); 680 } 681 682 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 683 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 684 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 685 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 686 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 687 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 688 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 689 rkflash_print_info("capacity: %x\n", p_dev->capacity); 690 691 return SFC_OK; 692 } 693 694 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 695 struct snor_info_packet *packet) 696 { 697 struct flash_info g_spi_flash_info; 698 u8 id_byte[5]; 699 int ret; 700 701 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 702 return SFC_PARAM_ERR; 703 704 snor_read_id(id_byte); 705 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 706 return SFC_ERROR; 707 708 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 709 g_spi_flash_info.block_size = NOR_SECS_BLK; 710 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 711 g_spi_flash_info.read_cmd = packet->read_cmd; 712 g_spi_flash_info.prog_cmd = packet->prog_cmd; 713 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 714 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 715 if (id_byte[2] >= 0x19) 716 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 717 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 718 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 719 g_spi_flash_info.feature = packet->feature; 720 g_spi_flash_info.density = id_byte[2] - 9; 721 g_spi_flash_info.QE_bits = packet->QE_bits; 722 723 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 724 725 return ret; 726 } 727 728