1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * (C) Copyright 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6 #include <common.h> 7 #include <debug_uart.h> 8 #include <dm.h> 9 #include <ram.h> 10 #include <syscon.h> 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/hardware.h> 14 #include <asm/arch/rk_atags.h> 15 #include <asm/arch/cru_rv1126.h> 16 #include <asm/arch/grf_rv1126.h> 17 #include <asm/arch/sdram_common.h> 18 #include <asm/arch/sdram_rv1126.h> 19 20 /* define training flag */ 21 #define CA_TRAINING (0x1 << 0) 22 #define READ_GATE_TRAINING (0x1 << 1) 23 #define WRITE_LEVELING (0x1 << 2) 24 #define WRITE_TRAINING (0x1 << 3) 25 #define READ_TRAINING (0x1 << 4) 26 #define FULL_TRAINING (0xff) 27 28 #define SKEW_RX_SIGNAL (0) 29 #define SKEW_TX_SIGNAL (1) 30 #define SKEW_CA_SIGNAL (2) 31 32 #define DESKEW_MDF_ABS_VAL (0) 33 #define DESKEW_MDF_DIFF_VAL (1) 34 35 #ifdef CONFIG_TPL_BUILD 36 #ifndef CONFIG_TPL_TINY_FRAMEWORK 37 #error please defined CONFIG_TPL_TINY_FRAMEWORK for RV1126 !!! 38 #endif 39 #endif 40 41 #ifdef CONFIG_TPL_BUILD 42 43 struct dram_info { 44 void __iomem *pctl; 45 void __iomem *phy; 46 struct rv1126_cru *cru; 47 struct msch_regs *msch; 48 struct rv1126_ddrgrf *ddrgrf; 49 struct rv1126_grf *grf; 50 struct ram_info info; 51 struct rv1126_pmugrf *pmugrf; 52 u32 sr_idle; 53 u32 pd_idle; 54 }; 55 56 #define GRF_BASE_ADDR 0xfe000000 57 #define PMU_GRF_BASE_ADDR 0xfe020000 58 #define DDR_GRF_BASE_ADDR 0xfe030000 59 #define BUS_SGRF_BASE_ADDR 0xfe0a0000 60 #define SERVER_MSCH_BASE_ADDR 0xfe800000 61 #define CRU_BASE_ADDR 0xff490000 62 #define DDR_PHY_BASE_ADDR 0xff4a0000 63 #define UPCTL2_BASE_ADDR 0xffa50000 64 65 #define SGRF_SOC_CON2 0x8 66 #define SGRF_SOC_CON12 0x30 67 #define SGRF_SOC_CON13 0x34 68 69 struct dram_info dram_info; 70 71 #if (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 3) 72 struct rv1126_sdram_params sdram_configs[] = { 73 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-328.inc" 74 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-396.inc" 75 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-528.inc" 76 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-664.inc" 77 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-784.inc" 78 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-924.inc" 79 #include "sdram_inc/rv1126/sdram-rv1126-ddr3-detect-1056.inc" 80 }; 81 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 0) 82 struct rv1126_sdram_params sdram_configs[] = { 83 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-328.inc" 84 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-396.inc" 85 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-528.inc" 86 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-664.inc" 87 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-784.inc" 88 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-924.inc" 89 #include "sdram_inc/rv1126/sdram-rv1126-ddr4-detect-1056.inc" 90 }; 91 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 6) 92 struct rv1126_sdram_params sdram_configs[] = { 93 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-328.inc" 94 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-396.inc" 95 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-528.inc" 96 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-664.inc" 97 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-784.inc" 98 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-924.inc" 99 #include "sdram_inc/rv1126/sdram-rv1126-lpddr3-detect-1056.inc" 100 }; 101 #elif (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 7) || (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 8) 102 struct rv1126_sdram_params sdram_configs[] = { 103 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-328.inc" 104 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-396.inc" 105 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-528.inc" 106 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-664.inc" 107 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-784.inc" 108 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-924.inc" 109 #include "sdram_inc/rv1126/sdram-rv1126-lpddr4-detect-1056.inc" 110 }; 111 #endif 112 113 u32 common_info[] = { 114 #include "sdram_inc/rv1126/sdram-rv1126-loader_params.inc" 115 }; 116 117 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 118 static struct rw_trn_result rw_trn_result; 119 #endif 120 121 static struct rv1126_fsp_param fsp_param[MAX_IDX]; 122 123 static u8 lp3_odt_value; 124 125 static s8 wrlvl_result[2][4]; 126 127 /* DDR configuration 0-9 */ 128 u16 ddr_cfg_2_rbc[] = { 129 ((0 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 3), /* 0 */ 130 ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 2), /* 1 */ 131 ((1 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 3), /* 2 */ 132 ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 1), /* 3 */ 133 ((0 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 4), /* 4 */ 134 ((0 << 8) | (3 << 5) | (1 << 4) | (1 << 3) | 1), /* 5 */ 135 ((0 << 8) | (3 << 5) | (1 << 4) | (1 << 3) | 2), /* 6 */ 136 ((0 << 8) | (2 << 5) | (1 << 4) | (1 << 3) | 3), /* 7 */ 137 ((1 << 8) | (3 << 5) | (0 << 4) | (0 << 3) | 2), /* 8 */ 138 ((1 << 8) | (2 << 5) | (0 << 4) | (1 << 3) | 2) /* 9 */ 139 }; 140 141 /* DDR configuration 10-21 */ 142 u8 ddr4_cfg_2_rbc[] = { 143 ((0 << 7) | (3 << 4) | (0 << 3) | (2 << 1) | 0), /* 10 */ 144 ((1 << 7) | (2 << 4) | (0 << 3) | (2 << 1) | 0), /* 11 */ 145 ((0 << 7) | (4 << 4) | (0 << 3) | (1 << 1) | 0), /* 12 */ 146 ((1 << 7) | (3 << 4) | (0 << 3) | (1 << 1) | 0), /* 13 */ 147 ((0 << 7) | (4 << 4) | (0 << 3) | (2 << 1) | 1), /* 14 */ 148 ((1 << 7) | (3 << 4) | (0 << 3) | (2 << 1) | 1), /* 15 */ 149 ((1 << 7) | (4 << 4) | (0 << 3) | (1 << 1) | 1), /* 16 */ 150 ((0 << 7) | (2 << 4) | (1 << 3) | (2 << 1) | 0), /* 17 */ 151 ((0 << 7) | (3 << 4) | (1 << 3) | (1 << 1) | 0), /* 18 */ 152 ((0 << 7) | (3 << 4) | (1 << 3) | (2 << 1) | 1), /* 19 */ 153 ((0 << 7) | (4 << 4) | (1 << 3) | (1 << 1) | 1), /* 20 */ 154 ((1 << 7) | (4 << 4) | (0 << 3) | (0 << 1) | 0) /* 21 */ 155 }; 156 157 /* DDR configuration 22-28 */ 158 u16 ddr_cfg_2_rbc_p2[] = { 159 ((1 << 8) | (3 << 5) | (0 << 4) | (1 << 3) | 0), /* 22 */ 160 ((0 << 8) | (4 << 5) | (0 << 4) | (1 << 3) | 2), /* 23 */ 161 ((1 << 8) | (3 << 5) | (0 << 4) | (0 << 3) | 3), /* 24 */ 162 ((0 << 8) | (3 << 5) | (1 << 4) | (0 << 3) | 3), /* 25 */ 163 ((0 << 8) | (4 << 5) | (1 << 4) | (0 << 3) | 2), /* 26 */ 164 ((1 << 8) | (4 << 5) | (0 << 4) | (0 << 3) | 2), /* 27 */ 165 ((0 << 8) | (4 << 5) | (0 << 4) | (0 << 3) | 3) /* 28 */ 166 }; 167 168 u8 d4_rbc_2_d3_rbc[][2] = { 169 {10, 0}, 170 {11, 2}, 171 {12, 23}, 172 {13, 1}, 173 {14, 28}, 174 {15, 24}, 175 {16, 27}, 176 {17, 7}, 177 {18, 6}, 178 {19, 25}, 179 {20, 26}, 180 {21, 3} 181 }; 182 183 u32 addrmap[29][9] = { 184 {24, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 185 0x08080808, 0x00000f0f, 0x3f3f}, /* 0 */ 186 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 187 0x07070707, 0x00000f0f, 0x3f3f}, /* 1 */ 188 {23, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 189 0x0f080808, 0x00000f0f, 0x3f3f}, /* 2 */ 190 {22, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x06060606, 191 0x06060606, 0x00000f0f, 0x3f3f}, /* 3 */ 192 {24, 0x000a0a0a, 0x00000000, 0x00000000, 0x00000000, 0x09090909, 193 0x0f090909, 0x00000f0f, 0x3f3f}, /* 4 */ 194 {6, 0x00070707, 0x00000000, 0x1f000000, 0x00001f1f, 0x07070707, 195 0x07070707, 0x00000f0f, 0x3f3f}, /* 5 */ 196 {7, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x08080808, 197 0x08080808, 0x00000f0f, 0x3f3f}, /* 6 */ 198 {8, 0x00090909, 0x00000000, 0x00000000, 0x00001f00, 0x09090909, 199 0x0f090909, 0x00000f0f, 0x3f3f}, /* 7 */ 200 {22, 0x001f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 201 0x06060606, 0x00000f0f, 0x3f3f}, /* 8 */ 202 {23, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 203 0x0f070707, 0x00000f0f, 0x3f3f}, /* 9 */ 204 205 {24, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 206 0x08080808, 0x00000f0f, 0x0801}, /* 10 */ 207 {23, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 208 0x0f080808, 0x00000f0f, 0x0801}, /* 11 */ 209 {24, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 210 0x07070707, 0x00000f07, 0x0700}, /* 12 */ 211 {23, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 212 0x07070707, 0x00000f0f, 0x0700}, /* 13 */ 213 {24, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 214 0x07070707, 0x00000f07, 0x3f01}, /* 14 */ 215 {23, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x07070707, 216 0x07070707, 0x00000f0f, 0x3f01}, /* 15 */ 217 {23, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x06060606, 218 0x06060606, 0x00000f06, 0x3f00}, /* 16 */ 219 {8, 0x003f0a0a, 0x01010100, 0x01010101, 0x00001f1f, 0x09090909, 220 0x0f090909, 0x00000f0f, 0x0801}, /* 17 */ 221 {7, 0x003f0909, 0x00000007, 0x1f000000, 0x00001f1f, 0x08080808, 222 0x08080808, 0x00000f0f, 0x0700}, /* 18 */ 223 {7, 0x003f0909, 0x01010100, 0x01010101, 0x00001f1f, 0x08080808, 224 0x08080808, 0x00000f0f, 0x3f01}, /* 19 */ 225 226 {6, 0x003f0808, 0x00000007, 0x1f000000, 0x00001f1f, 0x07070707, 227 0x07070707, 0x00000f07, 0x3f00}, /* 20 */ 228 {23, 0x003f0909, 0x00000006, 0x1f1f0000, 0x00001f1f, 0x06060606, 229 0x06060606, 0x00000f06, 0x0600}, /* 21 */ 230 {21, 0x00060606, 0x00000000, 0x1f1f0000, 0x00001f1f, 0x05050505, 231 0x05050505, 0x00000f0f, 0x3f3f}, /* 22 */ 232 233 {24, 0x00080808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 234 0x07070707, 0x00000f07, 0x3f3f}, /* 23 */ 235 {23, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x07070707, 236 0x07070707, 0x00000f0f, 0x3f3f}, /* 24 */ 237 {7, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x08080808, 238 0x08080808, 0x00000f0f, 0x3f3f}, /* 25 */ 239 {6, 0x003f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x07070707, 240 0x07070707, 0x00000f07, 0x3f3f}, /* 26 */ 241 {23, 0x003f0808, 0x00000000, 0x00000000, 0x00001f1f, 0x06060606, 242 0x06060606, 0x00000f06, 0x3f3f}, /* 27 */ 243 {24, 0x003f0909, 0x00000000, 0x00000000, 0x00001f00, 0x07070707, 244 0x07070707, 0x00000f07, 0x3f3f} /* 28 */ 245 }; 246 247 static u8 dq_sel[22][3] = { 248 {0x0, 0x17, 0x22}, 249 {0x1, 0x18, 0x23}, 250 {0x2, 0x19, 0x24}, 251 {0x3, 0x1a, 0x25}, 252 {0x4, 0x1b, 0x26}, 253 {0x5, 0x1c, 0x27}, 254 {0x6, 0x1d, 0x28}, 255 {0x7, 0x1e, 0x29}, 256 {0x8, 0x16, 0x21}, 257 {0x9, 0x1f, 0x2a}, 258 {0xa, 0x20, 0x2b}, 259 {0x10, 0x1, 0xc}, 260 {0x11, 0x2, 0xd}, 261 {0x12, 0x3, 0xe}, 262 {0x13, 0x4, 0xf}, 263 {0x14, 0x5, 0x10}, 264 {0x15, 0x6, 0x11}, 265 {0x16, 0x7, 0x12}, 266 {0x17, 0x8, 0x13}, 267 {0x18, 0x0, 0xb}, 268 {0x19, 0x9, 0x14}, 269 {0x1a, 0xa, 0x15} 270 }; 271 272 static u16 grp_addr[4] = { 273 ADD_GROUP_CS0_A, 274 ADD_GROUP_CS0_B, 275 ADD_GROUP_CS1_A, 276 ADD_GROUP_CS1_B 277 }; 278 279 static u8 wrlvl_result_offset[2][4] = { 280 {0xa0 + 0x26, 0xa0 + 0x27, 0xd0 + 0x26, 0xd0 + 0x27}, 281 {0xa0 + 0x28, 0xa0 + 0x29, 0xd0 + 0x28, 0xd0 + 0x29}, 282 }; 283 284 static u16 dqs_dq_skew_adr[16] = { 285 0x170 + 0, /* SKEW_UPDATE_RX_CS0_DQS0 */ 286 0x170 + 0xb, /* SKEW_UPDATE_RX_CS0_DQS1 */ 287 0x1d0 + 0, /* SKEW_UPDATE_RX_CS0_DQS2 */ 288 0x1d0 + 0xb, /* SKEW_UPDATE_RX_CS0_DQS3 */ 289 0x1a0 + 0, /* SKEW_UPDATE_RX_CS1_DQS0 */ 290 0x1a0 + 0xb, /* SKEW_UPDATE_RX_CS1_DQS1 */ 291 0x200 + 0, /* SKEW_UPDATE_RX_CS1_DQS2 */ 292 0x200 + 0xb, /* SKEW_UPDATE_RX_CS1_DQS3 */ 293 0x170 + 0x16, /* SKEW_UPDATE_TX_CS0_DQS0 */ 294 0x170 + 0x21, /* SKEW_UPDATE_TX_CS0_DQS1 */ 295 0x1d0 + 0x16, /* SKEW_UPDATE_TX_CS0_DQS2 */ 296 0x1d0 + 0x21, /* SKEW_UPDATE_TX_CS0_DQS3 */ 297 0x1a0 + 0x16, /* SKEW_UPDATE_TX_CS1_DQS0 */ 298 0x1a0 + 0x21, /* SKEW_UPDATE_TX_CS1_DQS1 */ 299 0x200 + 0x16, /* SKEW_UPDATE_TX_CS1_DQS2 */ 300 0x200 + 0x21, /* SKEW_UPDATE_TX_CS1_DQS3 */ 301 }; 302 303 static void rkclk_ddr_reset(struct dram_info *dram, 304 u32 ctl_srstn, u32 ctl_psrstn, 305 u32 phy_srstn, u32 phy_psrstn) 306 { 307 writel(UPCTL2_SRSTN_REQ(ctl_srstn) | UPCTL2_PSRSTN_REQ(ctl_psrstn) | 308 UPCTL2_ASRSTN_REQ(ctl_srstn), 309 BUS_SGRF_BASE_ADDR + SGRF_SOC_CON13); 310 311 writel(DDRPHY_SRSTN_REQ(phy_srstn) | DDRPHY_PSRSTN_REQ(phy_psrstn), 312 &dram->cru->softrst_con[12]); 313 } 314 315 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) 316 { 317 unsigned int refdiv, postdiv1, postdiv2, fbdiv; 318 int delay = 1000; 319 u32 mhz = hz / MHz; 320 struct global_info *gbl_info; 321 struct sdram_head_info_index_v2 *index = 322 (struct sdram_head_info_index_v2 *)common_info; 323 u32 ssmod_info; 324 u32 dsmpd = 1; 325 326 gbl_info = (struct global_info *)((void *)common_info + 327 index->global_index.offset * 4); 328 ssmod_info = gbl_info->info_2t; 329 refdiv = 1; 330 if (mhz <= 100) { 331 postdiv1 = 6; 332 postdiv2 = 4; 333 } else if (mhz <= 150) { 334 postdiv1 = 4; 335 postdiv2 = 4; 336 } else if (mhz <= 200) { 337 postdiv1 = 6; 338 postdiv2 = 2; 339 } else if (mhz <= 300) { 340 postdiv1 = 4; 341 postdiv2 = 2; 342 } else if (mhz <= 400) { 343 postdiv1 = 6; 344 postdiv2 = 1; 345 } else { 346 postdiv1 = 4; 347 postdiv2 = 1; 348 } 349 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; 350 351 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); 352 353 writel(0x1f000000, &dram->cru->clksel_con[64]); 354 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); 355 /* enable ssmod */ 356 if (PLL_SSMOD_SPREAD(ssmod_info)) { 357 dsmpd = 0; 358 clrsetbits_le32(&dram->cru->pll[1].con2, 359 0xffffff << 0, 0x0 << 0); 360 writel(SSMOD_SPREAD(PLL_SSMOD_SPREAD(ssmod_info)) | 361 SSMOD_DIVVAL(PLL_SSMOD_DIV(ssmod_info)) | 362 SSMOD_DOWNSPREAD(PLL_SSMOD_DOWNSPREAD(ssmod_info)) | 363 SSMOD_RESET(0) | 364 SSMOD_DIS_SSCG(0) | 365 SSMOD_BP(0), 366 &dram->cru->pll[1].con3); 367 } 368 writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv), 369 &dram->cru->pll[1].con1); 370 371 while (delay > 0) { 372 udelay(1); 373 if (LOCK(readl(&dram->cru->pll[1].con1))) 374 break; 375 delay--; 376 } 377 378 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); 379 } 380 381 static void rkclk_configure_ddr(struct dram_info *dram, 382 struct rv1126_sdram_params *sdram_params) 383 { 384 /* for inno ddr phy need freq / 2 */ 385 rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ / 2); 386 } 387 388 static unsigned int 389 calculate_ddrconfig(struct rv1126_sdram_params *sdram_params) 390 { 391 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 392 u32 cs, bw, die_bw, col, row, bank; 393 u32 cs1_row; 394 u32 i, tmp; 395 u32 ddrconf = -1; 396 u32 row_3_4; 397 398 cs = cap_info->rank; 399 bw = cap_info->bw; 400 die_bw = cap_info->dbw; 401 col = cap_info->col; 402 row = cap_info->cs0_row; 403 cs1_row = cap_info->cs1_row; 404 bank = cap_info->bk; 405 row_3_4 = cap_info->row_3_4; 406 407 if (sdram_params->base.dramtype == DDR4) { 408 if (cs == 2 && row == cs1_row && !row_3_4) { 409 tmp = ((row - 13) << 4) | (1 << 3) | (bw << 1) | 410 die_bw; 411 for (i = 17; i < 21; i++) { 412 if (((tmp & 0xf) == 413 (ddr4_cfg_2_rbc[i - 10] & 0xf)) && 414 ((tmp & 0x70) <= 415 (ddr4_cfg_2_rbc[i - 10] & 0x70))) { 416 ddrconf = i; 417 goto out; 418 } 419 } 420 } 421 422 tmp = ((cs - 1) << 7) | ((row - 13) << 4) | (bw << 1) | die_bw; 423 for (i = 10; i < 21; i++) { 424 if (((tmp & 0xf) == (ddr4_cfg_2_rbc[i - 10] & 0xf)) && 425 ((tmp & 0x70) <= (ddr4_cfg_2_rbc[i - 10] & 0x70)) && 426 ((tmp & 0x80) <= (ddr4_cfg_2_rbc[i - 10] & 0x80))) { 427 ddrconf = i; 428 goto out; 429 } 430 } 431 } else { 432 if (cs == 2 && row == cs1_row && bank == 3) { 433 for (i = 5; i < 8; i++) { 434 if (((bw + col - 10) == (ddr_cfg_2_rbc[i] & 435 0x7)) && 436 ((row - 13) << 5) <= (ddr_cfg_2_rbc[i] & 437 (0x7 << 5))) { 438 ddrconf = i; 439 goto out; 440 } 441 } 442 } 443 444 tmp = ((cs - 1) << 8) | ((row - 13) << 5) | 445 ((bw + col - 10) << 0); 446 if (bank == 3) 447 tmp |= (1 << 3); 448 449 for (i = 0; i < 9; i++) 450 if (((tmp & 0x1f) == (ddr_cfg_2_rbc[i] & 0x1f)) && 451 ((tmp & (7 << 5)) <= 452 (ddr_cfg_2_rbc[i] & (7 << 5))) && 453 ((tmp & (1 << 8)) <= 454 (ddr_cfg_2_rbc[i] & (1 << 8)))) { 455 ddrconf = i; 456 goto out; 457 } 458 459 for (i = 0; i < 7; i++) 460 if (((tmp & 0x1f) == (ddr_cfg_2_rbc_p2[i] & 0x1f)) && 461 ((tmp & (7 << 5)) <= 462 (ddr_cfg_2_rbc_p2[i] & (7 << 5))) && 463 ((tmp & (1 << 8)) <= 464 (ddr_cfg_2_rbc_p2[i] & (1 << 8)))) { 465 ddrconf = i + 22; 466 goto out; 467 } 468 469 if (cs == 1 && bank == 3 && row <= 17 && 470 (col + bw) == 12) 471 ddrconf = 23; 472 } 473 474 out: 475 if (ddrconf > 28) 476 printascii("calculate ddrconfig error\n"); 477 478 if (sdram_params->base.dramtype == DDR4) { 479 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { 480 if (ddrconf == d4_rbc_2_d3_rbc[i][0]) { 481 if (ddrconf == 21 && row > 16) 482 printascii("warn:ddrconf21 row > 16\n"); 483 else 484 ddrconf = d4_rbc_2_d3_rbc[i][1]; 485 break; 486 } 487 } 488 } 489 490 return ddrconf; 491 } 492 493 static void sw_set_req(struct dram_info *dram) 494 { 495 void __iomem *pctl_base = dram->pctl; 496 497 /* clear sw_done=0 */ 498 writel(PCTL2_SW_DONE_CLEAR, pctl_base + DDR_PCTL2_SWCTL); 499 } 500 501 static void sw_set_ack(struct dram_info *dram) 502 { 503 void __iomem *pctl_base = dram->pctl; 504 505 /* set sw_done=1 */ 506 writel(PCTL2_SW_DONE, pctl_base + DDR_PCTL2_SWCTL); 507 while (1) { 508 /* wait programming done */ 509 if (readl(pctl_base + DDR_PCTL2_SWSTAT) & 510 PCTL2_SW_DONE_ACK) 511 break; 512 } 513 } 514 515 static void set_ctl_address_map(struct dram_info *dram, 516 struct rv1126_sdram_params *sdram_params) 517 { 518 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 519 void __iomem *pctl_base = dram->pctl; 520 u32 ddrconf = cap_info->ddrconfig; 521 u32 i, row; 522 523 row = cap_info->cs0_row; 524 if (sdram_params->base.dramtype == DDR4) { 525 for (i = 0; i < ARRAY_SIZE(d4_rbc_2_d3_rbc) ; i++) { 526 if (ddrconf == d4_rbc_2_d3_rbc[i][1]) { 527 ddrconf = d4_rbc_2_d3_rbc[i][0]; 528 break; 529 } 530 } 531 } 532 533 if (ddrconf >= ARRAY_SIZE(addrmap)) { 534 printascii("set ctl address map fail\n"); 535 return; 536 } 537 538 sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0), 539 &addrmap[ddrconf][0], ARRAY_SIZE(addrmap[ddrconf]) * 4); 540 541 /* unused row set to 0xf */ 542 for (i = 17; i >= row; i--) 543 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + 544 ((i - 12) * 8 / 32) * 4, 545 0xf << ((i - 12) * 8 % 32)); 546 547 if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4) 548 setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31); 549 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) 550 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); 551 552 if (cap_info->rank == 1) 553 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f); 554 } 555 556 static void phy_pll_set(struct dram_info *dram, u32 freq, u32 wait) 557 { 558 void __iomem *phy_base = dram->phy; 559 u32 fbdiv, prediv, postdiv, postdiv_en; 560 561 if (wait) { 562 clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB); 563 while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) 564 continue; 565 } else { 566 freq /= MHz; 567 prediv = 1; 568 if (freq <= 200) { 569 fbdiv = 16; 570 postdiv = 2; 571 postdiv_en = 1; 572 } else if (freq <= 456) { 573 fbdiv = 8; 574 postdiv = 1; 575 postdiv_en = 1; 576 } else { 577 fbdiv = 4; 578 postdiv = 0; 579 postdiv_en = 0; 580 } 581 writel(fbdiv & 0xff, PHY_REG(phy_base, 0x50)); 582 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_PBDIV_BIT9_MASK, 583 (fbdiv >> 8) & 1); 584 clrsetbits_le32(PHY_REG(phy_base, 0x51), PHY_POSTDIV_EN_MASK, 585 postdiv_en << PHY_POSTDIV_EN_SHIFT); 586 587 clrsetbits_le32(PHY_REG(phy_base, 0x52), 588 PHY_PREDIV_MASK << PHY_PREDIV_SHIFT, prediv); 589 clrsetbits_le32(PHY_REG(phy_base, 0x53), 590 PHY_POSTDIV_MASK << PHY_POSTDIV_SHIFT, 591 postdiv << PHY_POSTDIV_SHIFT); 592 } 593 } 594 595 static const u16 d3_phy_drv_2_ohm[][2] = { 596 {PHY_DDR3_RON_455ohm, 455}, 597 {PHY_DDR3_RON_230ohm, 230}, 598 {PHY_DDR3_RON_153ohm, 153}, 599 {PHY_DDR3_RON_115ohm, 115}, 600 {PHY_DDR3_RON_91ohm, 91}, 601 {PHY_DDR3_RON_76ohm, 76}, 602 {PHY_DDR3_RON_65ohm, 65}, 603 {PHY_DDR3_RON_57ohm, 57}, 604 {PHY_DDR3_RON_51ohm, 51}, 605 {PHY_DDR3_RON_46ohm, 46}, 606 {PHY_DDR3_RON_41ohm, 41}, 607 {PHY_DDR3_RON_38ohm, 38}, 608 {PHY_DDR3_RON_35ohm, 35}, 609 {PHY_DDR3_RON_32ohm, 32}, 610 {PHY_DDR3_RON_30ohm, 30}, 611 {PHY_DDR3_RON_28ohm, 28}, 612 {PHY_DDR3_RON_27ohm, 27}, 613 {PHY_DDR3_RON_25ohm, 25}, 614 {PHY_DDR3_RON_24ohm, 24}, 615 {PHY_DDR3_RON_23ohm, 23}, 616 {PHY_DDR3_RON_22ohm, 22}, 617 {PHY_DDR3_RON_21ohm, 21}, 618 {PHY_DDR3_RON_20ohm, 20} 619 }; 620 621 static u16 d3_phy_odt_2_ohm[][2] = { 622 {PHY_DDR3_RTT_DISABLE, 0}, 623 {PHY_DDR3_RTT_561ohm, 561}, 624 {PHY_DDR3_RTT_282ohm, 282}, 625 {PHY_DDR3_RTT_188ohm, 188}, 626 {PHY_DDR3_RTT_141ohm, 141}, 627 {PHY_DDR3_RTT_113ohm, 113}, 628 {PHY_DDR3_RTT_94ohm, 94}, 629 {PHY_DDR3_RTT_81ohm, 81}, 630 {PHY_DDR3_RTT_72ohm, 72}, 631 {PHY_DDR3_RTT_64ohm, 64}, 632 {PHY_DDR3_RTT_58ohm, 58}, 633 {PHY_DDR3_RTT_52ohm, 52}, 634 {PHY_DDR3_RTT_48ohm, 48}, 635 {PHY_DDR3_RTT_44ohm, 44}, 636 {PHY_DDR3_RTT_41ohm, 41}, 637 {PHY_DDR3_RTT_38ohm, 38}, 638 {PHY_DDR3_RTT_37ohm, 37}, 639 {PHY_DDR3_RTT_34ohm, 34}, 640 {PHY_DDR3_RTT_32ohm, 32}, 641 {PHY_DDR3_RTT_31ohm, 31}, 642 {PHY_DDR3_RTT_29ohm, 29}, 643 {PHY_DDR3_RTT_28ohm, 28}, 644 {PHY_DDR3_RTT_27ohm, 27}, 645 {PHY_DDR3_RTT_25ohm, 25} 646 }; 647 648 static u16 d4lp3_phy_drv_2_ohm[][2] = { 649 {PHY_DDR4_LPDDR3_RON_482ohm, 482}, 650 {PHY_DDR4_LPDDR3_RON_244ohm, 244}, 651 {PHY_DDR4_LPDDR3_RON_162ohm, 162}, 652 {PHY_DDR4_LPDDR3_RON_122ohm, 122}, 653 {PHY_DDR4_LPDDR3_RON_97ohm, 97}, 654 {PHY_DDR4_LPDDR3_RON_81ohm, 81}, 655 {PHY_DDR4_LPDDR3_RON_69ohm, 69}, 656 {PHY_DDR4_LPDDR3_RON_61ohm, 61}, 657 {PHY_DDR4_LPDDR3_RON_54ohm, 54}, 658 {PHY_DDR4_LPDDR3_RON_48ohm, 48}, 659 {PHY_DDR4_LPDDR3_RON_44ohm, 44}, 660 {PHY_DDR4_LPDDR3_RON_40ohm, 40}, 661 {PHY_DDR4_LPDDR3_RON_37ohm, 37}, 662 {PHY_DDR4_LPDDR3_RON_34ohm, 34}, 663 {PHY_DDR4_LPDDR3_RON_32ohm, 32}, 664 {PHY_DDR4_LPDDR3_RON_30ohm, 30}, 665 {PHY_DDR4_LPDDR3_RON_28ohm, 28}, 666 {PHY_DDR4_LPDDR3_RON_27ohm, 27}, 667 {PHY_DDR4_LPDDR3_RON_25ohm, 25}, 668 {PHY_DDR4_LPDDR3_RON_24ohm, 24}, 669 {PHY_DDR4_LPDDR3_RON_23ohm, 23}, 670 {PHY_DDR4_LPDDR3_RON_22ohm, 22}, 671 {PHY_DDR4_LPDDR3_RON_21ohm, 21} 672 }; 673 674 static u16 d4lp3_phy_odt_2_ohm[][2] = { 675 {PHY_DDR4_LPDDR3_RTT_DISABLE, 0}, 676 {PHY_DDR4_LPDDR3_RTT_586ohm, 586}, 677 {PHY_DDR4_LPDDR3_RTT_294ohm, 294}, 678 {PHY_DDR4_LPDDR3_RTT_196ohm, 196}, 679 {PHY_DDR4_LPDDR3_RTT_148ohm, 148}, 680 {PHY_DDR4_LPDDR3_RTT_118ohm, 118}, 681 {PHY_DDR4_LPDDR3_RTT_99ohm, 99}, 682 {PHY_DDR4_LPDDR3_RTT_85ohm, 58}, 683 {PHY_DDR4_LPDDR3_RTT_76ohm, 76}, 684 {PHY_DDR4_LPDDR3_RTT_67ohm, 67}, 685 {PHY_DDR4_LPDDR3_RTT_60ohm, 60}, 686 {PHY_DDR4_LPDDR3_RTT_55ohm, 55}, 687 {PHY_DDR4_LPDDR3_RTT_50ohm, 50}, 688 {PHY_DDR4_LPDDR3_RTT_46ohm, 46}, 689 {PHY_DDR4_LPDDR3_RTT_43ohm, 43}, 690 {PHY_DDR4_LPDDR3_RTT_40ohm, 40}, 691 {PHY_DDR4_LPDDR3_RTT_38ohm, 38}, 692 {PHY_DDR4_LPDDR3_RTT_36ohm, 36}, 693 {PHY_DDR4_LPDDR3_RTT_34ohm, 34}, 694 {PHY_DDR4_LPDDR3_RTT_32ohm, 32}, 695 {PHY_DDR4_LPDDR3_RTT_31ohm, 31}, 696 {PHY_DDR4_LPDDR3_RTT_29ohm, 29}, 697 {PHY_DDR4_LPDDR3_RTT_28ohm, 28}, 698 {PHY_DDR4_LPDDR3_RTT_27ohm, 27} 699 }; 700 701 static u16 lp4_phy_drv_2_ohm[][2] = { 702 {PHY_LPDDR4_RON_501ohm, 501}, 703 {PHY_LPDDR4_RON_253ohm, 253}, 704 {PHY_LPDDR4_RON_168ohm, 168}, 705 {PHY_LPDDR4_RON_126ohm, 126}, 706 {PHY_LPDDR4_RON_101ohm, 101}, 707 {PHY_LPDDR4_RON_84ohm, 84}, 708 {PHY_LPDDR4_RON_72ohm, 72}, 709 {PHY_LPDDR4_RON_63ohm, 63}, 710 {PHY_LPDDR4_RON_56ohm, 56}, 711 {PHY_LPDDR4_RON_50ohm, 50}, 712 {PHY_LPDDR4_RON_46ohm, 46}, 713 {PHY_LPDDR4_RON_42ohm, 42}, 714 {PHY_LPDDR4_RON_38ohm, 38}, 715 {PHY_LPDDR4_RON_36ohm, 36}, 716 {PHY_LPDDR4_RON_33ohm, 33}, 717 {PHY_LPDDR4_RON_31ohm, 31}, 718 {PHY_LPDDR4_RON_29ohm, 29}, 719 {PHY_LPDDR4_RON_28ohm, 28}, 720 {PHY_LPDDR4_RON_26ohm, 26}, 721 {PHY_LPDDR4_RON_25ohm, 25}, 722 {PHY_LPDDR4_RON_24ohm, 24}, 723 {PHY_LPDDR4_RON_23ohm, 23}, 724 {PHY_LPDDR4_RON_22ohm, 22} 725 }; 726 727 static u16 lp4_phy_odt_2_ohm[][2] = { 728 {PHY_LPDDR4_RTT_DISABLE, 0}, 729 {PHY_LPDDR4_RTT_604ohm, 604}, 730 {PHY_LPDDR4_RTT_303ohm, 303}, 731 {PHY_LPDDR4_RTT_202ohm, 202}, 732 {PHY_LPDDR4_RTT_152ohm, 152}, 733 {PHY_LPDDR4_RTT_122ohm, 122}, 734 {PHY_LPDDR4_RTT_101ohm, 101}, 735 {PHY_LPDDR4_RTT_87ohm, 87}, 736 {PHY_LPDDR4_RTT_78ohm, 78}, 737 {PHY_LPDDR4_RTT_69ohm, 69}, 738 {PHY_LPDDR4_RTT_62ohm, 62}, 739 {PHY_LPDDR4_RTT_56ohm, 56}, 740 {PHY_LPDDR4_RTT_52ohm, 52}, 741 {PHY_LPDDR4_RTT_48ohm, 48}, 742 {PHY_LPDDR4_RTT_44ohm, 44}, 743 {PHY_LPDDR4_RTT_41ohm, 41}, 744 {PHY_LPDDR4_RTT_39ohm, 39}, 745 {PHY_LPDDR4_RTT_37ohm, 37}, 746 {PHY_LPDDR4_RTT_35ohm, 35}, 747 {PHY_LPDDR4_RTT_33ohm, 33}, 748 {PHY_LPDDR4_RTT_32ohm, 32}, 749 {PHY_LPDDR4_RTT_30ohm, 30}, 750 {PHY_LPDDR4_RTT_29ohm, 29}, 751 {PHY_LPDDR4_RTT_27ohm, 27} 752 }; 753 754 static u32 lp4_odt_calc(u32 odt_ohm) 755 { 756 u32 odt; 757 758 if (odt_ohm == 0) 759 odt = LPDDR4_DQODT_DIS; 760 else if (odt_ohm <= 40) 761 odt = LPDDR4_DQODT_40; 762 else if (odt_ohm <= 48) 763 odt = LPDDR4_DQODT_48; 764 else if (odt_ohm <= 60) 765 odt = LPDDR4_DQODT_60; 766 else if (odt_ohm <= 80) 767 odt = LPDDR4_DQODT_80; 768 else if (odt_ohm <= 120) 769 odt = LPDDR4_DQODT_120; 770 else 771 odt = LPDDR4_DQODT_240; 772 773 return odt; 774 } 775 776 static void *get_ddr_drv_odt_info(u32 dramtype) 777 { 778 struct sdram_head_info_index_v2 *index = 779 (struct sdram_head_info_index_v2 *)common_info; 780 void *ddr_info = 0; 781 782 if (dramtype == DDR4) 783 ddr_info = (void *)common_info + index->ddr4_index.offset * 4; 784 else if (dramtype == DDR3) 785 ddr_info = (void *)common_info + index->ddr3_index.offset * 4; 786 else if (dramtype == LPDDR3) 787 ddr_info = (void *)common_info + index->lp3_index.offset * 4; 788 else if (dramtype == LPDDR4) 789 ddr_info = (void *)common_info + index->lp4_index.offset * 4; 790 else if (dramtype == LPDDR4X) 791 ddr_info = (void *)common_info + index->lp4x_index.offset * 4; 792 else 793 printascii("unsupported dram type\n"); 794 return ddr_info; 795 } 796 797 static void set_lp4_vref(struct dram_info *dram, struct lp4_info *lp4_info, 798 u32 freq_mhz, u32 dst_fsp, u32 dramtype) 799 { 800 void __iomem *pctl_base = dram->pctl; 801 u32 ca_vref, dq_vref; 802 803 if (freq_mhz <= LP4_CA_ODT_EN_FREQ(lp4_info->ca_odten_freq)) 804 ca_vref = LP4_CA_VREF(lp4_info->vref_when_odtoff); 805 else 806 ca_vref = LP4_CA_VREF(lp4_info->vref_when_odten); 807 808 if (freq_mhz <= LP4_DQ_ODT_EN_FREQ(lp4_info->dq_odten_freq)) 809 dq_vref = LP4_DQ_VREF(lp4_info->vref_when_odtoff); 810 else 811 dq_vref = LP4_DQ_VREF(lp4_info->vref_when_odten); 812 813 if (dramtype == LPDDR4) { 814 if (ca_vref < 100) 815 ca_vref = 100; 816 if (ca_vref > 420) 817 ca_vref = 420; 818 819 if (ca_vref <= 300) 820 ca_vref = (0 << 6) | (ca_vref - 100) / 4; 821 else 822 ca_vref = (1 << 6) | (ca_vref - 220) / 4; 823 824 if (dq_vref < 100) 825 dq_vref = 100; 826 if (dq_vref > 420) 827 dq_vref = 420; 828 829 if (dq_vref <= 300) 830 dq_vref = (0 << 6) | (dq_vref - 100) / 4; 831 else 832 dq_vref = (1 << 6) | (dq_vref - 220) / 4; 833 } else { 834 ca_vref = ca_vref * 11 / 6; 835 if (ca_vref < 150) 836 ca_vref = 150; 837 if (ca_vref > 629) 838 ca_vref = 629; 839 840 if (ca_vref <= 449) 841 ca_vref = (0 << 6) | (ca_vref - 150) / 4; 842 else 843 ca_vref = (1 << 6) | (ca_vref - 329) / 4; 844 845 if (dq_vref < 150) 846 dq_vref = 150; 847 if (dq_vref > 629) 848 dq_vref = 629; 849 850 if (dq_vref <= 449) 851 dq_vref = (0 << 6) | (dq_vref - 150) / 6; 852 else 853 dq_vref = (1 << 6) | (dq_vref - 329) / 6; 854 } 855 sw_set_req(dram); 856 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 857 DDR_PCTL2_INIT6, 858 PCTL2_MR_MASK << PCTL2_LPDDR4_MR12_SHIFT, 859 ca_vref << PCTL2_LPDDR4_MR12_SHIFT); 860 861 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 862 DDR_PCTL2_INIT7, 863 PCTL2_MR_MASK << PCTL2_LPDDR4_MR14_SHIFT, 864 dq_vref << PCTL2_LPDDR4_MR14_SHIFT); 865 sw_set_ack(dram); 866 } 867 868 static void set_ds_odt(struct dram_info *dram, 869 struct rv1126_sdram_params *sdram_params, u32 dst_fsp) 870 { 871 void __iomem *phy_base = dram->phy; 872 void __iomem *pctl_base = dram->pctl; 873 u32 dramtype = sdram_params->base.dramtype; 874 struct ddr2_3_4_lp2_3_info *ddr_info; 875 struct lp4_info *lp4_info; 876 u32 i, j, tmp; 877 const u16 (*p_drv)[2]; 878 const u16 (*p_odt)[2]; 879 u32 drv_info, sr_info; 880 u32 phy_dq_drv_ohm, phy_clk_drv_ohm, phy_ca_drv_ohm, dram_drv_ohm; 881 u32 phy_odt_ohm, dram_odt_ohm; 882 u32 lp4_pu_cal, phy_lp4_drv_pd_en; 883 u32 phy_odt_up_en, phy_odt_dn_en; 884 u32 sr_dq, sr_clk; 885 u32 freq = sdram_params->base.ddr_freq; 886 u32 mr1_mr3, mr11, mr22, vref_out, vref_inner; 887 u32 phy_clk_drv = 0, phy_odt = 0, phy_ca_drv = 0, dram_caodt_ohm = 0; 888 u32 phy_dq_drv = 0; 889 u32 phy_odt_up = 0, phy_odt_dn = 0; 890 891 ddr_info = get_ddr_drv_odt_info(dramtype); 892 lp4_info = (void *)ddr_info; 893 894 if (!ddr_info) 895 return; 896 897 /* dram odt en freq control phy drv, dram odt and phy sr */ 898 if (freq <= DRAMODT_EN_FREQ(ddr_info->odten_freq)) { 899 drv_info = ddr_info->drv_when_odtoff; 900 dram_odt_ohm = 0; 901 sr_info = ddr_info->sr_when_odtoff; 902 phy_lp4_drv_pd_en = 903 PHY_LP4_DRV_PULLDOWN_EN_ODTOFF(lp4_info->odt_info); 904 } else { 905 drv_info = ddr_info->drv_when_odten; 906 dram_odt_ohm = ODT_INFO_DRAM_ODT(ddr_info->odt_info); 907 sr_info = ddr_info->sr_when_odten; 908 phy_lp4_drv_pd_en = 909 PHY_LP4_DRV_PULLDOWN_EN_ODTEN(lp4_info->odt_info); 910 } 911 phy_dq_drv_ohm = 912 DRV_INFO_PHY_DQ_DRV(drv_info); 913 phy_clk_drv_ohm = 914 DRV_INFO_PHY_CLK_DRV(drv_info); 915 phy_ca_drv_ohm = 916 DRV_INFO_PHY_CA_DRV(drv_info); 917 918 sr_dq = DQ_SR_INFO(sr_info); 919 sr_clk = CLK_SR_INFO(sr_info); 920 921 /* phy odt en freq control dram drv and phy odt */ 922 if (freq <= PHYODT_EN_FREQ(ddr_info->odten_freq)) { 923 dram_drv_ohm = DRV_INFO_DRAM_DQ_DRV(ddr_info->drv_when_odtoff); 924 lp4_pu_cal = LP4_DRV_PU_CAL_ODTOFF(lp4_info->odt_info); 925 phy_odt_ohm = 0; 926 phy_odt_up_en = 0; 927 phy_odt_dn_en = 0; 928 } else { 929 dram_drv_ohm = 930 DRV_INFO_DRAM_DQ_DRV(ddr_info->drv_when_odten); 931 phy_odt_ohm = ODT_INFO_PHY_ODT(ddr_info->odt_info); 932 phy_odt_up_en = 933 ODT_INFO_PULLUP_EN(ddr_info->odt_info); 934 phy_odt_dn_en = 935 ODT_INFO_PULLDOWN_EN(ddr_info->odt_info); 936 lp4_pu_cal = LP4_DRV_PU_CAL_ODTEN(lp4_info->odt_info); 937 } 938 939 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 940 if (phy_odt_ohm) { 941 phy_odt_up_en = 0; 942 phy_odt_dn_en = 1; 943 } 944 if (freq <= LP4_CA_ODT_EN_FREQ(lp4_info->ca_odten_freq)) 945 dram_caodt_ohm = 0; 946 else 947 dram_caodt_ohm = 948 ODT_INFO_LP4_CA_ODT(lp4_info->odt_info); 949 } 950 951 if (dramtype == DDR3) { 952 p_drv = d3_phy_drv_2_ohm; 953 p_odt = d3_phy_odt_2_ohm; 954 } else if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 955 p_drv = lp4_phy_drv_2_ohm; 956 p_odt = lp4_phy_odt_2_ohm; 957 } else { 958 p_drv = d4lp3_phy_drv_2_ohm; 959 p_odt = d4lp3_phy_odt_2_ohm; 960 } 961 962 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { 963 if (phy_dq_drv_ohm <= *(*(p_drv + i) + 1)) { 964 phy_dq_drv = **(p_drv + i); 965 break; 966 } 967 if (i == 0) 968 break; 969 } 970 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { 971 if (phy_clk_drv_ohm <= *(*(p_drv + i) + 1)) { 972 phy_clk_drv = **(p_drv + i); 973 break; 974 } 975 if (i == 0) 976 break; 977 } 978 for (i = ARRAY_SIZE(d3_phy_drv_2_ohm) - 1; ; i--) { 979 if (phy_ca_drv_ohm <= *(*(p_drv + i) + 1)) { 980 phy_ca_drv = **(p_drv + i); 981 break; 982 } 983 if (i == 0) 984 break; 985 } 986 if (!phy_odt_ohm) 987 phy_odt = 0; 988 else 989 for (i = ARRAY_SIZE(d4lp3_phy_odt_2_ohm) - 1; ; i--) { 990 if (phy_odt_ohm <= *(*(p_odt + i) + 1)) { 991 phy_odt = **(p_odt + i); 992 break; 993 } 994 if (i == 0) 995 break; 996 } 997 998 if (dramtype != LPDDR4 && dramtype != LPDDR4X) { 999 if (!phy_odt_ohm || (phy_odt_up_en && phy_odt_dn_en)) 1000 vref_inner = 0x80; 1001 else if (phy_odt_up_en) 1002 vref_inner = (2 * dram_drv_ohm + phy_odt_ohm) * 128 / 1003 (dram_drv_ohm + phy_odt_ohm); 1004 else 1005 vref_inner = phy_odt_ohm * 128 / 1006 (phy_odt_ohm + dram_drv_ohm); 1007 1008 if (dramtype != DDR3 && dram_odt_ohm) 1009 vref_out = (2 * phy_dq_drv_ohm + dram_odt_ohm) * 128 / 1010 (phy_dq_drv_ohm + dram_odt_ohm); 1011 else 1012 vref_out = 0x80; 1013 } else { 1014 /* for lp4 and lp4x*/ 1015 if (phy_odt_ohm) 1016 vref_inner = 1017 (PHY_LP4_DQ_VREF(lp4_info->vref_when_odten) * 1018 256) / 1000; 1019 else 1020 vref_inner = 1021 (PHY_LP4_DQ_VREF(lp4_info->vref_when_odtoff) * 1022 256) / 1000; 1023 1024 vref_out = 0x80; 1025 } 1026 1027 /* default ZQCALIB bypass mode */ 1028 clrsetbits_le32(PHY_REG(phy_base, 0x100), 0x1f, phy_ca_drv); 1029 clrsetbits_le32(PHY_REG(phy_base, 0x101), 0x1f, phy_ca_drv); 1030 clrsetbits_le32(PHY_REG(phy_base, 0x102), 0x1f, phy_clk_drv); 1031 clrsetbits_le32(PHY_REG(phy_base, 0x103), 0x1f, phy_clk_drv); 1032 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 1033 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_clk_drv); 1034 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_clk_drv); 1035 } else { 1036 clrsetbits_le32(PHY_REG(phy_base, 0x107), 0x1f, phy_ca_drv); 1037 clrsetbits_le32(PHY_REG(phy_base, 0x108), 0x1f, phy_ca_drv); 1038 } 1039 /* clk / cmd slew rate */ 1040 clrsetbits_le32(PHY_REG(phy_base, 0x106), 0x1f, sr_clk); 1041 1042 phy_lp4_drv_pd_en = (~phy_lp4_drv_pd_en) & 1; 1043 if (phy_odt_up_en) 1044 phy_odt_up = phy_odt; 1045 if (phy_odt_dn_en) 1046 phy_odt_dn = phy_odt; 1047 1048 for (i = 0; i < 4; i++) { 1049 j = 0x110 + i * 0x10; 1050 clrsetbits_le32(PHY_REG(phy_base, j + 1), 0x1f, phy_odt_up); 1051 clrsetbits_le32(PHY_REG(phy_base, j), 0x1f, phy_odt_dn); 1052 clrsetbits_le32(PHY_REG(phy_base, j + 2), 0x1f, phy_dq_drv); 1053 clrsetbits_le32(PHY_REG(phy_base, j + 3), 0x1f, phy_dq_drv); 1054 writel(vref_inner, PHY_REG(phy_base, 0x118 + i * 0x10)); 1055 1056 clrsetbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), 1057 1 << 3, phy_lp4_drv_pd_en << 3); 1058 if (dramtype == LPDDR4 || dramtype == LPDDR4X) 1059 clrbits_le32(PHY_REG(phy_base, 0x114 + i * 0x10), BIT(5)); 1060 /* dq slew rate */ 1061 clrsetbits_le32(PHY_REG(phy_base, 0x117 + i * 0x10), 1062 0x1f, sr_dq); 1063 } 1064 1065 /* reg_rx_vref_value_update */ 1066 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1067 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1068 1069 /* RAM VREF */ 1070 writel(vref_out, PHY_REG(phy_base, 0x105)); 1071 if (dramtype == LPDDR3) 1072 udelay(100); 1073 1074 if (dramtype == LPDDR4 || dramtype == LPDDR4X) 1075 set_lp4_vref(dram, lp4_info, freq, dst_fsp, dramtype); 1076 1077 if (dramtype == DDR3 || dramtype == DDR4) { 1078 mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1079 DDR_PCTL2_INIT3); 1080 mr1_mr3 = mr1_mr3 >> PCTL2_DDR34_MR1_SHIFT & PCTL2_MR_MASK; 1081 } else { 1082 mr1_mr3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1083 DDR_PCTL2_INIT4); 1084 mr1_mr3 = mr1_mr3 >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK; 1085 } 1086 1087 if (dramtype == DDR3) { 1088 mr1_mr3 &= ~(DDR3_DS_MASK | DDR3_RTT_NOM_MASK); 1089 if (dram_drv_ohm == 34) 1090 mr1_mr3 |= DDR3_DS_34; 1091 1092 if (dram_odt_ohm == 0) 1093 mr1_mr3 |= DDR3_RTT_NOM_DIS; 1094 else if (dram_odt_ohm <= 40) 1095 mr1_mr3 |= DDR3_RTT_NOM_40; 1096 else if (dram_odt_ohm <= 60) 1097 mr1_mr3 |= DDR3_RTT_NOM_60; 1098 else 1099 mr1_mr3 |= DDR3_RTT_NOM_120; 1100 1101 } else if (dramtype == DDR4) { 1102 mr1_mr3 &= ~(DDR4_DS_MASK | DDR4_RTT_NOM_MASK); 1103 if (dram_drv_ohm == 48) 1104 mr1_mr3 |= DDR4_DS_48; 1105 1106 if (dram_odt_ohm == 0) 1107 mr1_mr3 |= DDR4_RTT_NOM_DIS; 1108 else if (dram_odt_ohm <= 34) 1109 mr1_mr3 |= DDR4_RTT_NOM_34; 1110 else if (dram_odt_ohm <= 40) 1111 mr1_mr3 |= DDR4_RTT_NOM_40; 1112 else if (dram_odt_ohm <= 48) 1113 mr1_mr3 |= DDR4_RTT_NOM_48; 1114 else if (dram_odt_ohm <= 60) 1115 mr1_mr3 |= DDR4_RTT_NOM_60; 1116 else 1117 mr1_mr3 |= DDR4_RTT_NOM_120; 1118 1119 } else if (dramtype == LPDDR3) { 1120 if (dram_drv_ohm <= 34) 1121 mr1_mr3 |= LPDDR3_DS_34; 1122 else if (dram_drv_ohm <= 40) 1123 mr1_mr3 |= LPDDR3_DS_40; 1124 else if (dram_drv_ohm <= 48) 1125 mr1_mr3 |= LPDDR3_DS_48; 1126 else if (dram_drv_ohm <= 60) 1127 mr1_mr3 |= LPDDR3_DS_60; 1128 else if (dram_drv_ohm <= 80) 1129 mr1_mr3 |= LPDDR3_DS_80; 1130 1131 if (dram_odt_ohm == 0) 1132 lp3_odt_value = LPDDR3_ODT_DIS; 1133 else if (dram_odt_ohm <= 60) 1134 lp3_odt_value = LPDDR3_ODT_60; 1135 else if (dram_odt_ohm <= 120) 1136 lp3_odt_value = LPDDR3_ODT_120; 1137 else 1138 lp3_odt_value = LPDDR3_ODT_240; 1139 } else {/* for lpddr4 and lpddr4x */ 1140 /* MR3 for lp4 PU-CAL and PDDS */ 1141 mr1_mr3 &= ~(LPDDR4_PDDS_MASK | LPDDR4_PU_CAL_MASK); 1142 mr1_mr3 |= lp4_pu_cal; 1143 1144 tmp = lp4_odt_calc(dram_drv_ohm); 1145 if (!tmp) 1146 tmp = LPDDR4_PDDS_240; 1147 mr1_mr3 |= (tmp << LPDDR4_PDDS_SHIFT); 1148 1149 /* MR11 for lp4 ca odt, dq odt set */ 1150 mr11 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1151 DDR_PCTL2_INIT6); 1152 mr11 = mr11 >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK; 1153 1154 mr11 &= ~(LPDDR4_DQODT_MASK | LPDDR4_CAODT_MASK); 1155 1156 tmp = lp4_odt_calc(dram_odt_ohm); 1157 mr11 |= (tmp << LPDDR4_DQODT_SHIFT); 1158 1159 tmp = lp4_odt_calc(dram_caodt_ohm); 1160 mr11 |= (tmp << LPDDR4_CAODT_SHIFT); 1161 sw_set_req(dram); 1162 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1163 DDR_PCTL2_INIT6, 1164 PCTL2_MR_MASK << PCTL2_LPDDR4_MR11_SHIFT, 1165 mr11 << PCTL2_LPDDR4_MR11_SHIFT); 1166 sw_set_ack(dram); 1167 1168 /* MR22 for soc odt/odt-ck/odt-cs/odt-ca */ 1169 mr22 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1170 DDR_PCTL2_INIT7); 1171 mr22 = mr22 >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK; 1172 mr22 &= ~LPDDR4_SOC_ODT_MASK; 1173 1174 tmp = lp4_odt_calc(phy_odt_ohm); 1175 mr22 |= tmp; 1176 mr22 = mr22 | 1177 (LP4_ODTE_CK_EN(lp4_info->cs_drv_ca_odt_info) << 1178 LPDDR4_ODTE_CK_SHIFT) | 1179 (LP4_ODTE_CS_EN(lp4_info->cs_drv_ca_odt_info) << 1180 LPDDR4_ODTE_CS_SHIFT) | 1181 (LP4_ODTD_CA_EN(lp4_info->cs_drv_ca_odt_info) << 1182 LPDDR4_ODTD_CA_SHIFT); 1183 1184 sw_set_req(dram); 1185 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1186 DDR_PCTL2_INIT7, 1187 PCTL2_MR_MASK << PCTL2_LPDDR4_MR22_SHIFT, 1188 mr22 << PCTL2_LPDDR4_MR22_SHIFT); 1189 sw_set_ack(dram); 1190 } 1191 1192 if (dramtype == DDR4 || dramtype == DDR3) { 1193 sw_set_req(dram); 1194 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1195 DDR_PCTL2_INIT3, 1196 PCTL2_MR_MASK << PCTL2_DDR34_MR1_SHIFT, 1197 mr1_mr3 << PCTL2_DDR34_MR1_SHIFT); 1198 sw_set_ack(dram); 1199 } else { 1200 sw_set_req(dram); 1201 clrsetbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 1202 DDR_PCTL2_INIT4, 1203 PCTL2_MR_MASK << PCTL2_LPDDR234_MR3_SHIFT, 1204 mr1_mr3 << PCTL2_LPDDR234_MR3_SHIFT); 1205 sw_set_ack(dram); 1206 } 1207 } 1208 1209 static int sdram_cmd_dq_path_remap(struct dram_info *dram, 1210 struct rv1126_sdram_params *sdram_params) 1211 { 1212 void __iomem *phy_base = dram->phy; 1213 u32 dramtype = sdram_params->base.dramtype; 1214 struct sdram_head_info_index_v2 *index = 1215 (struct sdram_head_info_index_v2 *)common_info; 1216 struct dq_map_info *map_info; 1217 1218 map_info = (struct dq_map_info *)((void *)common_info + 1219 index->dq_map_index.offset * 4); 1220 1221 if (dramtype == LPDDR4X) 1222 dramtype = LPDDR4; 1223 1224 if (dramtype <= LPDDR4) 1225 writel((map_info->byte_map[dramtype / 4] >> 1226 ((dramtype % 4) * 8)) & 0xff, 1227 PHY_REG(phy_base, 0x4f)); 1228 1229 return 0; 1230 } 1231 1232 static void phy_cfg(struct dram_info *dram, 1233 struct rv1126_sdram_params *sdram_params) 1234 { 1235 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 1236 void __iomem *phy_base = dram->phy; 1237 u32 i, dq_map, tmp; 1238 u32 byte1 = 0, byte0 = 0; 1239 1240 sdram_cmd_dq_path_remap(dram, sdram_params); 1241 1242 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 0); 1243 for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) { 1244 writel(sdram_params->phy_regs.phy[i][1], 1245 phy_base + sdram_params->phy_regs.phy[i][0]); 1246 } 1247 1248 clrbits_le32(PHY_REG(phy_base, 0x62), BIT(5)); 1249 dq_map = readl(PHY_REG(phy_base, 0x4f)); 1250 for (i = 0; i < 4; i++) { 1251 if (((dq_map >> (i * 2)) & 0x3) == 0) { 1252 byte0 = i; 1253 break; 1254 } 1255 } 1256 for (i = 0; i < 4; i++) { 1257 if (((dq_map >> (i * 2)) & 0x3) == 1) { 1258 byte1 = i; 1259 break; 1260 } 1261 } 1262 1263 tmp = readl(PHY_REG(phy_base, 0xf)) & (~PHY_DQ_WIDTH_MASK); 1264 if (cap_info->bw == 2) 1265 tmp |= 0xf; 1266 else if (cap_info->bw == 1) 1267 tmp |= ((1 << byte0) | (1 << byte1)); 1268 else 1269 tmp |= (1 << byte0); 1270 1271 writel(tmp, PHY_REG(phy_base, 0xf)); 1272 1273 /* lpddr4 odt control by phy, enable cs0 odt */ 1274 if (sdram_params->base.dramtype == LPDDR4 || 1275 sdram_params->base.dramtype == LPDDR4X) 1276 clrsetbits_le32(PHY_REG(phy_base, 0x20), 0x7 << 4, 1277 (1 << 6) | (1 << 4)); 1278 /* for ca training ca vref choose range1 */ 1279 setbits_le32(PHY_REG(phy_base, 0x1e), BIT(6)); 1280 setbits_le32(PHY_REG(phy_base, 0x1f), BIT(6)); 1281 /* for wr training PHY_0x7c[5], choose range0 */ 1282 clrbits_le32(PHY_REG(phy_base, 0x7c), BIT(5)); 1283 } 1284 1285 static int update_refresh_reg(struct dram_info *dram) 1286 { 1287 void __iomem *pctl_base = dram->pctl; 1288 u32 ret; 1289 1290 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1); 1291 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); 1292 1293 return 0; 1294 } 1295 1296 /* 1297 * rank = 1: cs0 1298 * rank = 2: cs1 1299 */ 1300 u32 read_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 dramtype) 1301 { 1302 u32 ret; 1303 u32 i, temp; 1304 void __iomem *pctl_base = dram->pctl; 1305 struct sdram_head_info_index_v2 *index = 1306 (struct sdram_head_info_index_v2 *)common_info; 1307 struct dq_map_info *map_info; 1308 1309 map_info = (struct dq_map_info *)((void *)common_info + 1310 index->dq_map_index.offset * 4); 1311 1312 pctl_read_mr(pctl_base, rank, mr_num); 1313 1314 if (dramtype == LPDDR3) { 1315 temp = (readl(&dram->ddrgrf->ddr_grf_status[0]) & 0xff); 1316 ret = 0; 1317 for (i = 0; i < 8; i++) 1318 ret |= ((temp >> i) & 0x1) << ((map_info->lp3_dq0_7_map >> (i * 4)) & 0xf); 1319 } else { 1320 ret = readl(&dram->ddrgrf->ddr_grf_status[1]) & 0xff; 1321 } 1322 1323 return ret; 1324 } 1325 1326 /* before call this function autorefresh should be disabled */ 1327 void send_a_refresh(struct dram_info *dram) 1328 { 1329 void __iomem *pctl_base = dram->pctl; 1330 1331 while (readl(pctl_base + DDR_PCTL2_DBGSTAT) & 0x3) 1332 continue; 1333 writel(0x3, pctl_base + DDR_PCTL2_DBGCMD); 1334 } 1335 1336 static void enter_sr(struct dram_info *dram, u32 en) 1337 { 1338 void __iomem *pctl_base = dram->pctl; 1339 1340 if (en) { 1341 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); 1342 while (1) { 1343 if (((readl(pctl_base + DDR_PCTL2_STAT) & 1344 PCTL2_SELFREF_TYPE_MASK) == 1345 PCTL2_SELFREF_TYPE_SR_NOT_AUTO) && 1346 ((readl(pctl_base + DDR_PCTL2_STAT) & 1347 PCTL2_OPERATING_MODE_MASK) == 1348 PCTL2_OPERATING_MODE_SR)) 1349 break; 1350 } 1351 } else { 1352 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, PCTL2_SELFREF_SW); 1353 while ((readl(pctl_base + DDR_PCTL2_STAT) & 1354 PCTL2_OPERATING_MODE_MASK) == PCTL2_OPERATING_MODE_SR) 1355 continue; 1356 } 1357 } 1358 1359 void record_dq_prebit(struct dram_info *dram) 1360 { 1361 u32 group, i, tmp; 1362 void __iomem *phy_base = dram->phy; 1363 1364 for (group = 0; group < 4; group++) { 1365 for (i = 0; i < ARRAY_SIZE(dq_sel); i++) { 1366 /* l_loop_invdelaysel */ 1367 writel(dq_sel[i][0], PHY_REG(phy_base, 1368 grp_addr[group] + 0x2c)); 1369 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2e)); 1370 writel(tmp, PHY_REG(phy_base, 1371 grp_addr[group] + dq_sel[i][1])); 1372 1373 /* r_loop_invdelaysel */ 1374 writel(dq_sel[i][0], PHY_REG(phy_base, 1375 grp_addr[group] + 0x2d)); 1376 tmp = readl(PHY_REG(phy_base, grp_addr[group] + 0x2f)); 1377 writel(tmp, PHY_REG(phy_base, 1378 grp_addr[group] + dq_sel[i][2])); 1379 } 1380 } 1381 } 1382 1383 static void update_dq_rx_prebit(struct dram_info *dram) 1384 { 1385 void __iomem *phy_base = dram->phy; 1386 1387 clrsetbits_le32(PHY_REG(phy_base, 0x70), BIT(1) | BIT(6) | BIT(4), 1388 BIT(4)); 1389 udelay(1); 1390 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(4)); 1391 } 1392 1393 static void update_dq_tx_prebit(struct dram_info *dram) 1394 { 1395 void __iomem *phy_base = dram->phy; 1396 1397 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); 1398 setbits_le32(PHY_REG(phy_base, 0x2), BIT(3)); 1399 setbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); 1400 udelay(1); 1401 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(6)); 1402 } 1403 1404 static void update_ca_prebit(struct dram_info *dram) 1405 { 1406 void __iomem *phy_base = dram->phy; 1407 1408 clrbits_le32(PHY_REG(phy_base, 0x25), BIT(2)); 1409 setbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); 1410 udelay(1); 1411 clrbits_le32(PHY_REG(phy_base, 0x22), BIT(6)); 1412 } 1413 1414 /* 1415 * dir: 0: de-skew = delta_* 1416 * 1: de-skew = reg val - delta_* 1417 * delta_dir: value for differential signal: clk/ 1418 * delta_sig: value for single signal: ca/cmd 1419 */ 1420 static void modify_ca_deskew(struct dram_info *dram, u32 dir, int delta_dif, 1421 int delta_sig, u32 cs, u32 dramtype) 1422 { 1423 void __iomem *phy_base = dram->phy; 1424 u32 i, cs_en, tmp; 1425 u32 dfi_lp_stat = 0; 1426 1427 if (cs == 0) 1428 cs_en = 1; 1429 else if (cs == 2) 1430 cs_en = 2; 1431 else 1432 cs_en = 3; 1433 1434 if ((dramtype == LPDDR4 || dramtype == LPDDR4X) && 1435 ((readl(PHY_REG(phy_base, 0x60)) & BIT(5)) == 0)) { 1436 dfi_lp_stat = 1; 1437 setbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); 1438 } 1439 enter_sr(dram, 1); 1440 1441 for (i = 0; i < 0x20; i++) { 1442 if (dir == DESKEW_MDF_ABS_VAL) 1443 tmp = delta_sig; 1444 else 1445 tmp = readl(PHY_REG(phy_base, 0x150 + i)) + 1446 delta_sig; 1447 writel(tmp, PHY_REG(phy_base, 0x150 + i)); 1448 } 1449 1450 if (dir == DESKEW_MDF_ABS_VAL) 1451 tmp = delta_dif; 1452 else 1453 tmp = readl(PHY_REG(phy_base, 0x150 + 0x17)) - 1454 delta_sig + delta_dif; 1455 writel(tmp, PHY_REG(phy_base, 0x150 + 0x17)); 1456 writel(tmp, PHY_REG(phy_base, 0x150 + 0x18)); 1457 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 1458 writel(tmp, PHY_REG(phy_base, 0x150 + 0x4)); 1459 writel(tmp, PHY_REG(phy_base, 0x150 + 0xa)); 1460 1461 clrbits_le32(PHY_REG(phy_base, 0x10), cs_en << 6); 1462 update_ca_prebit(dram); 1463 } 1464 enter_sr(dram, 0); 1465 1466 if (dfi_lp_stat) 1467 clrbits_le32(PHY_REG(phy_base, 0x60), BIT(5)); 1468 1469 } 1470 1471 static u32 get_min_value(struct dram_info *dram, u32 signal, u32 rank) 1472 { 1473 u32 i, j, offset = 0; 1474 u32 min = 0x3f; 1475 void __iomem *phy_base = dram->phy; 1476 u32 byte_en; 1477 1478 if (signal == SKEW_TX_SIGNAL) 1479 offset = 8; 1480 1481 if (signal == SKEW_CA_SIGNAL) { 1482 for (i = 0; i < 0x20; i++) 1483 min = MIN(min, readl(PHY_REG(phy_base, 0x150 + i))); 1484 } else { 1485 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; 1486 for (j = offset; j < offset + rank * 4; j++) { 1487 if (!((byte_en >> (j % 4)) & 1)) 1488 continue; 1489 for (i = 0; i < 11; i++) 1490 min = MIN(min, 1491 readl(PHY_REG(phy_base, 1492 dqs_dq_skew_adr[j] + 1493 i))); 1494 } 1495 } 1496 1497 return min; 1498 } 1499 1500 static u32 low_power_update(struct dram_info *dram, u32 en) 1501 { 1502 void __iomem *pctl_base = dram->pctl; 1503 u32 lp_stat = 0; 1504 1505 if (en) { 1506 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, en & 0xf); 1507 } else { 1508 lp_stat = readl(pctl_base + DDR_PCTL2_PWRCTL) & 0xf; 1509 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 0xf); 1510 } 1511 1512 return lp_stat; 1513 } 1514 1515 /* 1516 * signal: 1517 * dir: 0: de-skew = delta_* 1518 * 1: de-skew = reg val - delta_* 1519 * delta_dir: value for differential signal: dqs 1520 * delta_sig: value for single signal: dq/dm 1521 */ 1522 static void modify_dq_deskew(struct dram_info *dram, u32 signal, u32 dir, 1523 int delta_dif, int delta_sig, u32 rank) 1524 { 1525 void __iomem *phy_base = dram->phy; 1526 u32 i, j, tmp, offset; 1527 u32 byte_en; 1528 1529 byte_en = readl(PHY_REG(phy_base, 0xf)) & 0xf; 1530 1531 if (signal == SKEW_RX_SIGNAL) 1532 offset = 0; 1533 else 1534 offset = 8; 1535 1536 for (j = offset; j < (offset + rank * 4); j++) { 1537 if (!((byte_en >> (j % 4)) & 1)) 1538 continue; 1539 for (i = 0; i < 0x9; i++) { 1540 if (dir == DESKEW_MDF_ABS_VAL) 1541 tmp = delta_sig; 1542 else 1543 tmp = delta_sig + readl(PHY_REG(phy_base, 1544 dqs_dq_skew_adr[j] + 1545 i)); 1546 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + i)); 1547 } 1548 if (dir == DESKEW_MDF_ABS_VAL) 1549 tmp = delta_dif; 1550 else 1551 tmp = delta_dif + readl(PHY_REG(phy_base, 1552 dqs_dq_skew_adr[j] + 9)); 1553 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 9)); 1554 writel(tmp, PHY_REG(phy_base, dqs_dq_skew_adr[j] + 0xa)); 1555 } 1556 if (signal == SKEW_RX_SIGNAL) 1557 update_dq_rx_prebit(dram); 1558 else 1559 update_dq_tx_prebit(dram); 1560 } 1561 1562 static int data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype) 1563 { 1564 void __iomem *phy_base = dram->phy; 1565 u32 ret; 1566 u32 dis_auto_zq = 0; 1567 u32 odt_val_up, odt_val_dn; 1568 u32 i, j; 1569 1570 odt_val_dn = readl(PHY_REG(phy_base, 0x110)); 1571 odt_val_up = readl(PHY_REG(phy_base, 0x111)); 1572 1573 if (dramtype != LPDDR4 || dramtype != LPDDR4X) { 1574 for (i = 0; i < 4; i++) { 1575 j = 0x110 + i * 0x10; 1576 writel(PHY_DDR4_LPDDR3_RTT_294ohm, 1577 PHY_REG(phy_base, j)); 1578 writel(PHY_DDR4_LPDDR3_RTT_DISABLE, 1579 PHY_REG(phy_base, j + 0x1)); 1580 } 1581 } 1582 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); 1583 /* use normal read mode for data training */ 1584 clrbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); 1585 1586 if (dramtype == DDR4) 1587 setbits_le32(PHY_REG(phy_base, 0xc), BIT(1)); 1588 1589 /* choose training cs */ 1590 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs)); 1591 /* enable gate training */ 1592 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1); 1593 udelay(50); 1594 ret = readl(PHY_REG(phy_base, 0x91)); 1595 /* disable gate training */ 1596 clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0); 1597 clrbits_le32(PHY_REG(phy_base, 2), 0x30); 1598 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); 1599 1600 ret = (ret & 0x2f) ^ (readl(PHY_REG(phy_base, 0xf)) & 0xf); 1601 1602 if (dramtype != LPDDR4 || dramtype != LPDDR4X) { 1603 for (i = 0; i < 4; i++) { 1604 j = 0x110 + i * 0x10; 1605 writel(odt_val_dn, PHY_REG(phy_base, j)); 1606 writel(odt_val_up, PHY_REG(phy_base, j + 0x1)); 1607 } 1608 } 1609 return ret; 1610 } 1611 1612 static int data_training_wl(struct dram_info *dram, u32 cs, u32 dramtype, 1613 u32 rank) 1614 { 1615 void __iomem *pctl_base = dram->pctl; 1616 void __iomem *phy_base = dram->phy; 1617 u32 dis_auto_zq = 0; 1618 u32 tmp; 1619 u32 cur_fsp; 1620 u32 timeout_us = 1000; 1621 1622 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); 1623 1624 clrbits_le32(PHY_REG(phy_base, 0x7a), 0x1); 1625 1626 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; 1627 tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_INIT3) & 1628 0xffff; 1629 writel(tmp & 0xff, PHY_REG(phy_base, 0x3)); 1630 1631 /* disable another cs's output */ 1632 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) 1633 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp | (1 << 12), 1634 dramtype); 1635 if (dramtype == DDR3 || dramtype == DDR4) 1636 writel(0x40 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); 1637 else 1638 writel(0x80 | ((tmp >> 8) & 0x3f), PHY_REG(phy_base, 0x4)); 1639 1640 /* choose cs */ 1641 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), 1642 ((0x2 >> cs) << 6) | (0 << 2)); 1643 /* enable write leveling */ 1644 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), 1645 ((0x2 >> cs) << 6) | (1 << 2)); 1646 1647 while (1) { 1648 if ((readl(PHY_REG(phy_base, 0x92)) & 0xf) == 1649 (readl(PHY_REG(phy_base, 0xf)) & 0xf)) 1650 break; 1651 1652 udelay(1); 1653 if (timeout_us-- == 0) { 1654 printascii("error: write leveling timeout\n"); 1655 while (1) 1656 ; 1657 } 1658 } 1659 1660 /* disable write leveling */ 1661 clrsetbits_le32(PHY_REG(phy_base, 2), (0x3 << 6) | (0x3 << 2), 1662 ((0x2 >> cs) << 6) | (0 << 2)); 1663 clrsetbits_le32(PHY_REG(phy_base, 2), 0x3 << 6, 0 << 6); 1664 1665 /* enable another cs's output */ 1666 if ((dramtype == DDR3 || dramtype == DDR4) && rank == 2) 1667 pctl_write_mr(dram->pctl, (cs + 1) & 1, 1, tmp & ~(1 << 12), 1668 dramtype); 1669 1670 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); 1671 1672 return 0; 1673 } 1674 1675 char pattern[32] = { 1676 0xaa, 0x55, 0xaa, 0x55, 0x55, 0xaa, 0x55, 0xaa, 1677 0x55, 0xaa, 0x55, 0xaa, 0xaa, 0x55, 0xaa, 0x55, 1678 0x55, 0x55, 0xaa, 0xaa, 0xaa, 0xaa, 0x55, 0x55, 1679 0xaa, 0xaa, 0x55, 0x55, 0x55, 0x55, 0xaa, 0xaa 1680 }; 1681 1682 static int data_training_rd(struct dram_info *dram, u32 cs, u32 dramtype, 1683 u32 mhz) 1684 { 1685 void __iomem *pctl_base = dram->pctl; 1686 void __iomem *phy_base = dram->phy; 1687 u32 trefi_1x, trfc_1x; 1688 u32 dis_auto_zq = 0; 1689 u32 timeout_us = 1000; 1690 u32 dqs_default; 1691 u32 cur_fsp; 1692 u32 vref_inner; 1693 u32 i; 1694 struct sdram_head_info_index_v2 *index = 1695 (struct sdram_head_info_index_v2 *)common_info; 1696 struct dq_map_info *map_info; 1697 1698 vref_inner = readl(PHY_REG(phy_base, 0x128)) & 0xff; 1699 if (dramtype == DDR3 && vref_inner == 0x80) { 1700 for (i = 0; i < 4; i++) 1701 writel(vref_inner - 0xa, 1702 PHY_REG(phy_base, 0x118 + i * 0x10)); 1703 1704 /* reg_rx_vref_value_update */ 1705 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1706 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1707 } 1708 1709 map_info = (struct dq_map_info *)((void *)common_info + 1710 index->dq_map_index.offset * 4); 1711 /* only 1cs a time, 0:cs0 1 cs1 */ 1712 if (cs > 1) 1713 return -1; 1714 1715 dqs_default = 0xf; 1716 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); 1717 1718 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; 1719 /* config refresh timing */ 1720 trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 1721 DDR_PCTL2_RFSHTMG) >> 16) & 0xfff) * 32; 1722 trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 1723 DDR_PCTL2_RFSHTMG) & 0x3ff; 1724 /* reg_phy_trefi[7:0] and reg_phy_trefi[13:8] */ 1725 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); 1726 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); 1727 /* reg_phy_trfc */ 1728 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); 1729 /* reg_max_refi_cnt */ 1730 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); 1731 1732 /* choose training cs */ 1733 clrsetbits_le32(PHY_REG(phy_base, 0x71), 0x3 << 6, (0x2 >> cs) << 6); 1734 1735 /* set dq map for ddr4 */ 1736 if (dramtype == DDR4) { 1737 setbits_le32(PHY_REG(phy_base, 0x70), BIT(7)); 1738 for (i = 0; i < 4; i++) { 1739 writel((map_info->ddr4_dq_map[cs * 2] >> 1740 ((i % 4) * 8)) & 0xff, 1741 PHY_REG(phy_base, 0x238 + i)); 1742 writel((map_info->ddr4_dq_map[cs * 2 + 1] >> 1743 ((i % 4) * 8)) & 0xff, 1744 PHY_REG(phy_base, 0x2b8 + i)); 1745 } 1746 } 1747 1748 /* cha_l reg_l_rd_train_dqs_default[5:0] */ 1749 clrsetbits_le32(PHY_REG(phy_base, 0x230), 0x3f, dqs_default); 1750 /* cha_h reg_h_rd_train_dqs_default[5:0] */ 1751 clrsetbits_le32(PHY_REG(phy_base, 0x234), 0x3f, dqs_default); 1752 /* chb_l reg_l_rd_train_dqs_default[5:0] */ 1753 clrsetbits_le32(PHY_REG(phy_base, 0x2b0), 0x3f, dqs_default); 1754 /* chb_h reg_h_rd_train_dqs_default[5:0] */ 1755 clrsetbits_le32(PHY_REG(phy_base, 0x2b4), 0x3f, dqs_default); 1756 1757 /* Choose the read train auto mode */ 1758 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x1); 1759 /* Enable the auto train of the read train */ 1760 clrsetbits_le32(PHY_REG(phy_base, 0x70), 0x3, 0x3); 1761 1762 /* Wait the train done. */ 1763 while (1) { 1764 if ((readl(PHY_REG(phy_base, 0x93)) >> 7) & 0x1) 1765 break; 1766 1767 udelay(1); 1768 if (timeout_us-- == 0) { 1769 printascii("error: read training timeout\n"); 1770 return -1; 1771 } 1772 } 1773 1774 /* Check the read train state */ 1775 if ((readl(PHY_REG(phy_base, 0x240)) & 0x3) || 1776 (readl(PHY_REG(phy_base, 0x2c0)) & 0x3)) { 1777 printascii("error: read training error\n"); 1778 return -1; 1779 } 1780 1781 /* Exit the Read Training by setting */ 1782 clrbits_le32(PHY_REG(phy_base, 0x70), BIT(1)); 1783 1784 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); 1785 1786 if (dramtype == DDR3 && vref_inner == 0x80) { 1787 for (i = 0; i < 4; i++) 1788 writel(vref_inner, 1789 PHY_REG(phy_base, 0x118 + i * 0x10)); 1790 1791 /* reg_rx_vref_value_update */ 1792 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1793 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int data_training_wr(struct dram_info *dram, u32 cs, u32 dramtype, 1800 u32 mhz, u32 dst_fsp) 1801 { 1802 void __iomem *pctl_base = dram->pctl; 1803 void __iomem *phy_base = dram->phy; 1804 u32 trefi_1x, trfc_1x; 1805 u32 dis_auto_zq = 0; 1806 u32 timeout_us = 1000; 1807 u32 cur_fsp; 1808 u32 mr_tmp, cl, cwl, phy_fsp, offset = 0; 1809 1810 if (dramtype == LPDDR3 && mhz <= 400) { 1811 phy_fsp = (readl(PHY_REG(phy_base, 0xc)) >> 0x2) & 0x3; 1812 offset = (phy_fsp == 0) ? 0x5 : 0x387 + (phy_fsp - 1) * 3; 1813 cl = readl(PHY_REG(phy_base, offset)); 1814 cwl = readl(PHY_REG(phy_base, offset + 2)); 1815 1816 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, 0x8); 1817 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, 0x4); 1818 pctl_write_mr(dram->pctl, 3, 2, 0x6, dramtype); 1819 } 1820 1821 dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl); 1822 1823 /* PHY_0x7b[7:0] reg_train_col_addr[7:0] */ 1824 clrsetbits_le32(PHY_REG(phy_base, 0x7b), 0xff, 0x0); 1825 /* PHY_0x7c[4:2] reg_train_ba_addr[2:0] */ 1826 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x7 << 2, 0x0 << 2); 1827 /* PHY_0x7c[1:0] reg_train_col_addr[9:8] */ 1828 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3, 0x0); 1829 /* PHY_0x7d[7:0] reg_train_row_addr[7:0] */ 1830 clrsetbits_le32(PHY_REG(phy_base, 0x7d), 0xff, 0x0); 1831 /* PHY_0x7e[7:0] reg_train_row_addr[15:8] */ 1832 clrsetbits_le32(PHY_REG(phy_base, 0x7e), 0xff, 0x0); 1833 1834 /* PHY_0x71[3] wrtrain_check_data_value_random_gen */ 1835 clrbits_le32(PHY_REG(phy_base, 0x71), BIT(3)); 1836 1837 /* config refresh timing */ 1838 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; 1839 trefi_1x = ((readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 1840 DDR_PCTL2_RFSHTMG) >> 16) & 0xfff) * 32; 1841 trfc_1x = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 1842 DDR_PCTL2_RFSHTMG) & 0x3ff; 1843 /* reg_phy_trefi[7:0] and reg_phy_trefi[13:8] */ 1844 clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xff, trefi_1x & 0xff); 1845 clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x3f, (trefi_1x >> 8) & 0x3f); 1846 /* reg_phy_trfc */ 1847 clrsetbits_le32(PHY_REG(phy_base, 0x57), 0xff, trfc_1x); 1848 /* reg_max_refi_cnt */ 1849 clrsetbits_le32(PHY_REG(phy_base, 0x61), 0xf << 4, 0x8 << 4); 1850 1851 /* choose training cs */ 1852 clrsetbits_le32(PHY_REG(phy_base, 0x7c), 0x3 << 6, (0x2 >> cs) << 6); 1853 1854 /* PHY_0x7a [4] reg_wr_train_dqs_default_bypass */ 1855 /* 0: Use the write-leveling value. */ 1856 /* 1: use reg0x233 0x237 0x2b3 0x2b7 */ 1857 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(4)); 1858 1859 /* PHY_0x7a [0] reg_dq_wr_train_auto */ 1860 setbits_le32(PHY_REG(phy_base, 0x7a), 0x1); 1861 1862 /* PHY_0x7a [1] reg_dq_wr_train_en */ 1863 setbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); 1864 1865 send_a_refresh(dram); 1866 1867 while (1) { 1868 if ((readl(PHY_REG(phy_base, 0x92)) >> 7) & 0x1) 1869 break; 1870 1871 udelay(1); 1872 if (timeout_us-- == 0) { 1873 printascii("error: write training timeout\n"); 1874 while (1) 1875 ; 1876 } 1877 } 1878 1879 /* Check the write train state */ 1880 if ((readl(PHY_REG(phy_base, 0x90)) >> 5) & 0x7) { 1881 printascii("error: write training error\n"); 1882 return -1; 1883 } 1884 1885 /* PHY_0x7a [1] reg_dq_wr_train_en */ 1886 clrbits_le32(PHY_REG(phy_base, 0x7a), BIT(1)); 1887 1888 pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq); 1889 1890 /* save LPDDR4/LPDDR4X write vref to fsp_param for dfs */ 1891 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 1892 fsp_param[dst_fsp].vref_dq[cs] = 1893 ((readl(PHY_REG(phy_base, 0x384)) & 0x3f) + 1894 (readl(PHY_REG(phy_base, 0x385)) & 0x3f)) / 2; 1895 /* add range info */ 1896 fsp_param[dst_fsp].vref_dq[cs] |= 1897 ((readl(PHY_REG(phy_base, 0x7c)) & BIT(5)) << 1); 1898 } 1899 1900 if (dramtype == LPDDR3 && mhz <= 400) { 1901 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); 1902 clrsetbits_le32(PHY_REG(phy_base, offset + 2), 0x1f, cwl); 1903 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 1904 DDR_PCTL2_INIT3); 1905 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, 1906 dramtype); 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int data_training(struct dram_info *dram, u32 cs, 1913 struct rv1126_sdram_params *sdram_params, u32 dst_fsp, 1914 u32 training_flag) 1915 { 1916 u32 ret = 0; 1917 1918 if (training_flag == FULL_TRAINING) 1919 training_flag = READ_GATE_TRAINING | WRITE_LEVELING | 1920 WRITE_TRAINING | READ_TRAINING; 1921 1922 if ((training_flag & WRITE_LEVELING) == WRITE_LEVELING) { 1923 ret = data_training_wl(dram, cs, 1924 sdram_params->base.dramtype, 1925 sdram_params->ch.cap_info.rank); 1926 if (ret != 0) 1927 goto out; 1928 } 1929 1930 if ((training_flag & READ_GATE_TRAINING) == READ_GATE_TRAINING) { 1931 ret = data_training_rg(dram, cs, 1932 sdram_params->base.dramtype); 1933 if (ret != 0) 1934 goto out; 1935 } 1936 1937 if ((training_flag & READ_TRAINING) == READ_TRAINING) { 1938 ret = data_training_rd(dram, cs, 1939 sdram_params->base.dramtype, 1940 sdram_params->base.ddr_freq); 1941 if (ret != 0) 1942 goto out; 1943 } 1944 1945 if ((training_flag & WRITE_TRAINING) == WRITE_TRAINING) { 1946 ret = data_training_wr(dram, cs, 1947 sdram_params->base.dramtype, 1948 sdram_params->base.ddr_freq, dst_fsp); 1949 if (ret != 0) 1950 goto out; 1951 } 1952 1953 out: 1954 return ret; 1955 } 1956 1957 static int get_wrlvl_val(struct dram_info *dram, 1958 struct rv1126_sdram_params *sdram_params) 1959 { 1960 int i, j, clk_skew; 1961 void __iomem *phy_base = dram->phy; 1962 u32 lp_stat; 1963 int ret; 1964 1965 lp_stat = low_power_update(dram, 0); 1966 1967 clk_skew = 0x1f; 1968 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, clk_skew, 3, 1969 sdram_params->base.dramtype); 1970 1971 ret = data_training(dram, 0, sdram_params, 0, WRITE_LEVELING); 1972 if (sdram_params->ch.cap_info.rank == 2) 1973 ret |= data_training(dram, 1, sdram_params, 0, WRITE_LEVELING); 1974 1975 for (j = 0; j < 2; j++) 1976 for (i = 0; i < 4; i++) 1977 wrlvl_result[j][i] = 1978 (readl(PHY_REG(phy_base, wrlvl_result_offset[j][i])) & 0x3f) - 1979 clk_skew; 1980 1981 low_power_update(dram, lp_stat); 1982 1983 return ret; 1984 } 1985 1986 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 1987 static void init_rw_trn_result_struct(struct rw_trn_result *result, 1988 void __iomem *phy_base, u8 cs_num) 1989 { 1990 int i; 1991 1992 result->cs_num = cs_num; 1993 result->byte_en = readb(PHY_REG(dram_info.phy, 0xf)) & 1994 PHY_DQ_WIDTH_MASK; 1995 for (i = 0; i < FSP_NUM; i++) 1996 result->fsp_mhz[i] = 0; 1997 } 1998 1999 static void save_rw_trn_min_max(void __iomem *phy_base, 2000 struct cs_rw_trn_result *rd_result, 2001 struct cs_rw_trn_result *wr_result, 2002 u8 byte_en) 2003 { 2004 u16 phy_ofs; 2005 u8 dqs; 2006 u8 dq; 2007 2008 for (dqs = 0; dqs < BYTE_NUM; dqs++) { 2009 if ((byte_en & BIT(dqs)) == 0) 2010 continue; 2011 2012 /* Channel A or B (low or high 16 bit) */ 2013 phy_ofs = dqs < 2 ? 0x230 : 0x2b0; 2014 /* low or high 8 bit */ 2015 phy_ofs += (dqs & 0x1) == 0 ? 0 : 0x9; 2016 for (dq = 0; dq < 8; dq++) { 2017 rd_result->dqs[dqs].dq_min[dq] = 2018 readb(PHY_REG(phy_base, phy_ofs + 0x15 + dq)); 2019 rd_result->dqs[dqs].dq_max[dq] = 2020 readb(PHY_REG(phy_base, phy_ofs + 0x27 + dq)); 2021 wr_result->dqs[dqs].dq_min[dq] = 2022 readb(PHY_REG(phy_base, phy_ofs + 0x3d + dq)); 2023 wr_result->dqs[dqs].dq_max[dq] = 2024 readb(PHY_REG(phy_base, phy_ofs + 0x4f + dq)); 2025 } 2026 } 2027 } 2028 2029 static void save_rw_trn_deskew(void __iomem *phy_base, 2030 struct fsp_rw_trn_result *result, u8 cs_num, 2031 int min_val, bool rw) 2032 { 2033 u16 phy_ofs; 2034 u8 cs; 2035 u8 dq; 2036 2037 result->min_val = min_val; 2038 2039 for (cs = 0; cs < cs_num; cs++) { 2040 phy_ofs = cs == 0 ? 0x170 : 0x1a0; 2041 phy_ofs += rw == SKEW_RX_SIGNAL ? 0x1 : 0x17; 2042 for (dq = 0; dq < 8; dq++) { 2043 result->cs[cs].dqs[0].dq_deskew[dq] = 2044 readb(PHY_REG(phy_base, phy_ofs + dq)); 2045 result->cs[cs].dqs[1].dq_deskew[dq] = 2046 readb(PHY_REG(phy_base, phy_ofs + 0xb + dq)); 2047 result->cs[cs].dqs[2].dq_deskew[dq] = 2048 readb(PHY_REG(phy_base, phy_ofs + 0x60 + dq)); 2049 result->cs[cs].dqs[3].dq_deskew[dq] = 2050 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + dq)); 2051 } 2052 2053 result->cs[cs].dqs[0].dqs_deskew = 2054 readb(PHY_REG(phy_base, phy_ofs + 0x8)); 2055 result->cs[cs].dqs[1].dqs_deskew = 2056 readb(PHY_REG(phy_base, phy_ofs + 0xb + 0x8)); 2057 result->cs[cs].dqs[2].dqs_deskew = 2058 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0x8)); 2059 result->cs[cs].dqs[3].dqs_deskew = 2060 readb(PHY_REG(phy_base, phy_ofs + 0x60 + 0xb + 0x8)); 2061 } 2062 } 2063 2064 static void save_rw_trn_result_to_ddr(struct rw_trn_result *result) 2065 { 2066 result->flag = DDR_DQ_EYE_FLAG; 2067 memcpy((void *)(RW_TRN_RESULT_ADDR), result, sizeof(*result)); 2068 } 2069 #endif 2070 2071 static int high_freq_training(struct dram_info *dram, 2072 struct rv1126_sdram_params *sdram_params, 2073 u32 fsp) 2074 { 2075 u32 i, j; 2076 void __iomem *phy_base = dram->phy; 2077 u32 dramtype = sdram_params->base.dramtype; 2078 int min_val; 2079 int dqs_skew, clk_skew, ca_skew; 2080 u8 byte_en; 2081 int ret; 2082 2083 byte_en = readl(PHY_REG(phy_base, 0xf)) & PHY_DQ_WIDTH_MASK; 2084 dqs_skew = 0; 2085 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) { 2086 for (i = 0; i < ARRAY_SIZE(wrlvl_result[0]); i++) { 2087 if ((byte_en & BIT(i)) != 0) 2088 dqs_skew += wrlvl_result[j][i]; 2089 } 2090 } 2091 dqs_skew = dqs_skew / 2092 (int)(sdram_params->ch.cap_info.rank * (1 << sdram_params->ch.cap_info.bw)); 2093 2094 clk_skew = 0x20 - dqs_skew; 2095 dqs_skew = 0x20; 2096 2097 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 2098 min_val = 0xff; 2099 for (j = 0; j < sdram_params->ch.cap_info.rank; j++) 2100 for (i = 0; i < ARRAY_SIZE(wrlvl_result[0]); i++) { 2101 if ((byte_en & BIT(i)) != 0) 2102 min_val = MIN(wrlvl_result[j][i], min_val); 2103 } 2104 2105 if (min_val < 0) { 2106 clk_skew = -min_val; 2107 ca_skew = -min_val; 2108 } else { 2109 clk_skew = 0; 2110 ca_skew = 0; 2111 } 2112 } else if (dramtype == LPDDR3) { 2113 ca_skew = clk_skew - 4; 2114 } else { 2115 ca_skew = clk_skew; 2116 } 2117 modify_ca_deskew(dram, DESKEW_MDF_ABS_VAL, clk_skew, ca_skew, 3, 2118 dramtype); 2119 2120 writel(wrlvl_result[0][0] + clk_skew, PHY_REG(phy_base, 0x233)); 2121 writel(wrlvl_result[0][1] + clk_skew, PHY_REG(phy_base, 0x237)); 2122 writel(wrlvl_result[0][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); 2123 writel(wrlvl_result[0][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); 2124 ret = data_training(dram, 0, sdram_params, fsp, READ_GATE_TRAINING | 2125 READ_TRAINING | WRITE_TRAINING); 2126 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 2127 rw_trn_result.fsp_mhz[fsp] = (u16)sdram_params->base.ddr_freq; 2128 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[0], 2129 &rw_trn_result.wr_fsp[fsp].cs[0], 2130 rw_trn_result.byte_en); 2131 #endif 2132 if (sdram_params->ch.cap_info.rank == 2) { 2133 writel(wrlvl_result[1][0] + clk_skew, PHY_REG(phy_base, 0x233)); 2134 writel(wrlvl_result[1][1] + clk_skew, PHY_REG(phy_base, 0x237)); 2135 writel(wrlvl_result[1][2] + clk_skew, PHY_REG(phy_base, 0x2b3)); 2136 writel(wrlvl_result[1][3] + clk_skew, PHY_REG(phy_base, 0x2b7)); 2137 ret |= data_training(dram, 1, sdram_params, fsp, 2138 READ_GATE_TRAINING | READ_TRAINING | 2139 WRITE_TRAINING); 2140 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 2141 save_rw_trn_min_max(phy_base, &rw_trn_result.rd_fsp[fsp].cs[1], 2142 &rw_trn_result.wr_fsp[fsp].cs[1], 2143 rw_trn_result.byte_en); 2144 #endif 2145 } 2146 if (ret) 2147 goto out; 2148 2149 record_dq_prebit(dram); 2150 2151 min_val = get_min_value(dram, SKEW_RX_SIGNAL, 2152 sdram_params->ch.cap_info.rank) * -1; 2153 modify_dq_deskew(dram, SKEW_RX_SIGNAL, DESKEW_MDF_DIFF_VAL, 2154 min_val, min_val, sdram_params->ch.cap_info.rank); 2155 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 2156 save_rw_trn_deskew(phy_base, &rw_trn_result.rd_fsp[fsp], 2157 rw_trn_result.cs_num, (u8)(min_val * (-1)), 2158 SKEW_RX_SIGNAL); 2159 #endif 2160 2161 min_val = MIN(get_min_value(dram, SKEW_TX_SIGNAL, 2162 sdram_params->ch.cap_info.rank), 2163 get_min_value(dram, SKEW_CA_SIGNAL, 2164 sdram_params->ch.cap_info.rank)) * -1; 2165 2166 /* clk = 0, rx all skew -7, tx - min_value */ 2167 modify_ca_deskew(dram, DESKEW_MDF_DIFF_VAL, min_val, min_val, 3, 2168 dramtype); 2169 2170 modify_dq_deskew(dram, SKEW_TX_SIGNAL, DESKEW_MDF_DIFF_VAL, 2171 min_val, min_val, sdram_params->ch.cap_info.rank); 2172 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 2173 save_rw_trn_deskew(phy_base, &rw_trn_result.wr_fsp[fsp], 2174 rw_trn_result.cs_num, (u8)(min_val * (-1)), 2175 SKEW_TX_SIGNAL); 2176 #endif 2177 2178 ret = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING); 2179 if (sdram_params->ch.cap_info.rank == 2) 2180 ret |= data_training(dram, 1, sdram_params, 0, 2181 READ_GATE_TRAINING); 2182 out: 2183 return ret; 2184 } 2185 2186 static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig) 2187 { 2188 writel(ddrconfig, &dram->msch->deviceconf); 2189 clrsetbits_le32(&dram->grf->noc_con0, 0x3 << 0, 0 << 0); 2190 } 2191 2192 static void update_noc_timing(struct dram_info *dram, 2193 struct rv1126_sdram_params *sdram_params) 2194 { 2195 void __iomem *pctl_base = dram->pctl; 2196 u32 bw, bl; 2197 2198 bw = 8 << sdram_params->ch.cap_info.bw; 2199 bl = ((readl(pctl_base + DDR_PCTL2_MSTR) >> 16) & 0xf) * 2; 2200 2201 /* update the noc timing related to data bus width */ 2202 if ((bw / 8 * bl) <= 16) 2203 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 0; 2204 else if ((bw / 8 * bl) == 32) 2205 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 1; 2206 else if ((bw / 8 * bl) == 64) 2207 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 2; 2208 else 2209 sdram_params->ch.noc_timings.ddrmode.b.burstsize = 3; 2210 2211 sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty = 2212 (bl * bw / 8) > 16 ? (bl / 4) : (16 / (bl * bw / 8)) * bl / 4; 2213 2214 if (sdram_params->base.dramtype == LPDDR4 || 2215 sdram_params->base.dramtype == LPDDR4X) { 2216 sdram_params->ch.noc_timings.ddrmode.b.mwrsize = 2217 (bw == 16) ? 0x1 : 0x2; 2218 sdram_params->ch.noc_timings.ddrtimingc0.b.wrtomwr = 2219 3 * sdram_params->ch.noc_timings.ddrtimingc0.b.burstpenalty; 2220 } 2221 2222 writel(sdram_params->ch.noc_timings.ddrtiminga0.d32, 2223 &dram->msch->ddrtiminga0); 2224 writel(sdram_params->ch.noc_timings.ddrtimingb0.d32, 2225 &dram->msch->ddrtimingb0); 2226 writel(sdram_params->ch.noc_timings.ddrtimingc0.d32, 2227 &dram->msch->ddrtimingc0); 2228 writel(sdram_params->ch.noc_timings.devtodev0.d32, 2229 &dram->msch->devtodev0); 2230 writel(sdram_params->ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode); 2231 writel(sdram_params->ch.noc_timings.ddr4timing.d32, 2232 &dram->msch->ddr4timing); 2233 } 2234 2235 static int split_setup(struct dram_info *dram, 2236 struct rv1126_sdram_params *sdram_params) 2237 { 2238 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2239 u32 dramtype = sdram_params->base.dramtype; 2240 u32 split_size, split_mode; 2241 u64 cs_cap[2], cap; 2242 2243 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dramtype); 2244 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dramtype); 2245 /* only support the larger cap is in low 16bit */ 2246 if (cap_info->cs0_high16bit_row < cap_info->cs0_row) { 2247 cap = cs_cap[0] / (1 << (cap_info->cs0_row - 2248 cap_info->cs0_high16bit_row)); 2249 } else if ((cap_info->cs1_high16bit_row < cap_info->cs1_row) && 2250 (cap_info->rank == 2)) { 2251 if (!cap_info->cs1_high16bit_row) 2252 cap = cs_cap[0]; 2253 else 2254 cap = cs_cap[0] + cs_cap[1] / (1 << (cap_info->cs1_row - 2255 cap_info->cs1_high16bit_row)); 2256 } else { 2257 goto out; 2258 } 2259 split_size = (u32)(cap >> 24) & SPLIT_SIZE_MASK; 2260 if (cap_info->bw == 2) 2261 split_mode = SPLIT_MODE_32_L16_VALID; 2262 else 2263 split_mode = SPLIT_MODE_16_L8_VALID; 2264 2265 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, 2266 (SPLIT_MODE_MASK << SPLIT_MODE_OFFSET) | 2267 (SPLIT_BYPASS_MASK << SPLIT_BYPASS_OFFSET) | 2268 (SPLIT_SIZE_MASK << SPLIT_SIZE_OFFSET), 2269 (split_mode << SPLIT_MODE_OFFSET) | 2270 (0x0 << SPLIT_BYPASS_OFFSET) | 2271 (split_size << SPLIT_SIZE_OFFSET)); 2272 2273 rk_clrsetreg(BUS_SGRF_BASE_ADDR + SGRF_SOC_CON2, 2274 MSCH_AXI_BYPASS_ALL_MASK << MSCH_AXI_BYPASS_ALL_SHIFT, 2275 0x0 << MSCH_AXI_BYPASS_ALL_SHIFT); 2276 2277 out: 2278 return 0; 2279 } 2280 2281 static void split_bypass(struct dram_info *dram) 2282 { 2283 if ((readl(&dram->ddrgrf->grf_ddrsplit_con) & 2284 (1 << SPLIT_BYPASS_OFFSET)) != 0) 2285 return; 2286 2287 /* bypass split */ 2288 rk_clrsetreg(&dram->ddrgrf->grf_ddrsplit_con, 2289 (SPLIT_BYPASS_MASK << SPLIT_BYPASS_OFFSET) | 2290 (SPLIT_SIZE_MASK << SPLIT_SIZE_OFFSET), 2291 (0x1 << SPLIT_BYPASS_OFFSET) | 2292 (0x0 << SPLIT_SIZE_OFFSET)); 2293 } 2294 2295 static void dram_all_config(struct dram_info *dram, 2296 struct rv1126_sdram_params *sdram_params) 2297 { 2298 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2299 u32 dram_type = sdram_params->base.dramtype; 2300 void __iomem *pctl_base = dram->pctl; 2301 u32 sys_reg2 = 0; 2302 u32 sys_reg3 = 0; 2303 u64 cs_cap[2]; 2304 u32 cs_pst; 2305 2306 set_ddrconfig(dram, cap_info->ddrconfig); 2307 sdram_org_config(cap_info, &sdram_params->base, &sys_reg2, 2308 &sys_reg3, 0); 2309 writel(sys_reg2, &dram->pmugrf->os_reg[2]); 2310 writel(sys_reg3, &dram->pmugrf->os_reg[3]); 2311 2312 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); 2313 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); 2314 2315 if (cap_info->rank == 2) { 2316 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + 2317 6 + 2; 2318 if (cs_pst > 28) 2319 cs_cap[0] = 1llu << cs_pst; 2320 } 2321 2322 writel(((((cs_cap[1] >> 20) / 64) & 0xff) << 8) | 2323 (((cs_cap[0] >> 20) / 64) & 0xff), 2324 &dram->msch->devicesize); 2325 update_noc_timing(dram, sdram_params); 2326 } 2327 2328 static void enable_low_power(struct dram_info *dram, 2329 struct rv1126_sdram_params *sdram_params) 2330 { 2331 void __iomem *pctl_base = dram->pctl; 2332 u32 grf_lp_con; 2333 2334 writel(0x1f1f0617, &dram->ddrgrf->ddr_grf_con[1]); 2335 2336 if (sdram_params->base.dramtype == DDR4) 2337 grf_lp_con = (0x7 << 16) | (1 << 1); 2338 else if (sdram_params->base.dramtype == DDR3) 2339 grf_lp_con = (0x7 << 16) | (1 << 0); 2340 else 2341 grf_lp_con = (0x7 << 16) | (1 << 2); 2342 2343 /* en lpckdis_en */ 2344 grf_lp_con = grf_lp_con | (0x1 << (9 + 16)) | (0x1 << 9); 2345 writel(grf_lp_con, &dram->ddrgrf->ddr_grf_lp_con); 2346 2347 /* enable sr, pd */ 2348 if (dram->pd_idle == 0) 2349 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); 2350 else 2351 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1)); 2352 if (dram->sr_idle == 0) 2353 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); 2354 else 2355 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); 2356 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); 2357 } 2358 2359 static void ddr_set_atags(struct dram_info *dram, 2360 struct rv1126_sdram_params *sdram_params) 2361 { 2362 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2363 u32 dram_type = sdram_params->base.dramtype; 2364 void __iomem *pctl_base = dram->pctl; 2365 struct tag_serial t_serial; 2366 struct tag_ddr_mem t_ddrmem; 2367 struct tag_soc_info t_socinfo; 2368 u64 cs_cap[2]; 2369 u32 cs_pst = 0; 2370 u32 split, split_size; 2371 u64 reduce_cap = 0; 2372 2373 cs_cap[0] = sdram_get_cs_cap(cap_info, 0, dram_type); 2374 cs_cap[1] = sdram_get_cs_cap(cap_info, 1, dram_type); 2375 2376 memset(&t_serial, 0, sizeof(struct tag_serial)); 2377 2378 t_serial.version = 0; 2379 t_serial.enable = 1; 2380 t_serial.addr = CONFIG_DEBUG_UART_BASE; 2381 t_serial.baudrate = CONFIG_BAUDRATE; 2382 t_serial.m_mode = SERIAL_M_MODE_M0; 2383 t_serial.id = 2; 2384 2385 atags_destroy(); 2386 atags_set_tag(ATAG_SERIAL, &t_serial); 2387 2388 split = readl(&dram->ddrgrf->grf_ddrsplit_con); 2389 memset(&t_ddrmem, 0, sizeof(struct tag_ddr_mem)); 2390 if (cap_info->row_3_4) { 2391 cs_cap[0] = cs_cap[0] * 3 / 4; 2392 cs_cap[1] = cs_cap[1] * 3 / 4; 2393 } else if (!(split & (1 << SPLIT_BYPASS_OFFSET))) { 2394 split_size = (split >> SPLIT_SIZE_OFFSET) & SPLIT_SIZE_MASK; 2395 reduce_cap = (cs_cap[0] + cs_cap[1] - (split_size << 24)) / 2; 2396 } 2397 t_ddrmem.version = 0; 2398 t_ddrmem.bank[0] = CONFIG_SYS_SDRAM_BASE; 2399 if (cs_cap[1]) { 2400 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + 2401 6 + 2; 2402 } 2403 2404 if (cs_cap[1] && cs_pst > 27) { 2405 t_ddrmem.count = 2; 2406 t_ddrmem.bank[1] = 1 << cs_pst; 2407 t_ddrmem.bank[2] = cs_cap[0]; 2408 t_ddrmem.bank[3] = cs_cap[1] - reduce_cap; 2409 } else { 2410 t_ddrmem.count = 1; 2411 t_ddrmem.bank[1] = (u64)cs_cap[0] + (u64)cs_cap[1] - reduce_cap; 2412 } 2413 2414 atags_set_tag(ATAG_DDR_MEM, &t_ddrmem); 2415 2416 memset(&t_socinfo, 0, sizeof(struct tag_soc_info)); 2417 t_socinfo.version = 0; 2418 t_socinfo.name = 0x1126; 2419 } 2420 2421 static void print_ddr_info(struct rv1126_sdram_params *sdram_params) 2422 { 2423 u32 split; 2424 2425 if ((readl(DDR_GRF_BASE_ADDR + DDR_GRF_SPLIT_CON) & 2426 (1 << SPLIT_BYPASS_OFFSET)) != 0) 2427 split = 0; 2428 else 2429 split = readl(DDR_GRF_BASE_ADDR + DDR_GRF_SPLIT_CON) & 2430 SPLIT_SIZE_MASK; 2431 2432 sdram_print_ddr_info(&sdram_params->ch.cap_info, 2433 &sdram_params->base, split); 2434 } 2435 2436 static int modify_ddr34_bw_byte_map(u8 rg_result, struct rv1126_sdram_params *sdram_params) 2437 { 2438 struct sdram_head_info_index_v2 *index = (struct sdram_head_info_index_v2 *)common_info; 2439 struct dq_map_info *map_info = (struct dq_map_info *) 2440 ((void *)common_info + index->dq_map_index.offset * 4); 2441 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2442 u32 dramtype = sdram_params->base.dramtype; 2443 u32 byte_map = 0; 2444 u32 byte = 0; 2445 u32 byte_map_shift; 2446 int i; 2447 2448 if (dramtype == DDR3) 2449 byte_map_shift = 24; 2450 else if (dramtype == DDR4) 2451 byte_map_shift = 0; 2452 else 2453 return -1; 2454 2455 for (i = 0; i < 4; i++) { 2456 if ((rg_result & BIT(i)) == 0) { 2457 byte_map |= byte << (i * 2); 2458 byte++; 2459 } 2460 } 2461 if (byte != 1 && byte != 2 && byte != 4) { 2462 printascii("DTT result is abnormal: "); 2463 printdec(byte); 2464 printascii("byte\n"); 2465 return -1; 2466 } 2467 cap_info->bw = byte / 2; 2468 for (i = 0; i < 4; i++) { 2469 if ((rg_result & BIT(i)) != 0) { 2470 byte_map |= byte << (i * 2); 2471 byte++; 2472 } 2473 } 2474 2475 if ((u8)byte_map != (u8)(map_info->byte_map[0] >> byte_map_shift)) { 2476 clrsetbits_le32(&map_info->byte_map[0], 2477 0xff << byte_map_shift, byte_map << byte_map_shift); 2478 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, dramtype); 2479 return 1; 2480 } 2481 2482 return 0; 2483 } 2484 2485 static int sdram_init_(struct dram_info *dram, 2486 struct rv1126_sdram_params *sdram_params, u32 post_init) 2487 { 2488 void __iomem *pctl_base = dram->pctl; 2489 void __iomem *phy_base = dram->phy; 2490 u32 ddr4_vref; 2491 u32 mr_tmp, tmp; 2492 2493 rkclk_configure_ddr(dram, sdram_params); 2494 2495 rkclk_ddr_reset(dram, 1, 1, 1, 1); 2496 udelay(10); 2497 2498 rkclk_ddr_reset(dram, 1, 1, 1, 0); 2499 phy_cfg(dram, sdram_params); 2500 2501 rkclk_ddr_reset(dram, 1, 1, 0, 0); 2502 phy_pll_set(dram, sdram_params->base.ddr_freq * MHZ, 1); 2503 2504 rkclk_ddr_reset(dram, 1, 0, 0, 0); 2505 pctl_cfg(dram->pctl, &sdram_params->pctl_regs, 2506 dram->sr_idle, dram->pd_idle); 2507 2508 if (sdram_params->ch.cap_info.bw == 2) { 2509 /* 32bit interface use pageclose */ 2510 setbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); 2511 /* pageclose = 1, pageclose_timer = 0 will err in lp4 328MHz */ 2512 clrsetbits_le32(pctl_base + DDR_PCTL2_SCHED1, 0xff, 0x1 << 0); 2513 } else { 2514 clrbits_le32(pctl_base + DDR_PCTL2_SCHED, 1 << 2); 2515 } 2516 2517 #ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT 2518 u32 trefi; 2519 2520 tmp = readl(pctl_base + DDR_PCTL2_RFSHTMG); 2521 trefi = (tmp >> 16) & 0xfff; 2522 writel((tmp & 0xf000ffff) | (trefi / 2) << 16, 2523 pctl_base + DDR_PCTL2_RFSHTMG); 2524 #endif 2525 2526 /* set frequency_mode */ 2527 setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); 2528 /* set target_frequency to Frequency 0 */ 2529 clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, 0); 2530 2531 set_ds_odt(dram, sdram_params, 0); 2532 sdram_params->ch.cap_info.ddrconfig = calculate_ddrconfig(sdram_params); 2533 set_ctl_address_map(dram, sdram_params); 2534 2535 setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4)); 2536 2537 rkclk_ddr_reset(dram, 0, 0, 0, 0); 2538 2539 while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) 2540 continue; 2541 2542 if (sdram_params->base.dramtype == LPDDR3) { 2543 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3); 2544 } else if (sdram_params->base.dramtype == LPDDR4 || 2545 sdram_params->base.dramtype == LPDDR4X) { 2546 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT6); 2547 /* MR11 */ 2548 pctl_write_mr(dram->pctl, 3, 11, 2549 mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, 2550 LPDDR4); 2551 /* MR12 */ 2552 pctl_write_mr(dram->pctl, 3, 12, 2553 mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, 2554 LPDDR4); 2555 2556 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); 2557 /* MR22 */ 2558 pctl_write_mr(dram->pctl, 3, 22, 2559 mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, 2560 LPDDR4); 2561 } 2562 2563 if (sdram_params->base.dramtype == DDR3 && post_init == 0) 2564 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); 2565 tmp = data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) & 0xf; 2566 2567 if (tmp != 0) { 2568 if (post_init != 0) { 2569 printascii("DTT cs0 error\n"); 2570 return -1; 2571 } 2572 if (sdram_params->base.dramtype != DDR3 || tmp == 0xf) 2573 return -1; 2574 } 2575 2576 if (sdram_params->base.dramtype == DDR3 && post_init == 0) { 2577 if (modify_ddr34_bw_byte_map((u8)tmp, sdram_params) != 0) 2578 return -1; 2579 } 2580 2581 if (sdram_params->base.dramtype == LPDDR4) { 2582 mr_tmp = read_mr(dram, 1, 14, LPDDR4); 2583 2584 if (mr_tmp != 0x4d) 2585 return -1; 2586 } 2587 2588 if (sdram_params->base.dramtype == LPDDR4 || 2589 sdram_params->base.dramtype == LPDDR4X) { 2590 mr_tmp = readl(pctl_base + DDR_PCTL2_INIT7); 2591 /* MR14 */ 2592 pctl_write_mr(dram->pctl, 3, 14, 2593 mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, 2594 LPDDR4); 2595 } 2596 if (post_init != 0 && sdram_params->ch.cap_info.rank == 2) { 2597 if (data_training(dram, 1, sdram_params, 0, 2598 READ_GATE_TRAINING) != 0) { 2599 printascii("DTT cs1 error\n"); 2600 return -1; 2601 } 2602 } 2603 2604 if (sdram_params->base.dramtype == DDR4) { 2605 ddr4_vref = readl(PHY_REG(phy_base, 0x105)) * 39; 2606 pctl_write_vrefdq(dram->pctl, 0x3, ddr4_vref, 2607 sdram_params->base.dramtype); 2608 } 2609 2610 dram_all_config(dram, sdram_params); 2611 enable_low_power(dram, sdram_params); 2612 2613 return 0; 2614 } 2615 2616 static u64 dram_detect_cap(struct dram_info *dram, 2617 struct rv1126_sdram_params *sdram_params, 2618 unsigned char channel) 2619 { 2620 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2621 void __iomem *pctl_base = dram->pctl; 2622 void __iomem *phy_base = dram->phy; 2623 u32 mr8; 2624 2625 u32 bktmp; 2626 u32 coltmp; 2627 u32 rowtmp; 2628 u32 cs; 2629 u32 dram_type = sdram_params->base.dramtype; 2630 u32 pwrctl; 2631 u32 i, dq_map; 2632 u32 byte1 = 0, byte0 = 0; 2633 2634 if (dram_type != LPDDR4 && dram_type != LPDDR4X) { 2635 if (dram_type != DDR4) { 2636 if (dram_type == DDR3) 2637 coltmp = 11; 2638 else 2639 coltmp = 12; 2640 bktmp = 3; 2641 if (dram_type == LPDDR2) 2642 rowtmp = 15; 2643 else 2644 rowtmp = 16; 2645 2646 if (sdram_detect_col(cap_info, coltmp) != 0) 2647 goto cap_err; 2648 2649 sdram_detect_bank(cap_info, coltmp, bktmp); 2650 if (dram_type != LPDDR3) 2651 sdram_detect_dbw(cap_info, dram_type); 2652 } else { 2653 coltmp = 10; 2654 bktmp = 4; 2655 rowtmp = 17; 2656 2657 cap_info->col = 10; 2658 cap_info->bk = 2; 2659 sdram_detect_bg(cap_info, coltmp); 2660 } 2661 2662 if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0) 2663 goto cap_err; 2664 2665 sdram_detect_row_3_4(cap_info, coltmp, bktmp); 2666 } else { 2667 cap_info->col = 10; 2668 cap_info->bk = 3; 2669 mr8 = read_mr(dram, 1, 8, dram_type); 2670 cap_info->dbw = ((mr8 >> 6) & 0x3) == 0 ? 1 : 0; 2671 mr8 = (mr8 >> 2) & 0xf; 2672 if (mr8 >= 0 && mr8 <= 6) { 2673 cap_info->cs0_row = 14 + (mr8 + 1) / 2; 2674 } else if (mr8 == 0xc) { 2675 cap_info->cs0_row = 13; 2676 } else { 2677 printascii("Cap ERR: Fail to get cap of LPDDR4/X from MR8\n"); 2678 goto cap_err; 2679 } 2680 if (cap_info->dbw == 0) 2681 cap_info->cs0_row++; 2682 cap_info->row_3_4 = mr8 % 2 == 1 ? 1 : 0; 2683 if (cap_info->cs0_row >= 17) { 2684 printascii("Cap ERR: "); 2685 printascii("RV1126 LPDDR4/X cannot support row >= 17\n"); 2686 goto cap_err; 2687 // cap_info->cs0_row = 16; 2688 // cap_info->row_3_4 = 0; 2689 } 2690 } 2691 2692 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); 2693 writel(0, pctl_base + DDR_PCTL2_PWRCTL); 2694 2695 if (data_training(dram, 1, sdram_params, 0, READ_GATE_TRAINING) == 0) 2696 cs = 1; 2697 else 2698 cs = 0; 2699 cap_info->rank = cs + 1; 2700 2701 setbits_le32(PHY_REG(phy_base, 0xf), 0xf); 2702 2703 if (dram_type != DDR3) { 2704 if ((data_training_rg(dram, 0, dram_type) & 0xf) == 0) { 2705 cap_info->bw = 2; 2706 } else { 2707 dq_map = readl(PHY_REG(phy_base, 0x4f)); 2708 for (i = 0; i < 4; i++) { 2709 if (((dq_map >> (i * 2)) & 0x3) == 0) 2710 byte0 = i; 2711 if (((dq_map >> (i * 2)) & 0x3) == 1) 2712 byte1 = i; 2713 } 2714 clrsetbits_le32(PHY_REG(phy_base, 0xf), PHY_DQ_WIDTH_MASK, 2715 BIT(byte0) | BIT(byte1)); 2716 if (data_training(dram, 0, sdram_params, 0, READ_GATE_TRAINING) == 0) 2717 cap_info->bw = 1; 2718 else 2719 cap_info->bw = 0; 2720 } 2721 } 2722 if (cap_info->bw > 0) 2723 cap_info->dbw = 1; 2724 2725 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); 2726 2727 cap_info->cs0_high16bit_row = cap_info->cs0_row; 2728 if (cs) { 2729 cap_info->cs1_row = cap_info->cs0_row; 2730 cap_info->cs1_high16bit_row = cap_info->cs0_row; 2731 } else { 2732 cap_info->cs1_row = 0; 2733 cap_info->cs1_high16bit_row = 0; 2734 } 2735 2736 if (dram_type == LPDDR3) 2737 sdram_detect_dbw(cap_info, dram_type); 2738 2739 return 0; 2740 cap_err: 2741 return -1; 2742 } 2743 2744 static int dram_detect_cs1_row(struct dram_info *dram, 2745 struct rv1126_sdram_params *sdram_params, 2746 unsigned char channel) 2747 { 2748 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2749 void __iomem *pctl_base = dram->pctl; 2750 u32 ret = 0; 2751 void __iomem *test_addr; 2752 u32 row, bktmp, coltmp, bw; 2753 u64 cs0_cap; 2754 u32 byte_mask; 2755 u32 cs_pst; 2756 u32 cs_add = 0; 2757 u32 max_row; 2758 2759 if (cap_info->rank == 2) { 2760 cs_pst = (readl(pctl_base + DDR_PCTL2_ADDRMAP0) & 0x1f) + 2761 6 + 2; 2762 if (cs_pst < 28) 2763 cs_add = 1; 2764 2765 cs0_cap = 1 << cs_pst; 2766 2767 if (sdram_params->base.dramtype == DDR4) { 2768 if (cap_info->dbw == 0) 2769 bktmp = cap_info->bk + 2; 2770 else 2771 bktmp = cap_info->bk + 1; 2772 } else { 2773 bktmp = cap_info->bk; 2774 } 2775 bw = cap_info->bw; 2776 coltmp = cap_info->col; 2777 2778 if (bw == 2) 2779 byte_mask = 0xFFFF; 2780 else 2781 byte_mask = 0xFF; 2782 2783 max_row = (cs_pst == 31) ? 30 : 31; 2784 2785 max_row = max_row - bktmp - coltmp - bw - cs_add + 1; 2786 2787 row = (cap_info->cs0_row > max_row) ? max_row : 2788 cap_info->cs0_row; 2789 2790 for (; row > 12; row--) { 2791 test_addr = (void __iomem *)(CONFIG_SYS_SDRAM_BASE + 2792 (u32)cs0_cap + 2793 (1ul << (row + bktmp + coltmp + 2794 cs_add + bw - 1ul))); 2795 2796 writel(0, CONFIG_SYS_SDRAM_BASE + (u32)cs0_cap); 2797 writel(PATTERN, test_addr); 2798 2799 if (((readl(test_addr) & byte_mask) == 2800 (PATTERN & byte_mask)) && 2801 ((readl(CONFIG_SYS_SDRAM_BASE + (u32)cs0_cap) & 2802 byte_mask) == 0)) { 2803 ret = row; 2804 break; 2805 } 2806 } 2807 } 2808 2809 return ret; 2810 } 2811 2812 /* return: 0 = success, other = fail */ 2813 static int sdram_init_detect(struct dram_info *dram, 2814 struct rv1126_sdram_params *sdram_params) 2815 { 2816 struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info; 2817 u32 ret; 2818 u32 sys_reg = 0; 2819 u32 sys_reg3 = 0; 2820 2821 if (sdram_init_(dram, sdram_params, 0)) { 2822 if (sdram_params->base.dramtype == DDR3) { 2823 if (sdram_init_(dram, sdram_params, 0)) 2824 return -1; 2825 } else { 2826 return -1; 2827 } 2828 } 2829 2830 if (sdram_params->base.dramtype == DDR3) { 2831 writel(PATTERN, CONFIG_SYS_SDRAM_BASE); 2832 if (readl(CONFIG_SYS_SDRAM_BASE) != PATTERN) 2833 return -1; 2834 } 2835 2836 split_bypass(dram); 2837 if (dram_detect_cap(dram, sdram_params, 0) != 0) 2838 return -1; 2839 2840 pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info, 2841 sdram_params->base.dramtype); 2842 ret = sdram_init_(dram, sdram_params, 1); 2843 if (ret != 0) 2844 goto out; 2845 2846 cap_info->cs1_row = 2847 dram_detect_cs1_row(dram, sdram_params, 0); 2848 if (cap_info->cs1_row) { 2849 sys_reg = readl(&dram->pmugrf->os_reg[2]); 2850 sys_reg3 = readl(&dram->pmugrf->os_reg[3]); 2851 SYS_REG_ENC_CS1_ROW(cap_info->cs1_row, 2852 sys_reg, sys_reg3, 0); 2853 writel(sys_reg, &dram->pmugrf->os_reg[2]); 2854 writel(sys_reg3, &dram->pmugrf->os_reg[3]); 2855 } 2856 2857 sdram_detect_high_row(cap_info, sdram_params->base.dramtype); 2858 split_setup(dram, sdram_params); 2859 out: 2860 return ret; 2861 } 2862 2863 struct rv1126_sdram_params *get_default_sdram_config(u32 freq_mhz) 2864 { 2865 u32 i; 2866 u32 offset = 0; 2867 struct ddr2_3_4_lp2_3_info *ddr_info; 2868 2869 if (!freq_mhz) { 2870 ddr_info = get_ddr_drv_odt_info(sdram_configs[0].base.dramtype); 2871 if (ddr_info) 2872 freq_mhz = 2873 (ddr_info->ddr_freq0_1 >> DDR_FREQ_F0_SHIFT) & 2874 DDR_FREQ_MASK; 2875 else 2876 freq_mhz = 0; 2877 } 2878 2879 for (i = 0; i < ARRAY_SIZE(sdram_configs); i++) { 2880 if (sdram_configs[i].base.ddr_freq == 0 || 2881 freq_mhz < sdram_configs[i].base.ddr_freq) 2882 break; 2883 } 2884 offset = i == 0 ? 0 : i - 1; 2885 2886 return &sdram_configs[offset]; 2887 } 2888 2889 static const u16 pctl_need_update_reg[] = { 2890 DDR_PCTL2_RFSHTMG, 2891 DDR_PCTL2_INIT3, 2892 DDR_PCTL2_INIT4, 2893 DDR_PCTL2_INIT6, 2894 DDR_PCTL2_INIT7, 2895 DDR_PCTL2_DRAMTMG0, 2896 DDR_PCTL2_DRAMTMG1, 2897 DDR_PCTL2_DRAMTMG2, 2898 DDR_PCTL2_DRAMTMG3, 2899 DDR_PCTL2_DRAMTMG4, 2900 DDR_PCTL2_DRAMTMG5, 2901 DDR_PCTL2_DRAMTMG6, 2902 DDR_PCTL2_DRAMTMG7, 2903 DDR_PCTL2_DRAMTMG8, 2904 DDR_PCTL2_DRAMTMG9, 2905 DDR_PCTL2_DRAMTMG12, 2906 DDR_PCTL2_DRAMTMG13, 2907 DDR_PCTL2_DRAMTMG14, 2908 DDR_PCTL2_ZQCTL0, 2909 DDR_PCTL2_DFITMG0, 2910 DDR_PCTL2_ODTCFG 2911 }; 2912 2913 static const u16 phy_need_update_reg[] = { 2914 0x14, 2915 0x18, 2916 0x1c 2917 }; 2918 2919 static void pre_set_rate(struct dram_info *dram, 2920 struct rv1126_sdram_params *sdram_params, 2921 u32 dst_fsp, u32 dst_fsp_lp4) 2922 { 2923 u32 i, j, find; 2924 void __iomem *pctl_base = dram->pctl; 2925 void __iomem *phy_base = dram->phy; 2926 u32 phy_offset; 2927 u32 mr_tmp; 2928 u32 dramtype = sdram_params->base.dramtype; 2929 2930 sw_set_req(dram); 2931 /* pctl timing update */ 2932 for (i = 0, find = 0; i < ARRAY_SIZE(pctl_need_update_reg); i++) { 2933 for (j = find; sdram_params->pctl_regs.pctl[j][0] != 0xFFFFFFFF; 2934 j++) { 2935 if (sdram_params->pctl_regs.pctl[j][0] == 2936 pctl_need_update_reg[i]) { 2937 writel(sdram_params->pctl_regs.pctl[j][1], 2938 pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 2939 pctl_need_update_reg[i]); 2940 find = j; 2941 break; 2942 } 2943 } 2944 } 2945 2946 #ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT 2947 u32 tmp, trefi; 2948 2949 tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); 2950 trefi = (tmp >> 16) & 0xfff; 2951 writel((tmp & 0xf000ffff) | (trefi / 2) << 16, 2952 pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_RFSHTMG); 2953 #endif 2954 2955 sw_set_ack(dram); 2956 2957 /* phy timing update */ 2958 if (dst_fsp == 0) 2959 phy_offset = 0; 2960 else 2961 phy_offset = PHY_REG(0, 0x387 - 5 + (dst_fsp - 1) * 3); 2962 /* cl cwl al update */ 2963 for (i = 0, find = 0; i < ARRAY_SIZE(phy_need_update_reg); i++) { 2964 for (j = find; sdram_params->phy_regs.phy[j][0] != 0xFFFFFFFF; 2965 j++) { 2966 if (sdram_params->phy_regs.phy[j][0] == 2967 phy_need_update_reg[i]) { 2968 writel(sdram_params->phy_regs.phy[j][1], 2969 phy_base + phy_offset + 2970 phy_need_update_reg[i]); 2971 find = j; 2972 break; 2973 } 2974 } 2975 } 2976 2977 set_ds_odt(dram, sdram_params, dst_fsp); 2978 if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 2979 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 2980 DDR_PCTL2_INIT4); 2981 /* MR13 */ 2982 pctl_write_mr(dram->pctl, 3, 13, 2983 ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & 2984 PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | 2985 ((0x2 << 6) >> dst_fsp_lp4), dramtype); 2986 writel(((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & 2987 PCTL2_MR_MASK) & (~(BIT(7) | BIT(6)))) | 2988 ((0x2 << 6) >> dst_fsp_lp4), 2989 PHY_REG(phy_base, 0x1b)); 2990 /* MR3 */ 2991 pctl_write_mr(dram->pctl, 3, 3, 2992 mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & 2993 PCTL2_MR_MASK, 2994 dramtype); 2995 writel(mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT & PCTL2_MR_MASK, 2996 PHY_REG(phy_base, 0x19)); 2997 2998 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 2999 DDR_PCTL2_INIT3); 3000 /* MR1 */ 3001 pctl_write_mr(dram->pctl, 3, 1, 3002 mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & 3003 PCTL2_MR_MASK, 3004 dramtype); 3005 writel(mr_tmp >> PCTL2_LPDDR234_MR1_SHIFT & PCTL2_MR_MASK, 3006 PHY_REG(phy_base, 0x17)); 3007 /* MR2 */ 3008 pctl_write_mr(dram->pctl, 3, 2, mr_tmp & PCTL2_MR_MASK, 3009 dramtype); 3010 writel(mr_tmp & PCTL2_MR_MASK, 3011 PHY_REG(phy_base, 0x18)); 3012 3013 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3014 DDR_PCTL2_INIT6); 3015 /* MR11 */ 3016 pctl_write_mr(dram->pctl, 3, 11, 3017 mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, 3018 dramtype); 3019 writel(mr_tmp >> PCTL2_LPDDR4_MR11_SHIFT & PCTL2_MR_MASK, 3020 PHY_REG(phy_base, 0x1a)); 3021 /* MR12 */ 3022 pctl_write_mr(dram->pctl, 3, 12, 3023 mr_tmp >> PCTL2_LPDDR4_MR12_SHIFT & PCTL2_MR_MASK, 3024 dramtype); 3025 3026 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3027 DDR_PCTL2_INIT7); 3028 /* MR22 */ 3029 pctl_write_mr(dram->pctl, 3, 22, 3030 mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, 3031 dramtype); 3032 writel(mr_tmp >> PCTL2_LPDDR4_MR22_SHIFT & PCTL2_MR_MASK, 3033 PHY_REG(phy_base, 0x1d)); 3034 /* MR14 */ 3035 pctl_write_mr(dram->pctl, 3, 14, 3036 mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, 3037 dramtype); 3038 writel(mr_tmp >> PCTL2_LPDDR4_MR14_SHIFT & PCTL2_MR_MASK, 3039 PHY_REG(phy_base, 0x1c)); 3040 } 3041 3042 update_noc_timing(dram, sdram_params); 3043 } 3044 3045 static void save_fsp_param(struct dram_info *dram, u32 dst_fsp, 3046 struct rv1126_sdram_params *sdram_params) 3047 { 3048 void __iomem *pctl_base = dram->pctl; 3049 void __iomem *phy_base = dram->phy; 3050 struct rv1126_fsp_param *p_fsp_param = &fsp_param[dst_fsp]; 3051 u32 temp, temp1; 3052 struct ddr2_3_4_lp2_3_info *ddr_info; 3053 3054 ddr_info = get_ddr_drv_odt_info(sdram_params->base.dramtype); 3055 3056 p_fsp_param->freq_mhz = sdram_params->base.ddr_freq; 3057 3058 if (sdram_params->base.dramtype == LPDDR4 || 3059 sdram_params->base.dramtype == LPDDR4X) { 3060 p_fsp_param->rd_odt_up_en = 0; 3061 p_fsp_param->rd_odt_down_en = 1; 3062 } else { 3063 p_fsp_param->rd_odt_up_en = 3064 ODT_INFO_PULLUP_EN(ddr_info->odt_info); 3065 p_fsp_param->rd_odt_down_en = 3066 ODT_INFO_PULLDOWN_EN(ddr_info->odt_info); 3067 } 3068 3069 if (p_fsp_param->rd_odt_up_en) 3070 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x111)); 3071 else if (p_fsp_param->rd_odt_down_en) 3072 p_fsp_param->rd_odt = readl(PHY_REG(phy_base, 0x110)); 3073 else 3074 p_fsp_param->rd_odt = 0; 3075 p_fsp_param->wr_dq_drv = readl(PHY_REG(phy_base, 0x112)); 3076 p_fsp_param->wr_ca_drv = readl(PHY_REG(phy_base, 0x100)); 3077 p_fsp_param->wr_ckcs_drv = readl(PHY_REG(phy_base, 0x102)); 3078 p_fsp_param->vref_inner = readl(PHY_REG(phy_base, 0x128)); 3079 p_fsp_param->vref_out = readl(PHY_REG(phy_base, 0x105)); 3080 3081 if (sdram_params->base.dramtype == DDR3) { 3082 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3083 DDR_PCTL2_INIT3); 3084 temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; 3085 p_fsp_param->ds_pdds = temp & DDR3_DS_MASK; 3086 p_fsp_param->dq_odt = temp & DDR3_RTT_NOM_MASK; 3087 p_fsp_param->ca_odt = p_fsp_param->dq_odt; 3088 } else if (sdram_params->base.dramtype == DDR4) { 3089 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3090 DDR_PCTL2_INIT3); 3091 temp = (temp >> PCTL2_DDR34_MR1_SHIFT) & PCTL2_MR_MASK; 3092 p_fsp_param->ds_pdds = temp & DDR4_DS_MASK; 3093 p_fsp_param->dq_odt = temp & DDR4_RTT_NOM_MASK; 3094 p_fsp_param->ca_odt = p_fsp_param->dq_odt; 3095 } else if (sdram_params->base.dramtype == LPDDR3) { 3096 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3097 DDR_PCTL2_INIT4); 3098 temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; 3099 p_fsp_param->ds_pdds = temp & 0xf; 3100 3101 p_fsp_param->dq_odt = lp3_odt_value; 3102 p_fsp_param->ca_odt = p_fsp_param->dq_odt; 3103 } else if (sdram_params->base.dramtype == LPDDR4 || 3104 sdram_params->base.dramtype == LPDDR4X) { 3105 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3106 DDR_PCTL2_INIT4); 3107 temp = (temp >> PCTL2_LPDDR234_MR3_SHIFT) & PCTL2_MR_MASK; 3108 p_fsp_param->ds_pdds = temp & LPDDR4_PDDS_MASK; 3109 3110 temp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3111 DDR_PCTL2_INIT6); 3112 temp = (temp >> PCTL2_LPDDR4_MR11_SHIFT) & PCTL2_MR_MASK; 3113 p_fsp_param->dq_odt = temp & LPDDR4_DQODT_MASK; 3114 p_fsp_param->ca_odt = temp & LPDDR4_CAODT_MASK; 3115 3116 temp = MAX(readl(PHY_REG(phy_base, 0x3ae)), 3117 readl(PHY_REG(phy_base, 0x3ce))); 3118 temp1 = MIN(readl(PHY_REG(phy_base, 0x3be)), 3119 readl(PHY_REG(phy_base, 0x3de))); 3120 p_fsp_param->vref_ca[0] = (temp + temp1) / 2; 3121 temp = MAX(readl(PHY_REG(phy_base, 0x3af)), 3122 readl(PHY_REG(phy_base, 0x3cf))); 3123 temp1 = MIN(readl(PHY_REG(phy_base, 0x3bf)), 3124 readl(PHY_REG(phy_base, 0x3df))); 3125 p_fsp_param->vref_ca[1] = (temp + temp1) / 2; 3126 p_fsp_param->vref_ca[0] |= 3127 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); 3128 p_fsp_param->vref_ca[1] |= 3129 (readl(PHY_REG(phy_base, 0x1e)) & BIT(6)); 3130 3131 p_fsp_param->lp4_drv_pd_en = (readl(PHY_REG(phy_base, 0x114)) >> 3132 3) & 0x1; 3133 } 3134 3135 p_fsp_param->noc_timings.ddrtiminga0 = 3136 sdram_params->ch.noc_timings.ddrtiminga0; 3137 p_fsp_param->noc_timings.ddrtimingb0 = 3138 sdram_params->ch.noc_timings.ddrtimingb0; 3139 p_fsp_param->noc_timings.ddrtimingc0 = 3140 sdram_params->ch.noc_timings.ddrtimingc0; 3141 p_fsp_param->noc_timings.devtodev0 = 3142 sdram_params->ch.noc_timings.devtodev0; 3143 p_fsp_param->noc_timings.ddrmode = 3144 sdram_params->ch.noc_timings.ddrmode; 3145 p_fsp_param->noc_timings.ddr4timing = 3146 sdram_params->ch.noc_timings.ddr4timing; 3147 p_fsp_param->noc_timings.agingx0 = 3148 sdram_params->ch.noc_timings.agingx0; 3149 p_fsp_param->noc_timings.aging0 = 3150 sdram_params->ch.noc_timings.aging0; 3151 p_fsp_param->noc_timings.aging1 = 3152 sdram_params->ch.noc_timings.aging1; 3153 p_fsp_param->noc_timings.aging2 = 3154 sdram_params->ch.noc_timings.aging2; 3155 p_fsp_param->noc_timings.aging3 = 3156 sdram_params->ch.noc_timings.aging3; 3157 3158 p_fsp_param->flag = FSP_FLAG; 3159 } 3160 3161 #ifndef CONFIG_SPL_KERNEL_BOOT 3162 static void copy_fsp_param_to_ddr(void) 3163 { 3164 memcpy((void *)FSP_PARAM_STORE_ADDR, (void *)&fsp_param, 3165 sizeof(fsp_param)); 3166 } 3167 #endif 3168 3169 static void pctl_modify_trfc(struct ddr_pctl_regs *pctl_regs, 3170 struct sdram_cap_info *cap_info, u32 dram_type, 3171 u32 freq) 3172 { 3173 u64 cs0_cap; 3174 u32 die_cap; 3175 u32 trfc_ns, trfc4_ns; 3176 u32 trfc, txsnr; 3177 u32 txs_abort_fast = 0; 3178 u32 tmp; 3179 3180 cs0_cap = sdram_get_cs_cap(cap_info, 0, dram_type); 3181 die_cap = (u32)(cs0_cap >> (20 + (cap_info->bw - cap_info->dbw))); 3182 3183 switch (dram_type) { 3184 case DDR3: 3185 if (die_cap <= DIE_CAP_512MBIT) 3186 trfc_ns = 90; 3187 else if (die_cap <= DIE_CAP_1GBIT) 3188 trfc_ns = 110; 3189 else if (die_cap <= DIE_CAP_2GBIT) 3190 trfc_ns = 160; 3191 else if (die_cap <= DIE_CAP_4GBIT) 3192 trfc_ns = 260; 3193 else 3194 trfc_ns = 350; 3195 txsnr = MAX(5, ((trfc_ns + 10) * freq + 999) / 1000); 3196 break; 3197 3198 case DDR4: 3199 if (die_cap <= DIE_CAP_2GBIT) { 3200 trfc_ns = 160; 3201 trfc4_ns = 90; 3202 } else if (die_cap <= DIE_CAP_4GBIT) { 3203 trfc_ns = 260; 3204 trfc4_ns = 110; 3205 } else if (die_cap <= DIE_CAP_8GBIT) { 3206 trfc_ns = 350; 3207 trfc4_ns = 160; 3208 } else { 3209 trfc_ns = 550; 3210 trfc4_ns = 260; 3211 } 3212 txsnr = ((trfc_ns + 10) * freq + 999) / 1000; 3213 txs_abort_fast = ((trfc4_ns + 10) * freq + 999) / 1000; 3214 break; 3215 3216 case LPDDR3: 3217 if (die_cap <= DIE_CAP_4GBIT) 3218 trfc_ns = 130; 3219 else 3220 trfc_ns = 210; 3221 txsnr = MAX(2, ((trfc_ns + 10) * freq + 999) / 1000); 3222 break; 3223 3224 case LPDDR4: 3225 case LPDDR4X: 3226 if (die_cap <= DIE_CAP_2GBIT) 3227 trfc_ns = 130; 3228 else if (die_cap <= DIE_CAP_4GBIT) 3229 trfc_ns = 180; 3230 else if (die_cap <= DIE_CAP_8GBIT) 3231 trfc_ns = 280; 3232 else 3233 trfc_ns = 380; 3234 txsnr = MAX(2, ((trfc_ns + 10) * freq + 999) / 1000); 3235 break; 3236 3237 default: 3238 return; 3239 } 3240 trfc = (trfc_ns * freq + 999) / 1000; 3241 3242 for (int i = 0; pctl_regs->pctl[i][0] != 0xffffffff; i++) { 3243 switch (pctl_regs->pctl[i][0]) { 3244 case DDR_PCTL2_RFSHTMG: 3245 tmp = pctl_regs->pctl[i][1]; 3246 /* t_rfc_min */ 3247 tmp &= ~((u32)0x3ff); 3248 tmp |= ((trfc + 1) / 2) & 0x3ff; 3249 pctl_regs->pctl[i][1] = tmp; 3250 break; 3251 3252 case DDR_PCTL2_DRAMTMG8: 3253 if (dram_type == DDR3 || dram_type == DDR4) { 3254 tmp = pctl_regs->pctl[i][1]; 3255 /* t_xs_x32 */ 3256 tmp &= ~((u32)0x7f); 3257 tmp |= ((txsnr + 63) / 64 + 1) & 0x7f; 3258 3259 if (dram_type == DDR4) { 3260 /* t_xs_abort_x32 */ 3261 tmp &= ~((u32)(0x7f << 16)); 3262 tmp |= (((txs_abort_fast + 63) / 64 + 1) & 0x7f) << 16; 3263 /* t_xs_fast_x32 */ 3264 tmp &= ~((u32)(0x7f << 24)); 3265 tmp |= (((txs_abort_fast + 63) / 64 + 1) & 0x7f) << 24; 3266 } 3267 3268 pctl_regs->pctl[i][1] = tmp; 3269 } 3270 break; 3271 3272 case DDR_PCTL2_DRAMTMG14: 3273 if (dram_type == LPDDR3 || 3274 dram_type == LPDDR4 || dram_type == LPDDR4X) { 3275 tmp = pctl_regs->pctl[i][1]; 3276 /* t_xsr */ 3277 tmp &= ~((u32)0xfff); 3278 tmp |= ((txsnr + 1) / 2) & 0xfff; 3279 pctl_regs->pctl[i][1] = tmp; 3280 } 3281 break; 3282 3283 default: 3284 break; 3285 } 3286 } 3287 } 3288 3289 void ddr_set_rate(struct dram_info *dram, 3290 struct rv1126_sdram_params *sdram_params, 3291 u32 freq, u32 cur_freq, u32 dst_fsp, 3292 u32 dst_fsp_lp4, u32 training_en) 3293 { 3294 u32 dest_dll_off, cur_init3, dst_init3, cur_fsp, cur_dll_off; 3295 u32 mr_tmp; 3296 u32 lp_stat; 3297 u32 dramtype = sdram_params->base.dramtype; 3298 struct rv1126_sdram_params *sdram_params_new; 3299 void __iomem *pctl_base = dram->pctl; 3300 void __iomem *phy_base = dram->phy; 3301 3302 lp_stat = low_power_update(dram, 0); 3303 sdram_params_new = get_default_sdram_config(freq); 3304 sdram_params_new->ch.cap_info.rank = sdram_params->ch.cap_info.rank; 3305 sdram_params_new->ch.cap_info.bw = sdram_params->ch.cap_info.bw; 3306 3307 pctl_modify_trfc(&sdram_params_new->pctl_regs, 3308 &sdram_params->ch.cap_info, dramtype, freq); 3309 pre_set_rate(dram, sdram_params_new, dst_fsp, dst_fsp_lp4); 3310 3311 while ((readl(pctl_base + DDR_PCTL2_STAT) & 3312 PCTL2_OPERATING_MODE_MASK) == 3313 PCTL2_OPERATING_MODE_SR) 3314 continue; 3315 3316 dest_dll_off = 0; 3317 dst_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3318 DDR_PCTL2_INIT3); 3319 if ((dramtype == DDR3 && (dst_init3 & 1)) || 3320 (dramtype == DDR4 && !(dst_init3 & 1))) 3321 dest_dll_off = 1; 3322 3323 cur_fsp = readl(pctl_base + DDR_PCTL2_MSTR2) & 0x3; 3324 cur_init3 = readl(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + 3325 DDR_PCTL2_INIT3); 3326 cur_init3 &= PCTL2_MR_MASK; 3327 cur_dll_off = 1; 3328 if ((dramtype == DDR3 && !(cur_init3 & 1)) || 3329 (dramtype == DDR4 && (cur_init3 & 1))) 3330 cur_dll_off = 0; 3331 3332 if (!cur_dll_off) { 3333 if (dramtype == DDR3) 3334 cur_init3 |= 1; 3335 else 3336 cur_init3 &= ~1; 3337 pctl_write_mr(dram->pctl, 2, 1, cur_init3, dramtype); 3338 } 3339 3340 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 3341 PCTL2_DIS_AUTO_REFRESH); 3342 update_refresh_reg(dram); 3343 3344 enter_sr(dram, 1); 3345 3346 writel(PMUGRF_CON_DDRPHY_BUFFEREN_MASK | 3347 PMUGRF_CON_DDRPHY_BUFFEREN_EN, 3348 &dram->pmugrf->soc_con[0]); 3349 sw_set_req(dram); 3350 clrbits_le32(pctl_base + DDR_PCTL2_DFIMISC, 3351 PCTL2_DFI_INIT_COMPLETE_EN); 3352 sw_set_ack(dram); 3353 3354 sw_set_req(dram); 3355 if ((dramtype == DDR3 || dramtype == DDR4) && dest_dll_off) 3356 setbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); 3357 else 3358 clrbits_le32(pctl_base + DDR_PCTL2_MSTR, PCTL2_DLL_OFF_MODE); 3359 3360 setbits_le32(pctl_base + UMCTL2_REGS_FREQ(cur_fsp) + DDR_PCTL2_ZQCTL0, 3361 PCTL2_DIS_SRX_ZQCL); 3362 setbits_le32(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_ZQCTL0, 3363 PCTL2_DIS_SRX_ZQCL); 3364 sw_set_ack(dram); 3365 3366 writel(DDR_MSCH_EN_MASK | (0x1 << DDR_MSCH_EN_SHIFT), 3367 &dram->cru->clkgate_con[21]); 3368 writel(CLK_DDR_UPCTL_EN_MASK | ACLK_DDR_UPCTL_EN_MASK | 3369 (0x1 << CLK_DDR_UPCTL_EN_SHIFT) | 3370 (0x1 << ACLK_DDR_UPCTL_EN_SHIFT), 3371 BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12); 3372 3373 clrbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); 3374 rkclk_set_dpll(dram, freq * MHz / 2); 3375 phy_pll_set(dram, freq * MHz, 0); 3376 phy_pll_set(dram, freq * MHz, 1); 3377 setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET | DIGITAL_DERESET); 3378 3379 writel(PMUGRF_CON_DDRPHY_BUFFEREN_MASK | 3380 PMUGRF_CON_DDRPHY_BUFFEREN_DIS, 3381 &dram->pmugrf->soc_con[0]); 3382 writel(DDR_MSCH_EN_MASK | (0x0 << DDR_MSCH_EN_SHIFT), 3383 &dram->cru->clkgate_con[21]); 3384 writel(CLK_DDR_UPCTL_EN_MASK | ACLK_DDR_UPCTL_EN_MASK | 3385 (0x0 << CLK_DDR_UPCTL_EN_SHIFT) | 3386 (0x0 << ACLK_DDR_UPCTL_EN_SHIFT), 3387 BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12); 3388 while ((readl(pctl_base + DDR_PCTL2_DFISTAT) & 3389 PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) 3390 continue; 3391 3392 sw_set_req(dram); 3393 setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29); 3394 clrsetbits_le32(pctl_base + DDR_PCTL2_MSTR2, 0x3, dst_fsp); 3395 sw_set_ack(dram); 3396 update_refresh_reg(dram); 3397 clrsetbits_le32(PHY_REG(phy_base, 0xc), 0x3 << 2, dst_fsp << 2); 3398 3399 enter_sr(dram, 0); 3400 3401 setbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 3402 clrbits_le32(PHY_REG(phy_base, 0x71), 1 << 5); 3403 3404 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + DDR_PCTL2_INIT4); 3405 if (dramtype == LPDDR3) { 3406 pctl_write_mr(dram->pctl, 3, 1, 3407 (dst_init3 >> PCTL2_LPDDR234_MR1_SHIFT) & 3408 PCTL2_MR_MASK, 3409 dramtype); 3410 pctl_write_mr(dram->pctl, 3, 2, dst_init3 & PCTL2_MR_MASK, 3411 dramtype); 3412 pctl_write_mr(dram->pctl, 3, 3, 3413 (mr_tmp >> PCTL2_LPDDR234_MR3_SHIFT) & 3414 PCTL2_MR_MASK, 3415 dramtype); 3416 pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, dramtype); 3417 } else if ((dramtype == DDR3) || (dramtype == DDR4)) { 3418 pctl_write_mr(dram->pctl, 3, 1, dst_init3 & PCTL2_MR_MASK, 3419 dramtype); 3420 if (!dest_dll_off) { 3421 pctl_write_mr(dram->pctl, 3, 0, 3422 ((dst_init3 >> PCTL2_DDR34_MR0_SHIFT) & 3423 PCTL2_MR_MASK) | DDR3_DLL_RESET, 3424 dramtype); 3425 udelay(2); 3426 } 3427 pctl_write_mr(dram->pctl, 3, 0, 3428 (dst_init3 >> PCTL2_DDR34_MR0_SHIFT & 3429 PCTL2_MR_MASK) & (~DDR3_DLL_RESET), 3430 dramtype); 3431 pctl_write_mr(dram->pctl, 3, 2, 3432 ((mr_tmp >> PCTL2_DDR34_MR2_SHIFT) & 3433 PCTL2_MR_MASK), dramtype); 3434 if (dramtype == DDR4) { 3435 pctl_write_mr(dram->pctl, 3, 3, mr_tmp & PCTL2_MR_MASK, 3436 dramtype); 3437 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3438 DDR_PCTL2_INIT6); 3439 pctl_write_mr(dram->pctl, 3, 4, 3440 (mr_tmp >> PCTL2_DDR4_MR4_SHIFT) & 3441 PCTL2_MR_MASK, 3442 dramtype); 3443 pctl_write_mr(dram->pctl, 3, 5, 3444 mr_tmp >> PCTL2_DDR4_MR5_SHIFT & 3445 PCTL2_MR_MASK, 3446 dramtype); 3447 3448 mr_tmp = readl(pctl_base + UMCTL2_REGS_FREQ(dst_fsp) + 3449 DDR_PCTL2_INIT7); 3450 pctl_write_mr(dram->pctl, 3, 6, 3451 mr_tmp >> PCTL2_DDR4_MR6_SHIFT & 3452 PCTL2_MR_MASK, 3453 dramtype); 3454 } 3455 } else if (dramtype == LPDDR4 || dramtype == LPDDR4X) { 3456 pctl_write_mr(dram->pctl, 3, 13, 3457 ((mr_tmp >> PCTL2_LPDDR4_MR13_SHIFT & 3458 PCTL2_MR_MASK) & (~(BIT(7)))) | 3459 dst_fsp_lp4 << 7, dramtype); 3460 } 3461 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 3462 PCTL2_DIS_AUTO_REFRESH); 3463 update_refresh_reg(dram); 3464 3465 /* training */ 3466 high_freq_training(dram, sdram_params_new, dst_fsp); 3467 low_power_update(dram, lp_stat); 3468 3469 save_fsp_param(dram, dst_fsp, sdram_params_new); 3470 } 3471 3472 static void ddr_set_rate_for_fsp(struct dram_info *dram, 3473 struct rv1126_sdram_params *sdram_params) 3474 { 3475 struct ddr2_3_4_lp2_3_info *ddr_info; 3476 u32 f0; 3477 u32 dramtype = sdram_params->base.dramtype; 3478 #ifndef CONFIG_SPL_KERNEL_BOOT 3479 u32 f1, f2, f3; 3480 #endif 3481 3482 ddr_info = get_ddr_drv_odt_info(dramtype); 3483 if (!ddr_info) 3484 return; 3485 3486 f0 = (ddr_info->ddr_freq0_1 >> DDR_FREQ_F0_SHIFT) & 3487 DDR_FREQ_MASK; 3488 3489 #ifndef CONFIG_SPL_KERNEL_BOOT 3490 memset((void *)FSP_PARAM_STORE_ADDR, 0, sizeof(fsp_param)); 3491 memset((void *)&fsp_param, 0, sizeof(fsp_param)); 3492 3493 f1 = (ddr_info->ddr_freq0_1 >> DDR_FREQ_F1_SHIFT) & 3494 DDR_FREQ_MASK; 3495 f2 = (ddr_info->ddr_freq2_3 >> DDR_FREQ_F2_SHIFT) & 3496 DDR_FREQ_MASK; 3497 f3 = (ddr_info->ddr_freq2_3 >> DDR_FREQ_F3_SHIFT) & 3498 DDR_FREQ_MASK; 3499 #endif 3500 3501 if (get_wrlvl_val(dram, sdram_params)) 3502 printascii("get wrlvl value fail\n"); 3503 3504 #ifndef CONFIG_SPL_KERNEL_BOOT 3505 printascii("change to: "); 3506 printdec(f1); 3507 printascii("MHz\n"); 3508 ddr_set_rate(&dram_info, sdram_params, f1, 3509 sdram_params->base.ddr_freq, 1, 1, 1); 3510 printascii("change to: "); 3511 printdec(f2); 3512 printascii("MHz\n"); 3513 ddr_set_rate(&dram_info, sdram_params, f2, f1, 2, 0, 1); 3514 printascii("change to: "); 3515 printdec(f3); 3516 printascii("MHz\n"); 3517 ddr_set_rate(&dram_info, sdram_params, f3, f2, 3, 1, 1); 3518 #endif 3519 printascii("change to: "); 3520 printdec(f0); 3521 printascii("MHz(final freq)\n"); 3522 #ifndef CONFIG_SPL_KERNEL_BOOT 3523 ddr_set_rate(&dram_info, sdram_params, f0, f3, 0, 0, 1); 3524 #else 3525 ddr_set_rate(&dram_info, sdram_params, f0, sdram_params->base.ddr_freq, 1, 1, 1); 3526 #endif 3527 } 3528 3529 int get_uart_config(void) 3530 { 3531 struct sdram_head_info_index_v2 *index = 3532 (struct sdram_head_info_index_v2 *)common_info; 3533 struct global_info *gbl_info; 3534 3535 gbl_info = (struct global_info *)((void *)common_info + 3536 index->global_index.offset * 4); 3537 3538 return gbl_info->uart_info; 3539 } 3540 3541 /* return: 0 = success, other = fail */ 3542 int sdram_init(void) 3543 { 3544 struct rv1126_sdram_params *sdram_params; 3545 int ret = 0; 3546 struct sdram_head_info_index_v2 *index = 3547 (struct sdram_head_info_index_v2 *)common_info; 3548 struct global_info *gbl_info; 3549 3550 dram_info.phy = (void *)DDR_PHY_BASE_ADDR; 3551 dram_info.pctl = (void *)UPCTL2_BASE_ADDR; 3552 dram_info.grf = (void *)GRF_BASE_ADDR; 3553 dram_info.cru = (void *)CRU_BASE_ADDR; 3554 dram_info.msch = (void *)SERVER_MSCH_BASE_ADDR; 3555 dram_info.ddrgrf = (void *)DDR_GRF_BASE_ADDR; 3556 dram_info.pmugrf = (void *)PMU_GRF_BASE_ADDR; 3557 3558 #ifdef CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT 3559 printascii("extended temp support\n"); 3560 #endif 3561 if (index->version_info != 2 || 3562 (index->global_index.size != sizeof(struct global_info) / 4) || 3563 (index->ddr3_index.size != 3564 sizeof(struct ddr2_3_4_lp2_3_info) / 4) || 3565 (index->ddr4_index.size != 3566 sizeof(struct ddr2_3_4_lp2_3_info) / 4) || 3567 (index->lp3_index.size != 3568 sizeof(struct ddr2_3_4_lp2_3_info) / 4) || 3569 (index->lp4_index.size != (sizeof(struct lp4_info) / 4)) || 3570 (index->lp4x_index.size != (sizeof(struct lp4_info) / 4)) || 3571 index->global_index.offset == 0 || 3572 index->ddr3_index.offset == 0 || 3573 index->ddr4_index.offset == 0 || 3574 index->lp3_index.offset == 0 || 3575 index->lp4_index.offset == 0 || 3576 index->lp4x_index.offset == 0) { 3577 printascii("common info error\n"); 3578 goto error; 3579 } 3580 3581 gbl_info = (struct global_info *)((void *)common_info + 3582 index->global_index.offset * 4); 3583 3584 dram_info.sr_idle = SR_INFO(gbl_info->sr_pd_info); 3585 dram_info.pd_idle = PD_INFO(gbl_info->sr_pd_info); 3586 3587 sdram_params = &sdram_configs[0]; 3588 #if (CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE == 8) 3589 for (int j = 0; j < ARRAY_SIZE(sdram_configs); j++) 3590 sdram_configs[j].base.dramtype = LPDDR4X; 3591 #endif 3592 if (sdram_params->base.dramtype == DDR3 || 3593 sdram_params->base.dramtype == DDR4) { 3594 if (DDR_2T_INFO(gbl_info->info_2t)) 3595 sdram_params->pctl_regs.pctl[0][1] |= 0x1 << 10; 3596 else 3597 sdram_params->pctl_regs.pctl[0][1] &= 3598 ~(0x1 << 10); 3599 } 3600 ret = sdram_init_detect(&dram_info, sdram_params); 3601 if (ret) { 3602 sdram_print_dram_type(sdram_params->base.dramtype); 3603 printascii(", "); 3604 printdec(sdram_params->base.ddr_freq); 3605 printascii("MHz\n"); 3606 goto error; 3607 } 3608 print_ddr_info(sdram_params); 3609 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 3610 init_rw_trn_result_struct(&rw_trn_result, dram_info.phy, 3611 (u8)sdram_params->ch.cap_info.rank); 3612 #endif 3613 3614 ddr_set_rate_for_fsp(&dram_info, sdram_params); 3615 #ifndef CONFIG_SPL_KERNEL_BOOT 3616 copy_fsp_param_to_ddr(); 3617 #endif 3618 3619 ddr_set_atags(&dram_info, sdram_params); 3620 #if defined(CONFIG_CMD_DDR_TEST_TOOL) 3621 save_rw_trn_result_to_ddr(&rw_trn_result); 3622 #endif 3623 3624 printascii("out\n"); 3625 3626 return ret; 3627 error: 3628 printascii("error\n"); 3629 return (-1); 3630 } 3631 #endif /* CONFIG_TPL_BUILD */ 3632