1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 secure_otp: secure_otp@0xff5d0000 { 19 compatible = "rockchip,rv1126-secure-otp"; 20 reg = <0xff5d0000 0x4000>; 21 secure_conf = <0xfe0a0008>; 22 }; 23}; 24 25&uart2 { 26 clock-frequency = <24000000>; 27 u-boot,dm-spl; 28 /delete-property/ pinctrl-names; 29 /delete-property/ pinctrl-0; 30}; 31 32&sdmmc { 33 u-boot,dm-spl; 34 status = "okay"; 35}; 36 37&sdmmc0 { 38 u-boot,dm-spl; 39}; 40 41&sdmmc0_bus4 { 42 u-boot,dm-spl; 43}; 44 45&sdmmc0_clk { 46 u-boot,dm-spl; 47}; 48 49&sdmmc0_cmd { 50 u-boot,dm-spl; 51}; 52 53&sdmmc0_det { 54 u-boot,dm-spl; 55}; 56 57&emmc { 58 mmc-ecsd = <0x0020f000>; 59 u-boot,dm-spl; 60 /delete-property/ pinctrl-names; 61 /delete-property/ pinctrl-0; 62}; 63 64&pmu { 65 u-boot,dm-spl; 66}; 67 68&pmugrf { 69 u-boot,dm-spl; 70}; 71 72&pmucru { 73 u-boot,dm-spl; 74}; 75 76&cru { 77 u-boot,dm-spl; 78 /delete-property/ assigned-clocks; 79 /delete-property/ assigned-clock-rates; 80 /delete-property/ assigned-clock-parents; 81}; 82 83&crypto { 84 u-boot,dm-spl; 85 status = "okay"; 86}; 87 88&grf { 89 u-boot,dm-spl; 90}; 91 92&saradc { 93 u-boot,dm-spl; 94 status = "okay"; 95}; 96 97&sfc { 98 u-boot,dm-spl; 99 /delete-property/ pinctrl-names; 100 /delete-property/ pinctrl-0; 101 /delete-property/ assigned-clocks; 102 /delete-property/ assigned-clock-rates; 103 status = "okay"; 104 105 #address-cells = <1>; 106 #size-cells = <0>; 107 spi_nand: flash@0 { 108 u-boot,dm-spl; 109 compatible = "spi-nand"; 110 reg = <0>; 111 spi-tx-bus-width = <1>; 112 spi-rx-bus-width = <4>; 113 spi-max-frequency = <96000000>; 114 }; 115 116 spi_nor: flash@1 { 117 u-boot,dm-spl; 118 compatible = "jedec,spi-nor"; 119 label = "sfc_nor"; 120 reg = <0>; 121 spi-tx-bus-width = <1>; 122 spi-rx-bus-width = <4>; 123 spi-max-frequency = <100000000>; 124 }; 125}; 126 127&nandc { 128 u-boot,dm-spl; 129 /delete-property/ pinctrl-names; 130 /delete-property/ pinctrl-0; 131 status = "okay"; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 135 nand@0 { 136 u-boot,dm-spl; 137 reg = <0>; 138 nand-ecc-mode = "hw_syndrome"; 139 nand-ecc-strength = <16>; 140 nand-ecc-step-size = <1024>; 141 }; 142}; 143 144&hw_decompress { 145 u-boot,dm-spl; 146 status = "okay"; 147}; 148 149&secure_otp { 150 u-boot,dm-spl; 151 status = "okay"; 152}; 153 154&i2c0 { 155 u-boot,dm-spl; 156 status = "okay"; 157 rk817_fg@20 { 158 u-boot,dm-spl; 159 compatible = "rk817,battery"; 160 reg = <0x20>; 161 bat_res_up = <140>; 162 bat_res_down = <20>; 163 }; 164}; 165 166&u2phy0 { 167 u-boot,dm-pre-reloc; 168 status = "okay"; 169}; 170 171&u2phy_otg { 172 u-boot,dm-pre-reloc; 173 status = "okay"; 174}; 175 176&usbdrd { 177 u-boot,dm-pre-reloc; 178 status = "okay"; 179}; 180 181&usbdrd_dwc3 { 182 u-boot,dm-pre-reloc; 183 status = "okay"; 184}; 185 186&pinctrl { 187 u-boot,dm-spl; 188 status = "okay"; 189}; 190 191&gpio1 { 192 u-boot,dm-spl; 193 status = "okay"; 194}; 195 196&pcfg_pull_up_drv_level_2 { 197 u-boot,dm-spl; 198}; 199 200&pcfg_pull_none { 201 u-boot,dm-spl; 202}; 203 204&gpio3 { 205 u-boot,dm-pre-reloc; 206 status = "okay"; 207}; 208 209&gmac { 210 u-boot,dm-pre-reloc; 211 212 phy-mode = "rgmii"; 213 clock_in_out = "input"; 214 215 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 216 snps,reset-active-low; 217 /* Reset time is 20ms, 100ms for rtl8211f */ 218 snps,reset-delays-us = <0 20000 100000>; 219 220 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 221 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 222 assigned-clock-rates = <125000000>, <0>, <25000000>; 223 224 pinctrl-names = "default"; 225 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 226 227 tx_delay = <0x2a>; 228 rx_delay = <0x1a>; 229 230 phy-handle = <&phy>; 231 status = "okay"; 232}; 233 234&mdio { 235 u-boot,dm-pre-reloc; 236 status = "okay"; 237 238 phy: phy@0 { 239 compatible = "ethernet-phy-ieee802.3-c22"; 240 u-boot,dm-pre-reloc; 241 reg = <0x0>; 242 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 243 }; 244}; 245 246&stmmac_axi_setup { 247 u-boot,dm-pre-reloc; 248 status = "okay"; 249 queue0 { 250 u-boot,dm-pre-reloc; 251 }; 252}; 253 254&mtl_rx_setup { 255 u-boot,dm-pre-reloc; 256 status = "okay"; 257 queue0 { 258 u-boot,dm-pre-reloc; 259 }; 260}; 261 262&mtl_tx_setup { 263 u-boot,dm-pre-reloc; 264 status = "okay"; 265}; 266 267&gmac_clkin_m0 { 268 u-boot,dm-pre-reloc; 269 status = "okay"; 270}; 271 272&gmac_clkini_m1 { 273 u-boot,dm-pre-reloc; 274 status = "okay"; 275}; 276 277&rgmiim1_pins { 278 u-boot,dm-pre-reloc; 279 status = "okay"; 280}; 281 282&rng { 283 u-boot,dm-spl; 284 status = "okay"; 285}; 286 287&clk_out_ethernetm1_pins{ 288 u-boot,dm-pre-reloc; 289 status = "okay"; 290}; 291 292&pcfg_pull_none { 293 u-boot,dm-pre-reloc; 294 status = "okay"; 295}; 296 297&pcfg_pull_none_drv_level_12 { 298 u-boot,dm-pre-reloc; 299 status = "okay"; 300}; 301 302&wdt { 303 u-boot,dm-pre-reloc; 304 status = "okay"; 305}; 306