1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 4 * 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <regmap.h> 14 #include <asm/arch/cpu.h> 15 #include <asm/unaligned.h> 16 #include <asm/io.h> 17 #include <linux/list.h> 18 #include <linux/log2.h> 19 #include <linux/media-bus-format.h> 20 #include <clk.h> 21 #include <asm/arch/clock.h> 22 #include <linux/err.h> 23 #include <linux/ioport.h> 24 #include <dm/device.h> 25 #include <dm/read.h> 26 #include <fixp-arith.h> 27 #include <syscon.h> 28 #include <linux/iopoll.h> 29 #include <dm/uclass-internal.h> 30 31 #include "rockchip_display.h" 32 #include "rockchip_crtc.h" 33 #include "rockchip_connector.h" 34 35 /* System registers definition */ 36 #define RK3568_REG_CFG_DONE 0x000 37 #define CFG_DONE_EN BIT(15) 38 39 #define RK3568_VERSION_INFO 0x004 40 #define EN_MASK 1 41 42 #define RK3568_AUTO_GATING_CTRL 0x008 43 44 #define RK3568_SYS_AXI_LUT_CTRL 0x024 45 #define LUT_DMA_EN_SHIFT 0 46 47 #define RK3568_DSP_IF_EN 0x028 48 #define RGB_EN_SHIFT 0 49 #define RK3588_DP0_EN_SHIFT 0 50 #define RK3588_DP1_EN_SHIFT 1 51 #define RK3588_RGB_EN_SHIFT 8 52 #define HDMI0_EN_SHIFT 1 53 #define EDP0_EN_SHIFT 3 54 #define RK3588_EDP0_EN_SHIFT 2 55 #define RK3588_HDMI0_EN_SHIFT 3 56 #define MIPI0_EN_SHIFT 4 57 #define RK3588_EDP1_EN_SHIFT 4 58 #define RK3588_HDMI1_EN_SHIFT 5 59 #define RK3588_MIPI0_EN_SHIFT 6 60 #define MIPI1_EN_SHIFT 20 61 #define RK3588_MIPI1_EN_SHIFT 7 62 #define LVDS0_EN_SHIFT 5 63 #define LVDS1_EN_SHIFT 24 64 #define BT1120_EN_SHIFT 6 65 #define BT656_EN_SHIFT 7 66 #define IF_MUX_MASK 3 67 #define RGB_MUX_SHIFT 8 68 #define HDMI0_MUX_SHIFT 10 69 #define RK3588_DP0_MUX_SHIFT 12 70 #define RK3588_DP1_MUX_SHIFT 14 71 #define EDP0_MUX_SHIFT 14 72 #define RK3588_HDMI_EDP0_MUX_SHIFT 16 73 #define RK3588_HDMI_EDP1_MUX_SHIFT 18 74 #define MIPI0_MUX_SHIFT 16 75 #define RK3588_MIPI0_MUX_SHIFT 20 76 #define MIPI1_MUX_SHIFT 21 77 #define LVDS0_MUX_SHIFT 18 78 #define LVDS1_MUX_SHIFT 25 79 80 #define RK3568_DSP_IF_CTRL 0x02c 81 #define LVDS_DUAL_EN_SHIFT 0 82 #define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1 83 #define LVDS_DUAL_SWAP_EN_SHIFT 2 84 #define RK3588_HDMI_DUAL_EN_SHIFT 8 85 #define RK3588_EDP_DUAL_EN_SHIFT 8 86 #define RK3588_DP_DUAL_EN_SHIFT 9 87 #define RK3568_MIPI_DUAL_EN_SHIFT 10 88 #define RK3588_MIPI_DSI0_MODE_SEL_SHIFT 11 89 #define RK3588_MIPI_DSI1_MODE_SEL_SHIFT 12 90 91 #define RK3568_DSP_IF_POL 0x030 92 #define IF_CTRL_REG_DONE_IMD_MASK 1 93 #define IF_CTRL_REG_DONE_IMD_SHIFT 28 94 #define IF_CRTL_MIPI_DCLK_POL_SHIT 19 95 #define IF_CRTL_EDP_DCLK_POL_SHIT 15 96 #define IF_CRTL_HDMI_DCLK_POL_SHIT 7 97 #define IF_CRTL_HDMI_PIN_POL_MASK 0x7 98 #define IF_CRTL_HDMI_PIN_POL_SHIT 4 99 100 #define RK3588_DP0_PIN_POL_SHIFT 8 101 #define RK3588_DP1_PIN_POL_SHIFT 12 102 #define RK3588_IF_PIN_POL_MASK 0x7 103 104 #define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3 105 106 #define HDMI_EDP0_DCLK_DIV_SHIFT 16 107 #define HDMI_EDP0_PIXCLK_DIV_SHIFT 18 108 #define HDMI_EDP1_DCLK_DIV_SHIFT 20 109 #define HDMI_EDP1_PIXCLK_DIV_SHIFT 22 110 #define MIPI0_PIXCLK_DIV_SHIFT 24 111 #define MIPI1_PIXCLK_DIV_SHIFT 26 112 113 #define RK3568_SYS_OTP_WIN_EN 0x50 114 #define OTP_WIN_EN_SHIFT 0 115 #define RK3568_SYS_LUT_PORT_SEL 0x58 116 #define GAMMA_PORT_SEL_MASK 0x3 117 #define GAMMA_PORT_SEL_SHIFT 0 118 #define PORT_MERGE_EN_SHIFT 16 119 120 #define RK3568_SYS_PD_CTRL 0x034 121 #define RK3568_VP0_LINE_FLAG 0x70 122 #define RK3568_VP1_LINE_FLAG 0x74 123 #define RK3568_VP2_LINE_FLAG 0x78 124 #define RK3568_SYS0_INT_EN 0x80 125 #define RK3568_SYS0_INT_CLR 0x84 126 #define RK3568_SYS0_INT_STATUS 0x88 127 #define RK3568_SYS1_INT_EN 0x90 128 #define RK3568_SYS1_INT_CLR 0x94 129 #define RK3568_SYS1_INT_STATUS 0x98 130 #define RK3568_VP0_INT_EN 0xA0 131 #define RK3568_VP0_INT_CLR 0xA4 132 #define RK3568_VP0_INT_STATUS 0xA8 133 #define RK3568_VP1_INT_EN 0xB0 134 #define RK3568_VP1_INT_CLR 0xB4 135 #define RK3568_VP1_INT_STATUS 0xB8 136 #define RK3568_VP2_INT_EN 0xC0 137 #define RK3568_VP2_INT_CLR 0xC4 138 #define RK3568_VP2_INT_STATUS 0xC8 139 #define RK3588_CLUSTER0_PD_EN_SHIFT 0 140 #define RK3588_CLUSTER1_PD_EN_SHIFT 1 141 #define RK3588_CLUSTER2_PD_EN_SHIFT 2 142 #define RK3588_CLUSTER3_PD_EN_SHIFT 3 143 #define RK3588_DSC_8K_PD_EN_SHIFT 5 144 #define RK3588_DSC_4K_PD_EN_SHIFT 6 145 #define RK3588_ESMART_PD_EN_SHIFT 7 146 147 #define RK3568_SYS_STATUS0 0x60 148 #define RK3588_CLUSTER0_PD_STATUS_SHIFT 8 149 #define RK3588_CLUSTER1_PD_STATUS_SHIFT 9 150 #define RK3588_CLUSTER2_PD_STATUS_SHIFT 10 151 #define RK3588_CLUSTER3_PD_STATUS_SHIFT 11 152 #define RK3588_DSC_8K_PD_STATUS_SHIFT 13 153 #define RK3588_DSC_4K_PD_STATUS_SHIFT 14 154 #define RK3588_ESMART_PD_STATUS_SHIFT 15 155 156 #define RK3568_SYS_CTRL_LINE_FLAG0 0x70 157 #define LINE_FLAG_NUM_MASK 0x1fff 158 #define RK3568_DSP_LINE_FLAG_NUM0_SHIFT 0 159 #define RK3568_DSP_LINE_FLAG_NUM1_SHIFT 16 160 161 /* DSC CTRL registers definition */ 162 #define RK3588_DSC_8K_SYS_CTRL 0x200 163 #define DSC_PORT_SEL_MASK 0x3 164 #define DSC_PORT_SEL_SHIFT 0 165 #define DSC_MAN_MODE_MASK 0x1 166 #define DSC_MAN_MODE_SHIFT 2 167 #define DSC_INTERFACE_MODE_MASK 0x3 168 #define DSC_INTERFACE_MODE_SHIFT 4 169 #define DSC_PIXEL_NUM_MASK 0x3 170 #define DSC_PIXEL_NUM_SHIFT 6 171 #define DSC_PXL_CLK_DIV_MASK 0x1 172 #define DSC_PXL_CLK_DIV_SHIFT 8 173 #define DSC_CDS_CLK_DIV_MASK 0x3 174 #define DSC_CDS_CLK_DIV_SHIFT 12 175 #define DSC_TXP_CLK_DIV_MASK 0x3 176 #define DSC_TXP_CLK_DIV_SHIFT 14 177 #define DSC_INIT_DLY_MODE_MASK 0x1 178 #define DSC_INIT_DLY_MODE_SHIFT 16 179 #define DSC_SCAN_EN_SHIFT 17 180 #define DSC_HALT_EN_SHIFT 18 181 182 #define RK3588_DSC_8K_RST 0x204 183 #define RST_DEASSERT_MASK 0x1 184 #define RST_DEASSERT_SHIFT 0 185 186 #define RK3588_DSC_8K_CFG_DONE 0x208 187 #define DSC_CFG_DONE_SHIFT 0 188 189 #define RK3588_DSC_8K_INIT_DLY 0x20C 190 #define DSC_INIT_DLY_NUM_MASK 0xffff 191 #define DSC_INIT_DLY_NUM_SHIFT 0 192 #define SCAN_TIMING_PARA_IMD_EN_SHIFT 16 193 194 #define RK3588_DSC_8K_HTOTAL_HS_END 0x210 195 #define DSC_HTOTAL_PW_MASK 0xffffffff 196 #define DSC_HTOTAL_PW_SHIFT 0 197 198 #define RK3588_DSC_8K_HACT_ST_END 0x214 199 #define DSC_HACT_ST_END_MASK 0xffffffff 200 #define DSC_HACT_ST_END_SHIFT 0 201 202 #define RK3588_DSC_8K_VTOTAL_VS_END 0x218 203 #define DSC_VTOTAL_PW_MASK 0xffffffff 204 #define DSC_VTOTAL_PW_SHIFT 0 205 206 #define RK3588_DSC_8K_VACT_ST_END 0x21C 207 #define DSC_VACT_ST_END_MASK 0xffffffff 208 #define DSC_VACT_ST_END_SHIFT 0 209 210 #define RK3588_DSC_8K_STATUS 0x220 211 212 /* Overlay registers definition */ 213 #define RK3568_OVL_CTRL 0x600 214 #define OVL_MODE_SEL_MASK 0x1 215 #define OVL_MODE_SEL_SHIFT 0 216 #define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28 217 #define RK3568_OVL_LAYER_SEL 0x604 218 #define LAYER_SEL_MASK 0xf 219 220 #define RK3568_OVL_PORT_SEL 0x608 221 #define PORT_MUX_MASK 0xf 222 #define PORT_MUX_SHIFT 0 223 #define LAYER_SEL_PORT_MASK 0x3 224 #define LAYER_SEL_PORT_SHIFT 16 225 226 #define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL 0x610 227 #define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614 228 #define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618 229 #define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C 230 #define RK3568_MIX0_SRC_COLOR_CTRL 0x650 231 #define RK3568_MIX0_DST_COLOR_CTRL 0x654 232 #define RK3568_MIX0_SRC_ALPHA_CTRL 0x658 233 #define RK3568_MIX0_DST_ALPHA_CTRL 0x65C 234 #define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0 235 #define RK3568_HDR0_DST_COLOR_CTRL 0x6C4 236 #define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8 237 #define RK3568_HDR0_DST_ALPHA_CTRL 0x6CC 238 #define RK3568_VP0_BG_MIX_CTRL 0x6E0 239 #define BG_MIX_CTRL_MASK 0xff 240 #define BG_MIX_CTRL_SHIFT 24 241 #define RK3568_VP1_BG_MIX_CTRL 0x6E4 242 #define RK3568_VP2_BG_MIX_CTRL 0x6E8 243 #define RK3568_CLUSTER_DLY_NUM 0x6F0 244 #define RK3568_SMART_DLY_NUM 0x6F8 245 246 /* Video Port registers definition */ 247 #define RK3568_VP0_DSP_CTRL 0xC00 248 #define OUT_MODE_MASK 0xf 249 #define OUT_MODE_SHIFT 0 250 #define DATA_SWAP_MASK 0x1f 251 #define DATA_SWAP_SHIFT 8 252 #define DSP_BG_SWAP 0x1 253 #define DSP_RB_SWAP 0x2 254 #define DSP_RG_SWAP 0x4 255 #define DSP_DELTA_SWAP 0x8 256 #define CORE_DCLK_DIV_EN_SHIFT 4 257 #define P2I_EN_SHIFT 5 258 #define DSP_FILED_POL 6 259 #define INTERLACE_EN_SHIFT 7 260 #define POST_DSP_OUT_R2Y_SHIFT 15 261 #define PRE_DITHER_DOWN_EN_SHIFT 16 262 #define DITHER_DOWN_EN_SHIFT 17 263 #define DSP_LUT_EN_SHIFT 28 264 265 #define STANDBY_EN_SHIFT 31 266 267 #define RK3568_VP0_MIPI_CTRL 0xC04 268 #define DCLK_DIV2_SHIFT 4 269 #define DCLK_DIV2_MASK 0x3 270 #define MIPI_DUAL_EN_SHIFT 20 271 #define MIPI_DUAL_SWAP_EN_SHIFT 21 272 #define EDPI_TE_EN 28 273 #define EDPI_WMS_HOLD_EN 30 274 #define EDPI_WMS_FS 31 275 276 277 #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 278 #define RK3568_VP0_3D_LUT_CTRL 0xC10 279 #define VP0_3D_LUT_EN_SHIFT 0 280 #define VP0_3D_LUT_UPDATE_SHIFT 2 281 282 #define RK3588_VP0_CLK_CTRL 0xC0C 283 #define DCLK_CORE_DIV_SHIFT 0 284 #define DCLK_OUT_DIV_SHIFT 2 285 286 #define RK3568_VP0_3D_LUT_MST 0xC20 287 288 #define RK3568_VP0_DSP_BG 0xC2C 289 #define RK3568_VP0_PRE_SCAN_HTIMING 0xC30 290 #define RK3568_VP0_POST_DSP_HACT_INFO 0xC34 291 #define RK3568_VP0_POST_DSP_VACT_INFO 0xC38 292 #define RK3568_VP0_POST_SCL_FACTOR_YRGB 0xC3C 293 #define RK3568_VP0_POST_SCL_CTRL 0xC40 294 #define RK3568_VP0_POST_DSP_VACT_INFO_F1 0xC44 295 #define RK3568_VP0_DSP_HTOTAL_HS_END 0xC48 296 #define RK3568_VP0_DSP_HACT_ST_END 0xC4C 297 #define RK3568_VP0_DSP_VTOTAL_VS_END 0xC50 298 #define RK3568_VP0_DSP_VACT_ST_END 0xC54 299 #define RK3568_VP0_DSP_VS_ST_END_F1 0xC58 300 #define RK3568_VP0_DSP_VACT_ST_END_F1 0xC5C 301 302 #define RK3568_VP0_BCSH_CTRL 0xC60 303 #define BCSH_CTRL_Y2R_SHIFT 0 304 #define BCSH_CTRL_Y2R_MASK 0x1 305 #define BCSH_CTRL_Y2R_CSC_MODE_SHIFT 2 306 #define BCSH_CTRL_Y2R_CSC_MODE_MASK 0x3 307 #define BCSH_CTRL_R2Y_SHIFT 4 308 #define BCSH_CTRL_R2Y_MASK 0x1 309 #define BCSH_CTRL_R2Y_CSC_MODE_SHIFT 6 310 #define BCSH_CTRL_R2Y_CSC_MODE_MASK 0x3 311 312 #define RK3568_VP0_BCSH_BCS 0xC64 313 #define BCSH_BRIGHTNESS_SHIFT 0 314 #define BCSH_BRIGHTNESS_MASK 0xFF 315 #define BCSH_CONTRAST_SHIFT 8 316 #define BCSH_CONTRAST_MASK 0x1FF 317 #define BCSH_SATURATION_SHIFT 20 318 #define BCSH_SATURATION_MASK 0x3FF 319 #define BCSH_OUT_MODE_SHIFT 30 320 #define BCSH_OUT_MODE_MASK 0x3 321 322 #define RK3568_VP0_BCSH_H 0xC68 323 #define BCSH_SIN_HUE_SHIFT 0 324 #define BCSH_SIN_HUE_MASK 0x1FF 325 #define BCSH_COS_HUE_SHIFT 16 326 #define BCSH_COS_HUE_MASK 0x1FF 327 328 #define RK3568_VP0_BCSH_COLOR 0xC6C 329 #define BCSH_EN_SHIFT 31 330 #define BCSH_EN_MASK 1 331 332 #define RK3568_VP1_DSP_CTRL 0xD00 333 #define RK3568_VP1_MIPI_CTRL 0xD04 334 #define RK3568_VP1_COLOR_BAR_CTRL 0xD08 335 #define RK3568_VP1_PRE_SCAN_HTIMING 0xD30 336 #define RK3568_VP1_POST_DSP_HACT_INFO 0xD34 337 #define RK3568_VP1_POST_DSP_VACT_INFO 0xD38 338 #define RK3568_VP1_POST_SCL_FACTOR_YRGB 0xD3C 339 #define RK3568_VP1_POST_SCL_CTRL 0xD40 340 #define RK3568_VP1_DSP_HACT_INFO 0xD34 341 #define RK3568_VP1_DSP_VACT_INFO 0xD38 342 #define RK3568_VP1_POST_DSP_VACT_INFO_F1 0xD44 343 #define RK3568_VP1_DSP_HTOTAL_HS_END 0xD48 344 #define RK3568_VP1_DSP_HACT_ST_END 0xD4C 345 #define RK3568_VP1_DSP_VTOTAL_VS_END 0xD50 346 #define RK3568_VP1_DSP_VACT_ST_END 0xD54 347 #define RK3568_VP1_DSP_VS_ST_END_F1 0xD58 348 #define RK3568_VP1_DSP_VACT_ST_END_F1 0xD5C 349 350 #define RK3568_VP2_DSP_CTRL 0xE00 351 #define RK3568_VP2_MIPI_CTRL 0xE04 352 #define RK3568_VP2_COLOR_BAR_CTRL 0xE08 353 #define RK3568_VP2_PRE_SCAN_HTIMING 0xE30 354 #define RK3568_VP2_POST_DSP_HACT_INFO 0xE34 355 #define RK3568_VP2_POST_DSP_VACT_INFO 0xE38 356 #define RK3568_VP2_POST_SCL_FACTOR_YRGB 0xE3C 357 #define RK3568_VP2_POST_SCL_CTRL 0xE40 358 #define RK3568_VP2_DSP_HACT_INFO 0xE34 359 #define RK3568_VP2_DSP_VACT_INFO 0xE38 360 #define RK3568_VP2_POST_DSP_VACT_INFO_F1 0xE44 361 #define RK3568_VP2_DSP_HTOTAL_HS_END 0xE48 362 #define RK3568_VP2_DSP_HACT_ST_END 0xE4C 363 #define RK3568_VP2_DSP_VTOTAL_VS_END 0xE50 364 #define RK3568_VP2_DSP_VACT_ST_END 0xE54 365 #define RK3568_VP2_DSP_VS_ST_END_F1 0xE58 366 #define RK3568_VP2_DSP_VACT_ST_END_F1 0xE5C 367 368 /* Cluster0 register definition */ 369 #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 370 #define CLUSTER_YUV2RGB_EN_SHIFT 8 371 #define CLUSTER_RGB2YUV_EN_SHIFT 9 372 #define CLUSTER_CSC_MODE_SHIFT 10 373 #define CLUSTER_YRGB_XSCL_MODE_SHIFT 12 374 #define CLUSTER_YRGB_YSCL_MODE_SHIFT 14 375 #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 376 #define CLUSTER_YRGB_GT2_SHIFT 28 377 #define CLUSTER_YRGB_GT4_SHIFT 29 378 #define RK3568_CLUSTER0_WIN0_CTRL2 0x1008 379 #define CLUSTER_AXI_YRGB_ID_MASK 0x1f 380 #define CLUSTER_AXI_YRGB_ID_SHIFT 0 381 #define CLUSTER_AXI_UV_ID_MASK 0x1f 382 #define CLUSTER_AXI_UV_ID_SHIFT 5 383 384 #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 385 #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 386 #define RK3568_CLUSTER0_WIN0_VIR 0x1018 387 #define RK3568_CLUSTER0_WIN0_ACT_INFO 0x1020 388 #define RK3568_CLUSTER0_WIN0_DSP_INFO 0x1024 389 #define RK3568_CLUSTER0_WIN0_DSP_ST 0x1028 390 #define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB 0x1030 391 #define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE 0x1054 392 #define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR 0x1058 393 #define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH 0x105C 394 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE 0x1060 395 #define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064 396 #define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068 397 #define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C 398 399 #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 400 #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 401 #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 402 #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 403 #define RK3568_CLUSTER0_WIN1_VIR 0x1098 404 #define RK3568_CLUSTER0_WIN1_ACT_INFO 0x10A0 405 #define RK3568_CLUSTER0_WIN1_DSP_INFO 0x10A4 406 #define RK3568_CLUSTER0_WIN1_DSP_ST 0x10A8 407 #define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB 0x10B0 408 #define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE 0x10D4 409 #define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR 0x10D8 410 #define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH 0x10DC 411 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE 0x10E0 412 #define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET 0x10E4 413 #define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET 0x10E8 414 #define RK3568_CLUSTER0_WIN1_AFBCD_CTRL 0x10EC 415 416 #define RK3568_CLUSTER0_CTRL 0x1100 417 #define CLUSTER_EN_SHIFT 0 418 #define CLUSTER_AXI_ID_MASK 0x1 419 #define CLUSTER_AXI_ID_SHIFT 13 420 421 #define RK3568_CLUSTER1_WIN0_CTRL0 0x1200 422 #define RK3568_CLUSTER1_WIN0_CTRL1 0x1204 423 #define RK3568_CLUSTER1_WIN0_YRGB_MST 0x1210 424 #define RK3568_CLUSTER1_WIN0_CBR_MST 0x1214 425 #define RK3568_CLUSTER1_WIN0_VIR 0x1218 426 #define RK3568_CLUSTER1_WIN0_ACT_INFO 0x1220 427 #define RK3568_CLUSTER1_WIN0_DSP_INFO 0x1224 428 #define RK3568_CLUSTER1_WIN0_DSP_ST 0x1228 429 #define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB 0x1230 430 #define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE 0x1254 431 #define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR 0x1258 432 #define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH 0x125C 433 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE 0x1260 434 #define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET 0x1264 435 #define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET 0x1268 436 #define RK3568_CLUSTER1_WIN0_AFBCD_CTRL 0x126C 437 438 #define RK3568_CLUSTER1_WIN1_CTRL0 0x1280 439 #define RK3568_CLUSTER1_WIN1_CTRL1 0x1284 440 #define RK3568_CLUSTER1_WIN1_YRGB_MST 0x1290 441 #define RK3568_CLUSTER1_WIN1_CBR_MST 0x1294 442 #define RK3568_CLUSTER1_WIN1_VIR 0x1298 443 #define RK3568_CLUSTER1_WIN1_ACT_INFO 0x12A0 444 #define RK3568_CLUSTER1_WIN1_DSP_INFO 0x12A4 445 #define RK3568_CLUSTER1_WIN1_DSP_ST 0x12A8 446 #define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB 0x12B0 447 #define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE 0x12D4 448 #define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR 0x12D8 449 #define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH 0x12DC 450 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE 0x12E0 451 #define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET 0x12E4 452 #define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET 0x12E8 453 #define RK3568_CLUSTER1_WIN1_AFBCD_CTRL 0x12EC 454 455 #define RK3568_CLUSTER1_CTRL 0x1300 456 457 /* Esmart register definition */ 458 #define RK3568_ESMART0_CTRL0 0x1800 459 #define RGB2YUV_EN_SHIFT 1 460 #define CSC_MODE_SHIFT 2 461 #define CSC_MODE_MASK 0x3 462 463 #define RK3568_ESMART0_CTRL1 0x1804 464 #define ESMART_AXI_YRGB_ID_MASK 0x1f 465 #define ESMART_AXI_YRGB_ID_SHIFT 4 466 #define ESMART_AXI_UV_ID_MASK 0x1f 467 #define ESMART_AXI_UV_ID_SHIFT 12 468 #define YMIRROR_EN_SHIFT 31 469 470 #define RK3568_ESMART0_AXI_CTRL 0x1808 471 #define ESMART_AXI_ID_MASK 0x1 472 #define ESMART_AXI_ID_SHIFT 1 473 474 #define RK3568_ESMART0_REGION0_CTRL 0x1810 475 #define REGION0_RB_SWAP_SHIFT 14 476 #define WIN_EN_SHIFT 0 477 #define WIN_FORMAT_MASK 0x1f 478 #define WIN_FORMAT_SHIFT 1 479 480 #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 481 #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 482 #define RK3568_ESMART0_REGION0_VIR 0x181C 483 #define RK3568_ESMART0_REGION0_ACT_INFO 0x1820 484 #define RK3568_ESMART0_REGION0_DSP_INFO 0x1824 485 #define RK3568_ESMART0_REGION0_DSP_ST 0x1828 486 #define RK3568_ESMART0_REGION0_SCL_CTRL 0x1830 487 #define YRGB_XSCL_MODE_MASK 0x3 488 #define YRGB_XSCL_MODE_SHIFT 0 489 #define YRGB_XSCL_FILTER_MODE_MASK 0x3 490 #define YRGB_XSCL_FILTER_MODE_SHIFT 2 491 #define YRGB_YSCL_MODE_MASK 0x3 492 #define YRGB_YSCL_MODE_SHIFT 4 493 #define YRGB_YSCL_FILTER_MODE_MASK 0x3 494 #define YRGB_YSCL_FILTER_MODE_SHIFT 6 495 496 #define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB 0x1834 497 #define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR 0x1838 498 #define RK3568_ESMART0_REGION0_SCL_OFFSET 0x183C 499 #define RK3568_ESMART0_REGION1_CTRL 0x1840 500 #define YRGB_GT2_MASK 0x1 501 #define YRGB_GT2_SHIFT 8 502 #define YRGB_GT4_MASK 0x1 503 #define YRGB_GT4_SHIFT 9 504 505 #define RK3568_ESMART0_REGION1_YRGB_MST 0x1844 506 #define RK3568_ESMART0_REGION1_CBR_MST 0x1848 507 #define RK3568_ESMART0_REGION1_VIR 0x184C 508 #define RK3568_ESMART0_REGION1_ACT_INFO 0x1850 509 #define RK3568_ESMART0_REGION1_DSP_INFO 0x1854 510 #define RK3568_ESMART0_REGION1_DSP_ST 0x1858 511 #define RK3568_ESMART0_REGION1_SCL_CTRL 0x1860 512 #define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB 0x1864 513 #define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR 0x1868 514 #define RK3568_ESMART0_REGION1_SCL_OFFSET 0x186C 515 #define RK3568_ESMART0_REGION2_CTRL 0x1870 516 #define RK3568_ESMART0_REGION2_YRGB_MST 0x1874 517 #define RK3568_ESMART0_REGION2_CBR_MST 0x1878 518 #define RK3568_ESMART0_REGION2_VIR 0x187C 519 #define RK3568_ESMART0_REGION2_ACT_INFO 0x1880 520 #define RK3568_ESMART0_REGION2_DSP_INFO 0x1884 521 #define RK3568_ESMART0_REGION2_DSP_ST 0x1888 522 #define RK3568_ESMART0_REGION2_SCL_CTRL 0x1890 523 #define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB 0x1894 524 #define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR 0x1898 525 #define RK3568_ESMART0_REGION2_SCL_OFFSET 0x189C 526 #define RK3568_ESMART0_REGION3_CTRL 0x18A0 527 #define RK3568_ESMART0_REGION3_YRGB_MST 0x18A4 528 #define RK3568_ESMART0_REGION3_CBR_MST 0x18A8 529 #define RK3568_ESMART0_REGION3_VIR 0x18AC 530 #define RK3568_ESMART0_REGION3_ACT_INFO 0x18B0 531 #define RK3568_ESMART0_REGION3_DSP_INFO 0x18B4 532 #define RK3568_ESMART0_REGION3_DSP_ST 0x18B8 533 #define RK3568_ESMART0_REGION3_SCL_CTRL 0x18C0 534 #define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB 0x18C4 535 #define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR 0x18C8 536 #define RK3568_ESMART0_REGION3_SCL_OFFSET 0x18CC 537 538 #define RK3568_ESMART1_CTRL0 0x1A00 539 #define RK3568_ESMART1_CTRL1 0x1A04 540 #define RK3568_ESMART1_REGION0_CTRL 0x1A10 541 #define RK3568_ESMART1_REGION0_YRGB_MST 0x1A14 542 #define RK3568_ESMART1_REGION0_CBR_MST 0x1A18 543 #define RK3568_ESMART1_REGION0_VIR 0x1A1C 544 #define RK3568_ESMART1_REGION0_ACT_INFO 0x1A20 545 #define RK3568_ESMART1_REGION0_DSP_INFO 0x1A24 546 #define RK3568_ESMART1_REGION0_DSP_ST 0x1A28 547 #define RK3568_ESMART1_REGION0_SCL_CTRL 0x1A30 548 #define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB 0x1A34 549 #define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR 0x1A38 550 #define RK3568_ESMART1_REGION0_SCL_OFFSET 0x1A3C 551 #define RK3568_ESMART1_REGION1_CTRL 0x1A40 552 #define RK3568_ESMART1_REGION1_YRGB_MST 0x1A44 553 #define RK3568_ESMART1_REGION1_CBR_MST 0x1A48 554 #define RK3568_ESMART1_REGION1_VIR 0x1A4C 555 #define RK3568_ESMART1_REGION1_ACT_INFO 0x1A50 556 #define RK3568_ESMART1_REGION1_DSP_INFO 0x1A54 557 #define RK3568_ESMART1_REGION1_DSP_ST 0x1A58 558 #define RK3568_ESMART1_REGION1_SCL_CTRL 0x1A60 559 #define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB 0x1A64 560 #define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR 0x1A68 561 #define RK3568_ESMART1_REGION1_SCL_OFFSET 0x1A6C 562 #define RK3568_ESMART1_REGION2_CTRL 0x1A70 563 #define RK3568_ESMART1_REGION2_YRGB_MST 0x1A74 564 #define RK3568_ESMART1_REGION2_CBR_MST 0x1A78 565 #define RK3568_ESMART1_REGION2_VIR 0x1A7C 566 #define RK3568_ESMART1_REGION2_ACT_INFO 0x1A80 567 #define RK3568_ESMART1_REGION2_DSP_INFO 0x1A84 568 #define RK3568_ESMART1_REGION2_DSP_ST 0x1A88 569 #define RK3568_ESMART1_REGION2_SCL_CTRL 0x1A90 570 #define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB 0x1A94 571 #define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR 0x1A98 572 #define RK3568_ESMART1_REGION2_SCL_OFFSET 0x1A9C 573 #define RK3568_ESMART1_REGION3_CTRL 0x1AA0 574 #define RK3568_ESMART1_REGION3_YRGB_MST 0x1AA4 575 #define RK3568_ESMART1_REGION3_CBR_MST 0x1AA8 576 #define RK3568_ESMART1_REGION3_VIR 0x1AAC 577 #define RK3568_ESMART1_REGION3_ACT_INFO 0x1AB0 578 #define RK3568_ESMART1_REGION3_DSP_INFO 0x1AB4 579 #define RK3568_ESMART1_REGION3_DSP_ST 0x1AB8 580 #define RK3568_ESMART1_REGION3_SCL_CTRL 0x1AC0 581 #define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB 0x1AC4 582 #define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR 0x1AC8 583 #define RK3568_ESMART1_REGION3_SCL_OFFSET 0x1ACC 584 585 #define RK3568_SMART0_CTRL0 0x1C00 586 #define RK3568_SMART0_CTRL1 0x1C04 587 #define RK3568_SMART0_REGION0_CTRL 0x1C10 588 #define RK3568_SMART0_REGION0_YRGB_MST 0x1C14 589 #define RK3568_SMART0_REGION0_CBR_MST 0x1C18 590 #define RK3568_SMART0_REGION0_VIR 0x1C1C 591 #define RK3568_SMART0_REGION0_ACT_INFO 0x1C20 592 #define RK3568_SMART0_REGION0_DSP_INFO 0x1C24 593 #define RK3568_SMART0_REGION0_DSP_ST 0x1C28 594 #define RK3568_SMART0_REGION0_SCL_CTRL 0x1C30 595 #define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB 0x1C34 596 #define RK3568_SMART0_REGION0_SCL_FACTOR_CBR 0x1C38 597 #define RK3568_SMART0_REGION0_SCL_OFFSET 0x1C3C 598 #define RK3568_SMART0_REGION1_CTRL 0x1C40 599 #define RK3568_SMART0_REGION1_YRGB_MST 0x1C44 600 #define RK3568_SMART0_REGION1_CBR_MST 0x1C48 601 #define RK3568_SMART0_REGION1_VIR 0x1C4C 602 #define RK3568_SMART0_REGION1_ACT_INFO 0x1C50 603 #define RK3568_SMART0_REGION1_DSP_INFO 0x1C54 604 #define RK3568_SMART0_REGION1_DSP_ST 0x1C58 605 #define RK3568_SMART0_REGION1_SCL_CTRL 0x1C60 606 #define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB 0x1C64 607 #define RK3568_SMART0_REGION1_SCL_FACTOR_CBR 0x1C68 608 #define RK3568_SMART0_REGION1_SCL_OFFSET 0x1C6C 609 #define RK3568_SMART0_REGION2_CTRL 0x1C70 610 #define RK3568_SMART0_REGION2_YRGB_MST 0x1C74 611 #define RK3568_SMART0_REGION2_CBR_MST 0x1C78 612 #define RK3568_SMART0_REGION2_VIR 0x1C7C 613 #define RK3568_SMART0_REGION2_ACT_INFO 0x1C80 614 #define RK3568_SMART0_REGION2_DSP_INFO 0x1C84 615 #define RK3568_SMART0_REGION2_DSP_ST 0x1C88 616 #define RK3568_SMART0_REGION2_SCL_CTRL 0x1C90 617 #define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB 0x1C94 618 #define RK3568_SMART0_REGION2_SCL_FACTOR_CBR 0x1C98 619 #define RK3568_SMART0_REGION2_SCL_OFFSET 0x1C9C 620 #define RK3568_SMART0_REGION3_CTRL 0x1CA0 621 #define RK3568_SMART0_REGION3_YRGB_MST 0x1CA4 622 #define RK3568_SMART0_REGION3_CBR_MST 0x1CA8 623 #define RK3568_SMART0_REGION3_VIR 0x1CAC 624 #define RK3568_SMART0_REGION3_ACT_INFO 0x1CB0 625 #define RK3568_SMART0_REGION3_DSP_INFO 0x1CB4 626 #define RK3568_SMART0_REGION3_DSP_ST 0x1CB8 627 #define RK3568_SMART0_REGION3_SCL_CTRL 0x1CC0 628 #define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB 0x1CC4 629 #define RK3568_SMART0_REGION3_SCL_FACTOR_CBR 0x1CC8 630 #define RK3568_SMART0_REGION3_SCL_OFFSET 0x1CCC 631 632 #define RK3568_SMART1_CTRL0 0x1E00 633 #define RK3568_SMART1_CTRL1 0x1E04 634 #define RK3568_SMART1_REGION0_CTRL 0x1E10 635 #define RK3568_SMART1_REGION0_YRGB_MST 0x1E14 636 #define RK3568_SMART1_REGION0_CBR_MST 0x1E18 637 #define RK3568_SMART1_REGION0_VIR 0x1E1C 638 #define RK3568_SMART1_REGION0_ACT_INFO 0x1E20 639 #define RK3568_SMART1_REGION0_DSP_INFO 0x1E24 640 #define RK3568_SMART1_REGION0_DSP_ST 0x1E28 641 #define RK3568_SMART1_REGION0_SCL_CTRL 0x1E30 642 #define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB 0x1E34 643 #define RK3568_SMART1_REGION0_SCL_FACTOR_CBR 0x1E38 644 #define RK3568_SMART1_REGION0_SCL_OFFSET 0x1E3C 645 #define RK3568_SMART1_REGION1_CTRL 0x1E40 646 #define RK3568_SMART1_REGION1_YRGB_MST 0x1E44 647 #define RK3568_SMART1_REGION1_CBR_MST 0x1E48 648 #define RK3568_SMART1_REGION1_VIR 0x1E4C 649 #define RK3568_SMART1_REGION1_ACT_INFO 0x1E50 650 #define RK3568_SMART1_REGION1_DSP_INFO 0x1E54 651 #define RK3568_SMART1_REGION1_DSP_ST 0x1E58 652 #define RK3568_SMART1_REGION1_SCL_CTRL 0x1E60 653 #define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB 0x1E64 654 #define RK3568_SMART1_REGION1_SCL_FACTOR_CBR 0x1E68 655 #define RK3568_SMART1_REGION1_SCL_OFFSET 0x1E6C 656 #define RK3568_SMART1_REGION2_CTRL 0x1E70 657 #define RK3568_SMART1_REGION2_YRGB_MST 0x1E74 658 #define RK3568_SMART1_REGION2_CBR_MST 0x1E78 659 #define RK3568_SMART1_REGION2_VIR 0x1E7C 660 #define RK3568_SMART1_REGION2_ACT_INFO 0x1E80 661 #define RK3568_SMART1_REGION2_DSP_INFO 0x1E84 662 #define RK3568_SMART1_REGION2_DSP_ST 0x1E88 663 #define RK3568_SMART1_REGION2_SCL_CTRL 0x1E90 664 #define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB 0x1E94 665 #define RK3568_SMART1_REGION2_SCL_FACTOR_CBR 0x1E98 666 #define RK3568_SMART1_REGION2_SCL_OFFSET 0x1E9C 667 #define RK3568_SMART1_REGION3_CTRL 0x1EA0 668 #define RK3568_SMART1_REGION3_YRGB_MST 0x1EA4 669 #define RK3568_SMART1_REGION3_CBR_MST 0x1EA8 670 #define RK3568_SMART1_REGION3_VIR 0x1EAC 671 #define RK3568_SMART1_REGION3_ACT_INFO 0x1EB0 672 #define RK3568_SMART1_REGION3_DSP_INFO 0x1EB4 673 #define RK3568_SMART1_REGION3_DSP_ST 0x1EB8 674 #define RK3568_SMART1_REGION3_SCL_CTRL 0x1EC0 675 #define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB 0x1EC4 676 #define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8 677 #define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC 678 679 /* DSC 8K/4K register definition */ 680 #define RK3588_DSC_8K_PPS0_3 0x4000 681 #define RK3588_DSC_8K_CTRL0 0x40A0 682 #define DSC_EN_SHIFT 0 683 #define DSC_RBIT_SHIFT 2 684 #define DSC_RBYT_SHIFT 3 685 #define DSC_FLAL_SHIFT 4 686 #define DSC_MER_SHIFT 5 687 #define DSC_EPB_SHIFT 6 688 #define DSC_EPL_SHIFT 7 689 #define DSC_NSLC_SHIFT 16 690 #define DSC_SBO_SHIFT 28 691 #define DSC_IFEP_SHIFT 29 692 #define DSC_PPS_UPD_SHIFT 31 693 694 #define RK3588_DSC_8K_CTRL1 0x40A4 695 #define RK3588_DSC_8K_STS0 0x40A8 696 #define RK3588_DSC_8K_ERS 0x40C4 697 698 #define RK3588_DSC_4K_PPS0_3 0x4100 699 #define RK3588_DSC_4K_CTRL0 0x41A0 700 #define RK3588_DSC_4K_CTRL1 0x41A4 701 #define RK3588_DSC_4K_STS0 0x41A8 702 #define RK3588_DSC_4K_ERS 0x41C4 703 704 #define RK3568_MAX_REG 0x1ED0 705 706 #define RK3568_GRF_VO_CON1 0x0364 707 #define GRF_BT656_CLK_INV_SHIFT 1 708 #define GRF_BT1120_CLK_INV_SHIFT 2 709 #define GRF_RGB_DCLK_INV_SHIFT 3 710 711 #define RK3588_GRF_VOP_CON2 0x0008 712 #define RK3588_GRF_EDP0_ENABLE_SHIFT 0 713 #define RK3588_GRF_HDMITX0_ENABLE_SHIFT 1 714 #define RK3588_GRF_EDP1_ENABLE_SHIFT 3 715 #define RK3588_GRF_HDMITX1_ENABLE_SHIFT 4 716 717 #define RK3588_GRF_VO1_CON0 0x0000 718 #define HDMI_SYNC_POL_MASK 0x3 719 #define HDMI0_SYNC_POL_SHIFT 5 720 #define HDMI1_SYNC_POL_SHIFT 7 721 722 #define RK3588_PMU_BISR_CON3 0x20C 723 #define RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT 9 724 #define RK3588_PD_CLUSTER1_REPAIR_EN_SHIFT 10 725 #define RK3588_PD_CLUSTER2_REPAIR_EN_SHIFT 11 726 #define RK3588_PD_CLUSTER3_REPAIR_EN_SHIFT 12 727 #define RK3588_PD_DSC_8K_REPAIR_EN_SHIFT 13 728 #define RK3588_PD_DSC_4K_REPAIR_EN_SHIFT 14 729 #define RK3588_PD_ESMART_REPAIR_EN_SHIFT 15 730 731 #define RK3588_PMU_BISR_STATUS5 0x294 732 #define RK3588_PD_CLUSTER0_PWR_STAT_SHIFI 9 733 #define RK3588_PD_CLUSTER1_PWR_STAT_SHIFI 10 734 #define RK3588_PD_CLUSTER2_PWR_STAT_SHIFI 11 735 #define RK3588_PD_CLUSTER3_PWR_STAT_SHIFI 12 736 #define RK3588_PD_DSC_8K_PWR_STAT_SHIFI 13 737 #define RK3588_PD_DSC_4K_PWR_STAT_SHIFI 14 738 #define RK3588_PD_ESMART_PWR_STAT_SHIFI 15 739 740 #define VOP2_LAYER_MAX 8 741 742 #define VOP2_MAX_VP_OUTPUT_WIDTH 4096 743 744 #define VOP_FEATURE_OUTPUT_10BIT BIT(0) 745 746 /* KHz */ 747 #define VOP2_MAX_DCLK_RATE 600000 748 749 /* 750 * vop2 dsc id 751 */ 752 #define ROCKCHIP_VOP2_DSC_8K 0 753 #define ROCKCHIP_VOP2_DSC_4K 1 754 755 /* 756 * vop2 internal power domain id, 757 * should be all none zero, 0 will be 758 * treat as invalid; 759 */ 760 #define VOP2_PD_CLUSTER0 BIT(0) 761 #define VOP2_PD_CLUSTER1 BIT(1) 762 #define VOP2_PD_CLUSTER2 BIT(2) 763 #define VOP2_PD_CLUSTER3 BIT(3) 764 #define VOP2_PD_DSC_8K BIT(5) 765 #define VOP2_PD_DSC_4K BIT(6) 766 #define VOP2_PD_ESMART BIT(7) 767 768 #define VOP2_PLANE_NO_SCALING BIT(16) 769 770 enum vop2_csc_format { 771 CSC_BT601L, 772 CSC_BT709L, 773 CSC_BT601F, 774 CSC_BT2020, 775 }; 776 777 enum vop2_pol { 778 HSYNC_POSITIVE = 0, 779 VSYNC_POSITIVE = 1, 780 DEN_NEGATIVE = 2, 781 DCLK_INVERT = 3 782 }; 783 784 enum vop2_bcsh_out_mode { 785 BCSH_OUT_MODE_BLACK, 786 BCSH_OUT_MODE_BLUE, 787 BCSH_OUT_MODE_COLOR_BAR, 788 BCSH_OUT_MODE_NORMAL_VIDEO, 789 }; 790 791 #define _VOP_REG(off, _mask, _shift, _write_mask) \ 792 { \ 793 .offset = off, \ 794 .mask = _mask, \ 795 .shift = _shift, \ 796 .write_mask = _write_mask, \ 797 } 798 799 #define VOP_REG(off, _mask, _shift) \ 800 _VOP_REG(off, _mask, _shift, false) 801 enum dither_down_mode { 802 RGB888_TO_RGB565 = 0x0, 803 RGB888_TO_RGB666 = 0x1 804 }; 805 806 enum vop2_video_ports_id { 807 VOP2_VP0, 808 VOP2_VP1, 809 VOP2_VP2, 810 VOP2_VP3, 811 VOP2_VP_MAX, 812 }; 813 814 enum vop2_layer_type { 815 CLUSTER_LAYER = 0, 816 ESMART_LAYER = 1, 817 SMART_LAYER = 2, 818 }; 819 820 /* This define must same with kernel win phy id */ 821 enum vop2_layer_phy_id { 822 ROCKCHIP_VOP2_CLUSTER0 = 0, 823 ROCKCHIP_VOP2_CLUSTER1, 824 ROCKCHIP_VOP2_ESMART0, 825 ROCKCHIP_VOP2_ESMART1, 826 ROCKCHIP_VOP2_SMART0, 827 ROCKCHIP_VOP2_SMART1, 828 ROCKCHIP_VOP2_CLUSTER2, 829 ROCKCHIP_VOP2_CLUSTER3, 830 ROCKCHIP_VOP2_ESMART2, 831 ROCKCHIP_VOP2_ESMART3, 832 ROCKCHIP_VOP2_LAYER_MAX, 833 }; 834 835 enum vop2_scale_up_mode { 836 VOP2_SCALE_UP_NRST_NBOR, 837 VOP2_SCALE_UP_BIL, 838 VOP2_SCALE_UP_BIC, 839 }; 840 841 enum vop2_scale_down_mode { 842 VOP2_SCALE_DOWN_NRST_NBOR, 843 VOP2_SCALE_DOWN_BIL, 844 VOP2_SCALE_DOWN_AVG, 845 }; 846 847 enum scale_mode { 848 SCALE_NONE = 0x0, 849 SCALE_UP = 0x1, 850 SCALE_DOWN = 0x2 851 }; 852 853 enum vop_dsc_interface_mode { 854 VOP_DSC_IF_DISABLE = 0, 855 VOP_DSC_IF_HDMI = 1, 856 VOP_DSC_IF_MIPI_DS_MODE = 2, 857 VOP_DSC_IF_MIPI_VIDEO_MODE = 3, 858 }; 859 860 struct vop2_layer { 861 u8 id; 862 /** 863 * @win_phys_id: window id of the layer selected. 864 * Every layer must make sure to select different 865 * windows of others. 866 */ 867 u8 win_phys_id; 868 }; 869 870 struct vop2_power_domain_data { 871 u8 id; 872 u8 parent_id; 873 /* 874 * @module_id_mask: module id of which module this power domain is belongs to. 875 * PD_CLUSTER0,1,2,3 only belongs to CLUSTER0/1/2/3, PD_Esmart0 shared by Esmart1/2/3 876 */ 877 u32 module_id_mask; 878 }; 879 880 struct vop2_win_data { 881 char *name; 882 u8 phys_id; 883 enum vop2_layer_type type; 884 u8 win_sel_port_offset; 885 u8 layer_sel_win_id; 886 u8 axi_id; 887 u8 axi_uv_id; 888 u8 axi_yrgb_id; 889 u8 splice_win_id; 890 u8 pd_id; 891 u32 reg_offset; 892 u32 max_upscale_factor; 893 u32 max_downscale_factor; 894 bool splice_mode_right; 895 }; 896 897 struct vop2_vp_data { 898 u32 feature; 899 u8 pre_scan_max_dly; 900 u8 splice_vp_id; 901 struct vop_rect max_output; 902 u32 max_dclk; 903 }; 904 905 struct vop2_plane_table { 906 enum vop2_layer_phy_id plane_id; 907 enum vop2_layer_type plane_type; 908 }; 909 910 struct vop2_vp_plane_mask { 911 u8 primary_plane_id; /* use this win to show logo */ 912 u8 attached_layers_nr; /* number layers attach to this vp */ 913 u8 attached_layers[VOP2_LAYER_MAX]; /* the layers attached to this vp */ 914 u32 plane_mask; 915 int cursor_plane_id; 916 }; 917 918 struct vop2_dsc_data { 919 u8 id; 920 u8 pd_id; 921 u8 max_slice_num; 922 u8 max_linebuf_depth; /* used to generate the bitstream */ 923 u8 min_bits_per_pixel; /* bit num after encoder compress */ 924 const char *dsc_txp_clk_src_name; 925 const char *dsc_txp_clk_name; 926 const char *dsc_pxl_clk_name; 927 const char *dsc_cds_clk_name; 928 }; 929 930 struct dsc_error_info { 931 u32 dsc_error_val; 932 char dsc_error_info[50]; 933 }; 934 935 struct vop2_data { 936 u32 version; 937 struct vop2_vp_data *vp_data; 938 struct vop2_win_data *win_data; 939 struct vop2_vp_plane_mask *plane_mask; 940 struct vop2_plane_table *plane_table; 941 struct vop2_power_domain_data *pd; 942 struct vop2_dsc_data *dsc; 943 struct dsc_error_info *dsc_error_ecw; 944 struct dsc_error_info *dsc_error_buffer_flow; 945 u8 nr_vps; 946 u8 nr_layers; 947 u8 nr_mixers; 948 u8 nr_gammas; 949 u8 nr_pd; 950 u8 nr_dscs; 951 u8 nr_dsc_ecw; 952 u8 nr_dsc_buffer_flow; 953 u32 reg_len; 954 }; 955 956 struct vop2 { 957 u32 *regsbak; 958 void *regs; 959 void *grf; 960 void *vop_grf; 961 void *vo1_grf; 962 void *sys_pmu; 963 u32 reg_len; 964 u32 version; 965 bool global_init; 966 const struct vop2_data *data; 967 struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX]; 968 }; 969 970 static struct vop2 *rockchip_vop2; 971 /* 972 * bli_sd_factor = (src - 1) / (dst - 1) << 12; 973 * avg_sd_factor: 974 * bli_su_factor: 975 * bic_su_factor: 976 * = (src - 1) / (dst - 1) << 16; 977 * 978 * gt2 enable: dst get one line from two line of the src 979 * gt4 enable: dst get one line from four line of the src. 980 * 981 */ 982 #define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1)) 983 #define VOP2_COMMON_SCL(src, dst) (((src - 1) << 16) / (dst - 1)) 984 985 #define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \ 986 (fac * (dst - 1) >> 12 < (src - 1)) 987 #define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \ 988 (fac * (dst - 1) >> 16 < (src - 1)) 989 990 static uint16_t vop2_scale_factor(enum scale_mode mode, 991 int32_t filter_mode, 992 uint32_t src, uint32_t dst) 993 { 994 uint32_t fac = 0; 995 int i = 0; 996 997 if (mode == SCALE_NONE) 998 return 0; 999 1000 /* 1001 * A workaround to avoid zero div. 1002 */ 1003 if ((dst == 1) || (src == 1)) { 1004 dst = dst + 1; 1005 src = src + 1; 1006 } 1007 1008 if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) { 1009 fac = VOP2_BILI_SCL_DN(src, dst); 1010 for (i = 0; i < 100; i++) { 1011 if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac)) 1012 break; 1013 fac -= 1; 1014 printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1015 } 1016 } else { 1017 fac = VOP2_COMMON_SCL(src, dst); 1018 for (i = 0; i < 100; i++) { 1019 if (VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac)) 1020 break; 1021 fac -= 1; 1022 printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac); 1023 } 1024 } 1025 1026 return fac; 1027 } 1028 1029 static inline enum scale_mode scl_get_scl_mode(int src, int dst) 1030 { 1031 if (src < dst) 1032 return SCALE_UP; 1033 else if (src > dst) 1034 return SCALE_DOWN; 1035 1036 return SCALE_NONE; 1037 } 1038 1039 static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1040 ROCKCHIP_VOP2_ESMART0, 1041 ROCKCHIP_VOP2_ESMART1, 1042 ROCKCHIP_VOP2_ESMART2, 1043 ROCKCHIP_VOP2_ESMART3, 1044 }; 1045 1046 static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = { 1047 ROCKCHIP_VOP2_SMART0, 1048 ROCKCHIP_VOP2_SMART1, 1049 ROCKCHIP_VOP2_ESMART1, 1050 }; 1051 1052 static inline int interpolate(int x1, int y1, int x2, int y2, int x) 1053 { 1054 return y1 + (y2 - y1) * (x - x1) / (x2 - x1); 1055 } 1056 1057 static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask) 1058 { 1059 int i = 0; 1060 u8 *vop2_vp_primary_plane_order; 1061 u8 default_primary_plane; 1062 1063 if (vop2->version == VOP_VERSION_RK3588) { 1064 vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order; 1065 default_primary_plane = ROCKCHIP_VOP2_ESMART0; 1066 } else { 1067 vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order; 1068 default_primary_plane = ROCKCHIP_VOP2_SMART0; 1069 } 1070 1071 for (i = 0; i < vop2->data->nr_vps; i++) { 1072 if (plane_mask & BIT(vop2_vp_primary_plane_order[i])) 1073 return vop2_vp_primary_plane_order[i]; 1074 } 1075 1076 return default_primary_plane; 1077 } 1078 1079 static inline u16 scl_cal_scale(int src, int dst, int shift) 1080 { 1081 return ((src * 2 - 3) << (shift - 1)) / (dst - 1); 1082 } 1083 1084 static inline u16 scl_cal_scale2(int src, int dst) 1085 { 1086 return ((src - 1) << 12) / (dst - 1); 1087 } 1088 1089 static inline void vop2_writel(struct vop2 *vop2, u32 offset, u32 v) 1090 { 1091 writel(v, vop2->regs + offset); 1092 vop2->regsbak[offset >> 2] = v; 1093 } 1094 1095 static inline u32 vop2_readl(struct vop2 *vop2, u32 offset) 1096 { 1097 return readl(vop2->regs + offset); 1098 } 1099 1100 static inline void vop2_mask_write(struct vop2 *vop2, u32 offset, 1101 u32 mask, u32 shift, u32 v, 1102 bool write_mask) 1103 { 1104 if (!mask) 1105 return; 1106 1107 if (write_mask) { 1108 v = ((v & mask) << shift) | (mask << (shift + 16)); 1109 } else { 1110 u32 cached_val = vop2->regsbak[offset >> 2]; 1111 1112 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift); 1113 vop2->regsbak[offset >> 2] = v; 1114 } 1115 1116 writel(v, vop2->regs + offset); 1117 } 1118 1119 static inline void vop2_grf_writel(struct vop2 *vop, void *grf_base, u32 offset, 1120 u32 mask, u32 shift, u32 v) 1121 { 1122 u32 val = 0; 1123 1124 val = (v << shift) | (mask << (shift + 16)); 1125 writel(val, grf_base + offset); 1126 } 1127 1128 static inline u32 vop2_grf_readl(struct vop2 *vop, void *grf_base, u32 offset, 1129 u32 mask, u32 shift) 1130 { 1131 return (readl(grf_base + offset) >> shift) & mask; 1132 } 1133 1134 static char* get_output_if_name(u32 output_if, char *name) 1135 { 1136 if (output_if & VOP_OUTPUT_IF_RGB) 1137 strcat(name, " RGB"); 1138 if (output_if & VOP_OUTPUT_IF_BT1120) 1139 strcat(name, " BT1120"); 1140 if (output_if & VOP_OUTPUT_IF_BT656) 1141 strcat(name, " BT656"); 1142 if (output_if & VOP_OUTPUT_IF_LVDS0) 1143 strcat(name, " LVDS0"); 1144 if (output_if & VOP_OUTPUT_IF_LVDS1) 1145 strcat(name, " LVDS1"); 1146 if (output_if & VOP_OUTPUT_IF_MIPI0) 1147 strcat(name, " MIPI0"); 1148 if (output_if & VOP_OUTPUT_IF_MIPI1) 1149 strcat(name, " MIPI1"); 1150 if (output_if & VOP_OUTPUT_IF_eDP0) 1151 strcat(name, " eDP0"); 1152 if (output_if & VOP_OUTPUT_IF_eDP1) 1153 strcat(name, " eDP1"); 1154 if (output_if & VOP_OUTPUT_IF_DP0) 1155 strcat(name, " DP0"); 1156 if (output_if & VOP_OUTPUT_IF_DP1) 1157 strcat(name, " DP1"); 1158 if (output_if & VOP_OUTPUT_IF_HDMI0) 1159 strcat(name, " HDMI0"); 1160 if (output_if & VOP_OUTPUT_IF_HDMI1) 1161 strcat(name, " HDMI1"); 1162 1163 return name; 1164 } 1165 1166 static char *get_plane_name(int plane_id, char *name) 1167 { 1168 switch (plane_id) { 1169 case ROCKCHIP_VOP2_CLUSTER0: 1170 strcat(name, "Cluster0"); 1171 break; 1172 case ROCKCHIP_VOP2_CLUSTER1: 1173 strcat(name, "Cluster1"); 1174 break; 1175 case ROCKCHIP_VOP2_ESMART0: 1176 strcat(name, "Esmart0"); 1177 break; 1178 case ROCKCHIP_VOP2_ESMART1: 1179 strcat(name, "Esmart1"); 1180 break; 1181 case ROCKCHIP_VOP2_SMART0: 1182 strcat(name, "Smart0"); 1183 break; 1184 case ROCKCHIP_VOP2_SMART1: 1185 strcat(name, "Smart1"); 1186 break; 1187 case ROCKCHIP_VOP2_CLUSTER2: 1188 strcat(name, "Cluster2"); 1189 break; 1190 case ROCKCHIP_VOP2_CLUSTER3: 1191 strcat(name, "Cluster3"); 1192 break; 1193 case ROCKCHIP_VOP2_ESMART2: 1194 strcat(name, "Esmart2"); 1195 break; 1196 case ROCKCHIP_VOP2_ESMART3: 1197 strcat(name, "Esmart3"); 1198 break; 1199 } 1200 1201 return name; 1202 } 1203 1204 static bool is_yuv_output(u32 bus_format) 1205 { 1206 switch (bus_format) { 1207 case MEDIA_BUS_FMT_YUV8_1X24: 1208 case MEDIA_BUS_FMT_YUV10_1X30: 1209 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1210 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1211 case MEDIA_BUS_FMT_YUYV8_2X8: 1212 case MEDIA_BUS_FMT_YVYU8_2X8: 1213 case MEDIA_BUS_FMT_UYVY8_2X8: 1214 case MEDIA_BUS_FMT_VYUY8_2X8: 1215 case MEDIA_BUS_FMT_YUYV8_1X16: 1216 case MEDIA_BUS_FMT_YVYU8_1X16: 1217 case MEDIA_BUS_FMT_UYVY8_1X16: 1218 case MEDIA_BUS_FMT_VYUY8_1X16: 1219 return true; 1220 default: 1221 return false; 1222 } 1223 } 1224 1225 static int vop2_convert_csc_mode(int csc_mode) 1226 { 1227 switch (csc_mode) { 1228 case V4L2_COLORSPACE_SMPTE170M: 1229 case V4L2_COLORSPACE_470_SYSTEM_M: 1230 case V4L2_COLORSPACE_470_SYSTEM_BG: 1231 return CSC_BT601L; 1232 case V4L2_COLORSPACE_REC709: 1233 case V4L2_COLORSPACE_SMPTE240M: 1234 case V4L2_COLORSPACE_DEFAULT: 1235 return CSC_BT709L; 1236 case V4L2_COLORSPACE_JPEG: 1237 return CSC_BT601F; 1238 case V4L2_COLORSPACE_BT2020: 1239 return CSC_BT2020; 1240 default: 1241 return CSC_BT709L; 1242 } 1243 } 1244 1245 static bool is_uv_swap(u32 bus_format, u32 output_mode) 1246 { 1247 /* 1248 * FIXME: 1249 * 1250 * There is no media type for YUV444 output, 1251 * so when out_mode is AAAA or P888, assume output is YUV444 on 1252 * yuv format. 1253 * 1254 * From H/W testing, YUV444 mode need a rb swap. 1255 */ 1256 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 || 1257 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 || 1258 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 || 1259 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 || 1260 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 1261 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 1262 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 1263 output_mode == ROCKCHIP_OUT_MODE_P888))) 1264 return true; 1265 else 1266 return false; 1267 } 1268 1269 static inline bool is_hot_plug_devices(int output_type) 1270 { 1271 switch (output_type) { 1272 case DRM_MODE_CONNECTOR_HDMIA: 1273 case DRM_MODE_CONNECTOR_HDMIB: 1274 case DRM_MODE_CONNECTOR_TV: 1275 case DRM_MODE_CONNECTOR_DisplayPort: 1276 case DRM_MODE_CONNECTOR_VGA: 1277 case DRM_MODE_CONNECTOR_Unknown: 1278 return true; 1279 default: 1280 return false; 1281 } 1282 } 1283 1284 static struct vop2_win_data *vop2_find_win_by_phys_id(struct vop2 *vop2, int phys_id) 1285 { 1286 int i = 0; 1287 1288 for (i = 0; i < vop2->data->nr_layers; i++) { 1289 if (vop2->data->win_data[i].phys_id == phys_id) 1290 return &vop2->data->win_data[i]; 1291 } 1292 1293 return NULL; 1294 } 1295 1296 static struct vop2_power_domain_data *vop2_find_pd_data_by_id(struct vop2 *vop2, int pd_id) 1297 { 1298 int i = 0; 1299 1300 for (i = 0; i < vop2->data->nr_pd; i++) { 1301 if (vop2->data->pd[i].id == pd_id) 1302 return &vop2->data->pd[i]; 1303 } 1304 1305 return NULL; 1306 } 1307 1308 static int rockchip_vop2_gamma_lut_init(struct vop2 *vop2, 1309 struct display_state *state) 1310 { 1311 struct connector_state *conn_state = &state->conn_state; 1312 struct crtc_state *cstate = &state->crtc_state; 1313 struct resource gamma_res; 1314 fdt_size_t lut_size; 1315 int i, lut_len, ret = 0; 1316 u32 *lut_regs; 1317 u32 *lut_val; 1318 u32 r, g, b; 1319 u32 vp_offset = cstate->crtc_id * 0x100; 1320 struct base2_disp_info *disp_info = conn_state->disp_info; 1321 static int gamma_lut_en_num = 1; 1322 1323 if (gamma_lut_en_num > vop2->data->nr_gammas) { 1324 printf("warn: only %d vp support gamma\n", vop2->data->nr_gammas); 1325 return 0; 1326 } 1327 1328 if (!disp_info) 1329 return 0; 1330 1331 if (!disp_info->gamma_lut_data.size) 1332 return 0; 1333 1334 ret = ofnode_read_resource_byname(cstate->node, "gamma_lut", &gamma_res); 1335 if (ret) 1336 printf("failed to get gamma lut res\n"); 1337 lut_regs = (u32 *)gamma_res.start; 1338 lut_size = gamma_res.end - gamma_res.start + 1; 1339 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 1340 printf("failed to get gamma lut register\n"); 1341 return 0; 1342 } 1343 lut_len = lut_size / 4; 1344 if (lut_len != 256 && lut_len != 1024) { 1345 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 1346 return 0; 1347 } 1348 lut_val = (u32 *)calloc(1, lut_size); 1349 for (i = 0; i < lut_len; i++) { 1350 r = disp_info->gamma_lut_data.lred[i] * (lut_len - 1) / 0xffff; 1351 g = disp_info->gamma_lut_data.lgreen[i] * (lut_len - 1) / 0xffff; 1352 b = disp_info->gamma_lut_data.lblue[i] * (lut_len - 1) / 0xffff; 1353 1354 lut_val[i] = b * lut_len * lut_len + g * lut_len + r; 1355 } 1356 1357 for (i = 0; i < lut_len; i++) 1358 writel(lut_val[i], lut_regs + i); 1359 1360 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, 1361 GAMMA_PORT_SEL_MASK, GAMMA_PORT_SEL_SHIFT, 1362 cstate->crtc_id , false); 1363 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 1364 EN_MASK, DSP_LUT_EN_SHIFT, 1, false); 1365 gamma_lut_en_num++; 1366 1367 return 0; 1368 } 1369 1370 static int rockchip_vop2_cubic_lut_init(struct vop2 *vop2, 1371 struct display_state *state) 1372 { 1373 struct connector_state *conn_state = &state->conn_state; 1374 struct crtc_state *cstate = &state->crtc_state; 1375 int i, cubic_lut_len; 1376 u32 vp_offset = cstate->crtc_id * 0x100; 1377 struct base2_disp_info *disp_info = conn_state->disp_info; 1378 struct base2_cubic_lut_data *lut = &conn_state->disp_info->cubic_lut_data; 1379 u32 *cubic_lut_addr; 1380 1381 if (!disp_info || CONFIG_ROCKCHIP_CUBIC_LUT_SIZE == 0) 1382 return 0; 1383 1384 if (!disp_info->cubic_lut_data.size) 1385 return 0; 1386 1387 cubic_lut_addr = (u32 *)get_cubic_lut_buffer(cstate->crtc_id); 1388 cubic_lut_len = disp_info->cubic_lut_data.size; 1389 1390 for (i = 0; i < cubic_lut_len / 2; i++) { 1391 *cubic_lut_addr++ = ((lut->lred[2 * i]) & 0xfff) + 1392 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1393 ((lut->lblue[2 * i] & 0xff) << 24); 1394 *cubic_lut_addr++ = ((lut->lblue[2 * i] & 0xf00) >> 8) + 1395 ((lut->lred[2 * i + 1] & 0xfff) << 4) + 1396 ((lut->lgreen[2 * i + 1] & 0xfff) << 16) + 1397 ((lut->lblue[2 * i + 1] & 0xf) << 28); 1398 *cubic_lut_addr++ = (lut->lblue[2 * i + 1] & 0xff0) >> 4; 1399 *cubic_lut_addr++ = 0; 1400 } 1401 1402 if (cubic_lut_len % 2) { 1403 *cubic_lut_addr++ = (lut->lred[2 * i] & 0xfff) + 1404 ((lut->lgreen[2 * i] & 0xfff) << 12) + 1405 ((lut->lblue[2 * i] & 0xff) << 24); 1406 *cubic_lut_addr++ = (lut->lblue[2 * i] & 0xf00) >> 8; 1407 *cubic_lut_addr++ = 0; 1408 *cubic_lut_addr = 0; 1409 } 1410 1411 vop2_writel(vop2, RK3568_VP0_3D_LUT_MST + vp_offset, 1412 get_cubic_lut_buffer(cstate->crtc_id)); 1413 vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, 1414 EN_MASK, LUT_DMA_EN_SHIFT, 1, false); 1415 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1416 EN_MASK, VP0_3D_LUT_EN_SHIFT, 1, false); 1417 vop2_mask_write(vop2, RK3568_VP0_3D_LUT_CTRL + vp_offset, 1418 EN_MASK, VP0_3D_LUT_UPDATE_SHIFT, 1, false); 1419 1420 return 0; 1421 } 1422 1423 static void vop2_bcsh_reg_update(struct display_state *state, struct vop2 *vop2, 1424 struct bcsh_state *bcsh_state, int crtc_id) 1425 { 1426 struct crtc_state *cstate = &state->crtc_state; 1427 u32 vp_offset = crtc_id * 0x100; 1428 1429 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_MASK, 1430 BCSH_CTRL_R2Y_SHIFT, cstate->post_r2y_en, false); 1431 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_MASK, 1432 BCSH_CTRL_Y2R_SHIFT, cstate->post_y2r_en, false); 1433 1434 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_R2Y_CSC_MODE_MASK, 1435 BCSH_CTRL_R2Y_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1436 vop2_mask_write(vop2, RK3568_VP0_BCSH_CTRL + vp_offset, BCSH_CTRL_Y2R_CSC_MODE_MASK, 1437 BCSH_CTRL_Y2R_CSC_MODE_SHIFT, cstate->post_csc_mode, false); 1438 1439 if (!cstate->bcsh_en) { 1440 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1441 BCSH_EN_MASK, BCSH_EN_SHIFT, 0, false); 1442 return; 1443 } 1444 1445 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1446 BCSH_BRIGHTNESS_MASK, BCSH_BRIGHTNESS_SHIFT, 1447 bcsh_state->brightness, false); 1448 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1449 BCSH_CONTRAST_MASK, BCSH_CONTRAST_SHIFT, bcsh_state->contrast, false); 1450 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1451 BCSH_SATURATION_MASK, BCSH_SATURATION_SHIFT, 1452 bcsh_state->saturation * bcsh_state->contrast / 0x100, false); 1453 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1454 BCSH_SIN_HUE_MASK, BCSH_SIN_HUE_SHIFT, bcsh_state->sin_hue, false); 1455 vop2_mask_write(vop2, RK3568_VP0_BCSH_H + vp_offset, 1456 BCSH_COS_HUE_MASK, BCSH_COS_HUE_SHIFT, bcsh_state->cos_hue, false); 1457 vop2_mask_write(vop2, RK3568_VP0_BCSH_BCS + vp_offset, 1458 BCSH_OUT_MODE_MASK, BCSH_OUT_MODE_SHIFT, 1459 BCSH_OUT_MODE_NORMAL_VIDEO, false); 1460 vop2_mask_write(vop2, RK3568_VP0_BCSH_COLOR + vp_offset, 1461 BCSH_EN_MASK, BCSH_EN_SHIFT, 1, false); 1462 } 1463 1464 static void vop2_tv_config_update(struct display_state *state, struct vop2 *vop2) 1465 { 1466 struct connector_state *conn_state = &state->conn_state; 1467 struct base_bcsh_info *bcsh_info; 1468 struct crtc_state *cstate = &state->crtc_state; 1469 struct bcsh_state bcsh_state; 1470 int brightness, contrast, saturation, hue, sin_hue, cos_hue; 1471 1472 if (!conn_state->disp_info) 1473 return; 1474 bcsh_info = &conn_state->disp_info->bcsh_info; 1475 if (!bcsh_info) 1476 return; 1477 1478 if (bcsh_info->brightness != 50 || 1479 bcsh_info->contrast != 50 || 1480 bcsh_info->saturation != 50 || bcsh_info->hue != 50) 1481 cstate->bcsh_en = true; 1482 1483 if (cstate->bcsh_en) { 1484 if (!cstate->yuv_overlay) 1485 cstate->post_r2y_en = 1; 1486 if (!is_yuv_output(conn_state->bus_format)) 1487 cstate->post_y2r_en = 1; 1488 } else { 1489 if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format)) 1490 cstate->post_r2y_en = 1; 1491 if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format)) 1492 cstate->post_y2r_en = 1; 1493 } 1494 1495 cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space); 1496 1497 if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT) 1498 brightness = interpolate(0, -128, 100, 127, 1499 bcsh_info->brightness); 1500 else 1501 brightness = interpolate(0, -32, 100, 31, 1502 bcsh_info->brightness); 1503 contrast = interpolate(0, 0, 100, 511, bcsh_info->contrast); 1504 saturation = interpolate(0, 0, 100, 511, bcsh_info->saturation); 1505 hue = interpolate(0, -30, 100, 30, bcsh_info->hue); 1506 1507 1508 /* 1509 * a:[-30~0): 1510 * sin_hue = 0x100 - sin(a)*256; 1511 * cos_hue = cos(a)*256; 1512 * a:[0~30] 1513 * sin_hue = sin(a)*256; 1514 * cos_hue = cos(a)*256; 1515 */ 1516 sin_hue = fixp_sin32(hue) >> 23; 1517 cos_hue = fixp_cos32(hue) >> 23; 1518 1519 bcsh_state.brightness = brightness; 1520 bcsh_state.contrast = contrast; 1521 bcsh_state.saturation = saturation; 1522 bcsh_state.sin_hue = sin_hue; 1523 bcsh_state.cos_hue = cos_hue; 1524 1525 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->crtc_id); 1526 if (cstate->splice_mode) 1527 vop2_bcsh_reg_update(state, vop2, &bcsh_state, cstate->splice_crtc_id); 1528 } 1529 1530 static void vop2_setup_dly_for_vp(struct display_state *state, struct vop2 *vop2, int crtc_id) 1531 { 1532 struct connector_state *conn_state = &state->conn_state; 1533 struct drm_display_mode *mode = &conn_state->mode; 1534 struct crtc_state *cstate = &state->crtc_state; 1535 u32 bg_ovl_dly, bg_dly, pre_scan_dly; 1536 u16 hdisplay = mode->crtc_hdisplay; 1537 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 1538 1539 bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly; 1540 bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly; 1541 bg_dly -= bg_ovl_dly; 1542 1543 if (cstate->splice_mode) 1544 pre_scan_dly = bg_dly + (hdisplay >> 2) - 1; 1545 else 1546 pre_scan_dly = bg_dly + (hdisplay >> 1) - 1; 1547 1548 if (vop2->version == VOP_VERSION_RK3588 && hsync_len < 8) 1549 hsync_len = 8; 1550 pre_scan_dly = (pre_scan_dly << 16) | hsync_len; 1551 vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4, 1552 BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false); 1553 vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly); 1554 } 1555 1556 static void vop2_post_config(struct display_state *state, struct vop2 *vop2) 1557 { 1558 struct connector_state *conn_state = &state->conn_state; 1559 struct drm_display_mode *mode = &conn_state->mode; 1560 struct crtc_state *cstate = &state->crtc_state; 1561 u32 vp_offset = (cstate->crtc_id * 0x100); 1562 u16 vtotal = mode->crtc_vtotal; 1563 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 1564 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 1565 u16 hdisplay = mode->crtc_hdisplay; 1566 u16 vdisplay = mode->crtc_vdisplay; 1567 u16 hsize = 1568 hdisplay * (conn_state->overscan.left_margin + 1569 conn_state->overscan.right_margin) / 200; 1570 u16 vsize = 1571 vdisplay * (conn_state->overscan.top_margin + 1572 conn_state->overscan.bottom_margin) / 200; 1573 u16 hact_end, vact_end; 1574 u32 val; 1575 1576 hsize = round_down(hsize, 2); 1577 vsize = round_down(vsize, 2); 1578 1579 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 1580 hact_end = hact_st + hsize; 1581 val = hact_st << 16; 1582 val |= hact_end; 1583 1584 vop2_writel(vop2, RK3568_VP0_POST_DSP_HACT_INFO + vp_offset, val); 1585 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 1586 vact_end = vact_st + vsize; 1587 val = vact_st << 16; 1588 val |= vact_end; 1589 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO + vp_offset, val); 1590 val = scl_cal_scale2(vdisplay, vsize) << 16; 1591 val |= scl_cal_scale2(hdisplay, hsize); 1592 vop2_writel(vop2, RK3568_VP0_POST_SCL_FACTOR_YRGB + vp_offset, val); 1593 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 1594 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 1595 vop2_writel(vop2, RK3568_VP0_POST_SCL_CTRL + vp_offset, 1596 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 1597 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 1598 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1599 u16 vact_st_f1 = vtotal + vact_st + 1; 1600 u16 vact_end_f1 = vact_st_f1 + vsize; 1601 1602 val = vact_st_f1 << 16 | vact_end_f1; 1603 vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val); 1604 } 1605 1606 vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id); 1607 if (cstate->splice_mode) 1608 vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id); 1609 } 1610 1611 /* 1612 * Read VOP internal power domain on/off status. 1613 * We should query BISR_STS register in PMU for 1614 * power up/down status when memory repair is enabled. 1615 * Return value: 1 for power on, 0 for power off; 1616 */ 1617 static int vop2_wait_power_domain_on(struct vop2 *vop2, struct vop2_power_domain_data *pd_data) 1618 { 1619 int val = 0; 1620 int shift = 0; 1621 int shift_factor = 0; 1622 bool is_bisr_en = false; 1623 1624 /* 1625 * The order of pd status bits in BISR_STS register 1626 * is different from that in VOP SYS_STS register. 1627 */ 1628 if (pd_data->id == VOP2_PD_DSC_8K || 1629 pd_data->id == VOP2_PD_DSC_4K || 1630 pd_data->id == VOP2_PD_ESMART) 1631 shift_factor = 1; 1632 1633 shift = RK3588_PD_CLUSTER0_REPAIR_EN_SHIFT + generic_ffs(pd_data->id) - 1 - shift_factor; 1634 is_bisr_en = vop2_grf_readl(vop2, vop2->sys_pmu, RK3588_PMU_BISR_CON3, EN_MASK, shift); 1635 if (is_bisr_en) { 1636 shift = RK3588_PD_CLUSTER0_PWR_STAT_SHIFI + generic_ffs(pd_data->id) - 1 - shift_factor; 1637 1638 return readl_poll_timeout(vop2->sys_pmu + RK3588_PMU_BISR_STATUS5, val, 1639 ((val >> shift) & 0x1), 50 * 1000); 1640 } else { 1641 shift = RK3588_CLUSTER0_PD_STATUS_SHIFT + generic_ffs(pd_data->id) - 1; 1642 1643 return readl_poll_timeout(vop2->regs + RK3568_SYS_STATUS0, val, 1644 !((val >> shift) & 0x1), 50 * 1000); 1645 } 1646 } 1647 1648 static int vop2_power_domain_on(struct vop2 *vop2, int pd_id) 1649 { 1650 struct vop2_power_domain_data *pd_data; 1651 int ret = 0; 1652 1653 if (!pd_id) 1654 return 0; 1655 1656 pd_data = vop2_find_pd_data_by_id(vop2, pd_id); 1657 if (!pd_data) { 1658 printf("can't find pd_data by id\n"); 1659 return -EINVAL; 1660 } 1661 1662 if (pd_data->parent_id) { 1663 ret = vop2_power_domain_on(vop2, pd_data->parent_id); 1664 if (ret) { 1665 printf("can't open parent power domain\n"); 1666 return -EINVAL; 1667 } 1668 } 1669 1670 vop2_mask_write(vop2, RK3568_SYS_PD_CTRL, EN_MASK, 1671 RK3588_CLUSTER0_PD_EN_SHIFT + generic_ffs(pd_id) - 1, 0, false); 1672 ret = vop2_wait_power_domain_on(vop2, pd_data); 1673 if (ret) { 1674 printf("wait vop2 power domain timeout\n"); 1675 return ret; 1676 } 1677 1678 return 0; 1679 } 1680 1681 static void rk3588_vop2_regsbak(struct vop2 *vop2) 1682 { 1683 u32 *base = vop2->regs; 1684 int i = 0; 1685 1686 /* 1687 * No need to backup HDR/DSC/GAMMA_LUT/BPP_LUT/MMU 1688 */ 1689 for (i = 0; i < (vop2->reg_len >> 2); i++) 1690 vop2->regsbak[i] = base[i]; 1691 } 1692 1693 static void vop2_global_initial(struct vop2 *vop2, struct display_state *state) 1694 { 1695 struct crtc_state *cstate = &state->crtc_state; 1696 int i, j, port_mux = 0, total_used_layer = 0; 1697 u8 shift = 0; 1698 int layer_phy_id = 0; 1699 u32 layer_nr = 0; 1700 struct vop2_win_data *win_data; 1701 struct vop2_vp_plane_mask *plane_mask; 1702 1703 if (vop2->global_init) 1704 return; 1705 1706 /* OTP must enable at the first time, otherwise mirror layer register is error */ 1707 if (soc_is_rk3566()) 1708 vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK, 1709 OTP_WIN_EN_SHIFT, 1, false); 1710 1711 if (cstate->crtc->assign_plane) {/* dts assign plane */ 1712 u32 plane_mask; 1713 int primary_plane_id; 1714 1715 for (i = 0; i < vop2->data->nr_vps; i++) { 1716 plane_mask = cstate->crtc->vps[i].plane_mask; 1717 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1718 layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */ 1719 vop2->vp_plane_mask[i].attached_layers_nr = layer_nr; 1720 primary_plane_id = cstate->crtc->vps[i].primary_plane_id; 1721 if (primary_plane_id < 0) 1722 primary_plane_id = vop2_get_primary_plane(vop2, plane_mask); 1723 vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id; 1724 vop2->vp_plane_mask[i].plane_mask = plane_mask; 1725 1726 /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/ 1727 for (j = 0; j < layer_nr; j++) { 1728 vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1; 1729 plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]); 1730 } 1731 } 1732 } else {/* need soft assign plane mask */ 1733 /* find the first unplug devices and set it as main display */ 1734 int main_vp_index = -1; 1735 int active_vp_num = 0; 1736 1737 for (i = 0; i < vop2->data->nr_vps; i++) { 1738 if (cstate->crtc->vps[i].enable) 1739 active_vp_num++; 1740 } 1741 printf("VOP have %d active VP\n", active_vp_num); 1742 1743 if (soc_is_rk3566() && active_vp_num > 2) 1744 printf("ERROR: rk3566 only support 2 display output!!\n"); 1745 plane_mask = vop2->data->plane_mask; 1746 plane_mask += (active_vp_num - 1) * VOP2_VP_MAX; 1747 1748 for (i = 0; i < vop2->data->nr_vps; i++) { 1749 if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) { 1750 vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/ 1751 main_vp_index = i; 1752 break; 1753 } 1754 } 1755 1756 /* if no find unplug devices, use vp0 as main display */ 1757 if (main_vp_index < 0) { 1758 main_vp_index = 0; 1759 vop2->vp_plane_mask[0] = plane_mask[0]; 1760 } 1761 1762 j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */ 1763 1764 /* init other display except main display */ 1765 for (i = 0; i < vop2->data->nr_vps; i++) { 1766 if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */ 1767 continue; 1768 vop2->vp_plane_mask[i] = plane_mask[j++]; 1769 } 1770 1771 /* store plane mask for vop2_fixup_dts */ 1772 for (i = 0; i < vop2->data->nr_vps; i++) { 1773 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1774 for (j = 0; j < layer_nr; j++) { 1775 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1776 vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id); 1777 } 1778 } 1779 } 1780 1781 if (vop2->version == VOP_VERSION_RK3588) 1782 rk3588_vop2_regsbak(vop2); 1783 else 1784 memcpy(vop2->regsbak, vop2->regs, vop2->reg_len); 1785 1786 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, 1787 OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false); 1788 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 1789 IF_CTRL_REG_DONE_IMD_SHIFT, 1, false); 1790 1791 for (i = 0; i < vop2->data->nr_vps; i++) { 1792 printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr); 1793 for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++) 1794 printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]); 1795 printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id); 1796 } 1797 1798 shift = 0; 1799 /* layer sel win id */ 1800 for (i = 0; i < vop2->data->nr_vps; i++) { 1801 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1802 for (j = 0; j < layer_nr; j++) { 1803 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1804 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1805 vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK, 1806 shift, win_data->layer_sel_win_id, false); 1807 shift += 4; 1808 } 1809 } 1810 1811 /* win sel port */ 1812 for (i = 0; i < vop2->data->nr_vps; i++) { 1813 layer_nr = vop2->vp_plane_mask[i].attached_layers_nr; 1814 for (j = 0; j < layer_nr; j++) { 1815 if (!vop2->vp_plane_mask[i].attached_layers[j]) 1816 continue; 1817 layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j]; 1818 win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id); 1819 shift = win_data->win_sel_port_offset * 2; 1820 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, LAYER_SEL_PORT_MASK, 1821 LAYER_SEL_PORT_SHIFT + shift, i, false); 1822 } 1823 } 1824 1825 /** 1826 * port mux config 1827 */ 1828 for (i = 0; i < vop2->data->nr_vps; i++) { 1829 shift = i * 4; 1830 if (vop2->vp_plane_mask[i].attached_layers_nr) { 1831 total_used_layer += vop2->vp_plane_mask[i].attached_layers_nr; 1832 port_mux = total_used_layer - 1; 1833 } else { 1834 port_mux = 8; 1835 } 1836 1837 if (i == vop2->data->nr_vps - 1) 1838 port_mux = vop2->data->nr_mixers; 1839 1840 cstate->crtc->vps[i].bg_ovl_dly = (vop2->data->nr_mixers - port_mux) << 1; 1841 vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK, 1842 PORT_MUX_SHIFT + shift, port_mux, false); 1843 } 1844 1845 if (vop2->version == VOP_VERSION_RK3568) 1846 vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0); 1847 1848 vop2->global_init = true; 1849 } 1850 1851 static int vop2_initial(struct vop2 *vop2, struct display_state *state) 1852 { 1853 struct crtc_state *cstate = &state->crtc_state; 1854 int ret; 1855 1856 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 1857 ret = clk_set_defaults(cstate->dev); 1858 if (ret) 1859 debug("%s clk_set_defaults failed %d\n", __func__, ret); 1860 1861 rockchip_vop2_gamma_lut_init(vop2, state); 1862 rockchip_vop2_cubic_lut_init(vop2, state); 1863 1864 return 0; 1865 } 1866 1867 /* 1868 * VOP2 have multi video ports. 1869 * video port ------- crtc 1870 */ 1871 static int rockchip_vop2_preinit(struct display_state *state) 1872 { 1873 struct crtc_state *cstate = &state->crtc_state; 1874 const struct vop2_data *vop2_data = cstate->crtc->data; 1875 1876 if (!rockchip_vop2) { 1877 rockchip_vop2 = calloc(1, sizeof(struct vop2)); 1878 if (!rockchip_vop2) 1879 return -ENOMEM; 1880 rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev); 1881 rockchip_vop2->regsbak = malloc(RK3568_MAX_REG); 1882 rockchip_vop2->reg_len = RK3568_MAX_REG; 1883 rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 1884 if (rockchip_vop2->grf <= 0) 1885 printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf); 1886 rockchip_vop2->version = vop2_data->version; 1887 rockchip_vop2->data = vop2_data; 1888 if (rockchip_vop2->version == VOP_VERSION_RK3588) { 1889 struct regmap *map; 1890 1891 rockchip_vop2->vop_grf = syscon_get_first_range(ROCKCHIP_SYSCON_VOP_GRF); 1892 if (rockchip_vop2->vop_grf <= 0) 1893 printf("%s: Get syscon vop_grf failed (ret=%p)\n", __func__, rockchip_vop2->vop_grf); 1894 map = syscon_regmap_lookup_by_phandle(cstate->dev, "rockchip,vo1-grf"); 1895 rockchip_vop2->vo1_grf = regmap_get_range(map, 0); 1896 if (rockchip_vop2->vo1_grf <= 0) 1897 printf("%s: Get syscon vo1_grf failed (ret=%p)\n", __func__, rockchip_vop2->vo1_grf); 1898 rockchip_vop2->sys_pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); 1899 if (rockchip_vop2->sys_pmu <= 0) 1900 printf("%s: Get syscon sys_pmu failed (ret=%p)\n", __func__, rockchip_vop2->sys_pmu); 1901 } 1902 } 1903 1904 cstate->private = rockchip_vop2; 1905 cstate->max_output = vop2_data->vp_data[cstate->crtc_id].max_output; 1906 cstate->feature = vop2_data->vp_data[cstate->crtc_id].feature; 1907 1908 vop2_global_initial(rockchip_vop2, state); 1909 1910 return 0; 1911 } 1912 1913 /* 1914 * calc the dclk on rk3588 1915 * the available div of dclk is 1, 2, 4 1916 * 1917 */ 1918 static unsigned long vop2_calc_dclk(unsigned long child_clk, unsigned long max_dclk) 1919 { 1920 if (child_clk * 4 <= max_dclk) 1921 return child_clk * 4; 1922 else if (child_clk * 2 <= max_dclk) 1923 return child_clk * 2; 1924 else if (child_clk <= max_dclk) 1925 return child_clk; 1926 else 1927 return 0; 1928 } 1929 1930 /* 1931 * 4 pixclk/cycle on rk3588 1932 * RGB/eDP/HDMI: if_pixclk >= dclk_core 1933 * DP: dp_pixclk = dclk_out <= dclk_core 1934 * DSI: mipi_pixclk <= dclk_out <= dclk_core 1935 */ 1936 static unsigned long vop2_calc_cru_cfg(struct display_state *state, 1937 int *dclk_core_div, int *dclk_out_div, 1938 int *if_pixclk_div, int *if_dclk_div) 1939 { 1940 struct crtc_state *cstate = &state->crtc_state; 1941 struct connector_state *conn_state = &state->conn_state; 1942 struct drm_display_mode *mode = &conn_state->mode; 1943 struct vop2 *vop2 = cstate->private; 1944 unsigned long v_pixclk = mode->crtc_clock; 1945 unsigned long dclk_core_rate = v_pixclk >> 2; 1946 unsigned long dclk_rate = v_pixclk; 1947 unsigned long dclk_out_rate; 1948 u64 if_dclk_rate; 1949 u64 if_pixclk_rate; 1950 int output_type = conn_state->type; 1951 int output_mode = conn_state->output_mode; 1952 int K = 1; 1953 1954 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE && 1955 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1956 printf("Dual channel and YUV420 can't work together\n"); 1957 return -EINVAL; 1958 } 1959 1960 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1961 output_mode == ROCKCHIP_OUT_MODE_YUV420) 1962 K = 2; 1963 1964 if (output_type == DRM_MODE_CONNECTOR_HDMIA) { 1965 /* 1966 * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate 1967 * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate 1968 */ 1969 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE || 1970 output_mode == ROCKCHIP_OUT_MODE_YUV420) { 1971 dclk_rate = dclk_rate >> 1; 1972 K = 2; 1973 } 1974 if (cstate->dsc_enable) { 1975 if_pixclk_rate = cstate->dsc_cds_clk_rate << 1; 1976 if_dclk_rate = cstate->dsc_cds_clk_rate; 1977 } else { 1978 if_pixclk_rate = (dclk_core_rate << 1) / K; 1979 if_dclk_rate = dclk_core_rate / K; 1980 } 1981 1982 if (v_pixclk > VOP2_MAX_DCLK_RATE) 1983 dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk); 1984 1985 if (!dclk_rate) { 1986 printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n", 1987 vop2->data->vp_data->max_dclk, if_pixclk_rate); 1988 return -EINVAL; 1989 } 1990 *if_pixclk_div = dclk_rate / if_pixclk_rate; 1991 *if_dclk_div = dclk_rate / if_dclk_rate; 1992 *dclk_core_div = dclk_rate / dclk_core_rate; 1993 printf("dclk:%lu,if_pixclk_div;%d,if_dclk_div:%d\n", 1994 dclk_rate, *if_pixclk_div, *if_dclk_div); 1995 } else if (output_type == DRM_MODE_CONNECTOR_eDP) { 1996 /* edp_pixclk = edp_dclk > dclk_core */ 1997 if_pixclk_rate = v_pixclk / K; 1998 if_dclk_rate = v_pixclk / K; 1999 dclk_rate = if_pixclk_rate * K; 2000 *dclk_core_div = dclk_rate / dclk_core_rate; 2001 *if_pixclk_div = dclk_rate / if_pixclk_rate; 2002 *if_dclk_div = *if_pixclk_div; 2003 } else if (output_type == DRM_MODE_CONNECTOR_DisplayPort) { 2004 dclk_out_rate = v_pixclk >> 2; 2005 dclk_out_rate = dclk_out_rate / K; 2006 2007 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2008 if (!dclk_rate) { 2009 printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n", 2010 vop2->data->vp_data->max_dclk, dclk_core_rate); 2011 return -EINVAL; 2012 } 2013 *dclk_out_div = dclk_rate / dclk_out_rate; 2014 *dclk_core_div = dclk_rate / dclk_core_rate; 2015 } else if (output_type == DRM_MODE_CONNECTOR_DSI) { 2016 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2017 K = 2; 2018 if (cstate->dsc_enable) 2019 /* dsc output is 96bit, dsi input is 192 bit */ 2020 if_pixclk_rate = cstate->dsc_cds_clk_rate >> 1; 2021 else 2022 if_pixclk_rate = dclk_core_rate / K; 2023 /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */ 2024 dclk_out_rate = dclk_core_rate / K; 2025 /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */ 2026 dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk); 2027 if (!dclk_rate) { 2028 printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n", 2029 vop2->data->vp_data->max_dclk, dclk_rate); 2030 return -EINVAL; 2031 } 2032 2033 if (cstate->dsc_enable) 2034 dclk_rate = dclk_rate >> 1; 2035 2036 *dclk_out_div = dclk_rate / dclk_out_rate; 2037 *dclk_core_div = dclk_rate / dclk_core_rate; 2038 *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/ 2039 if (cstate->dsc_enable) 2040 *if_pixclk_div = dclk_out_rate / if_pixclk_rate; 2041 2042 } else if (output_type == DRM_MODE_CONNECTOR_DPI) { 2043 dclk_rate = v_pixclk; 2044 *dclk_core_div = dclk_rate / dclk_core_rate; 2045 } 2046 2047 *if_pixclk_div = ilog2(*if_pixclk_div); 2048 *if_dclk_div = ilog2(*if_dclk_div); 2049 *dclk_core_div = ilog2(*dclk_core_div); 2050 *dclk_out_div = ilog2(*dclk_out_div); 2051 2052 return dclk_rate; 2053 } 2054 2055 static int vop2_calc_dsc_clk(struct display_state *state) 2056 { 2057 struct connector_state *conn_state = &state->conn_state; 2058 struct drm_display_mode *mode = &conn_state->mode; 2059 struct crtc_state *cstate = &state->crtc_state; 2060 u64 v_pixclk = mode->clock; /* video timing pixclk */ 2061 u8 k = 1; 2062 2063 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2064 k = 2; 2065 2066 cstate->dsc_txp_clk_rate = v_pixclk; 2067 do_div(cstate->dsc_txp_clk_rate, (cstate->dsc_pixel_num * k)); 2068 2069 cstate->dsc_pxl_clk_rate = v_pixclk; 2070 do_div(cstate->dsc_pxl_clk_rate, (cstate->dsc_slice_num * k)); 2071 2072 /* dsc_cds = crtc_clock / (cds_dat_width / bits_per_pixel) 2073 * cds_dat_width = 96; 2074 * bits_per_pixel = [8-12]; 2075 * As cds clk is div from txp clk and only support 1/2/4 div, 2076 * so when txp_clk is equal to v_pixclk, we set dsc_cds = crtc_clock / 4, 2077 * otherwise dsc_cds = crtc_clock / 8; 2078 */ 2079 cstate->dsc_cds_clk_rate = v_pixclk / (cstate->dsc_txp_clk_rate == v_pixclk ? 4 : 8); 2080 2081 return 0; 2082 } 2083 2084 static unsigned long rk3588_vop2_if_cfg(struct display_state *state) 2085 { 2086 struct crtc_state *cstate = &state->crtc_state; 2087 struct connector_state *conn_state = &state->conn_state; 2088 struct drm_display_mode *mode = &conn_state->mode; 2089 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2090 struct vop2 *vop2 = cstate->private; 2091 u32 vp_offset = (cstate->crtc_id * 0x100); 2092 u16 hdisplay = mode->crtc_hdisplay; 2093 int output_if = conn_state->output_if; 2094 int if_pixclk_div = 0; 2095 int if_dclk_div = 0; 2096 unsigned long dclk_rate; 2097 u32 val; 2098 2099 if (output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2100 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; 2101 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; 2102 } else { 2103 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2104 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2105 } 2106 2107 if (cstate->dsc_enable) { 2108 int k = 1; 2109 2110 if (!vop2->data->nr_dscs) { 2111 printf("Unsupported DSC\n"); 2112 return 0; 2113 } 2114 2115 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2116 k = 2; 2117 2118 cstate->dsc_id = output_if & (VOP_OUTPUT_IF_MIPI0 | VOP_OUTPUT_IF_HDMI0) ? 0 : 1; 2119 cstate->dsc_slice_num = hdisplay / dsc_sink_cap->slice_width / k; 2120 cstate->dsc_pixel_num = cstate->dsc_slice_num > 4 ? 4 : cstate->dsc_slice_num; 2121 2122 vop2_calc_dsc_clk(state); 2123 printf("Enable DSC%d slice:%dx%d, slice num:%d\n", 2124 cstate->dsc_id, dsc_sink_cap->slice_width, 2125 dsc_sink_cap->slice_height, cstate->dsc_slice_num); 2126 } 2127 2128 dclk_rate = vop2_calc_cru_cfg(state, &cstate->dclk_core_div, &cstate->dclk_out_div, &if_pixclk_div, &if_dclk_div); 2129 2130 if (output_if & VOP_OUTPUT_IF_RGB) { 2131 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2132 4, false); 2133 } 2134 2135 if (output_if & VOP_OUTPUT_IF_BT1120) { 2136 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2137 3, false); 2138 } 2139 2140 if (output_if & VOP_OUTPUT_IF_BT656) { 2141 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 0x7, RK3588_RGB_EN_SHIFT, 2142 2, false); 2143 } 2144 2145 if (output_if & VOP_OUTPUT_IF_MIPI0) { 2146 if (cstate->crtc_id == 2) 2147 val = 0; 2148 else 2149 val = 1; 2150 2151 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2152 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2153 RK3588_MIPI_DSI0_MODE_SEL_SHIFT, 1, false); 2154 2155 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI0_EN_SHIFT, 2156 1, false); 2157 vop2_mask_write(vop2, RK3568_DSP_IF_EN, 1, RK3588_MIPI0_MUX_SHIFT, val, false); 2158 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI0_PIXCLK_DIV_SHIFT, 2159 if_pixclk_div, false); 2160 2161 if (conn_state->hold_mode) { 2162 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2163 EN_MASK, EDPI_TE_EN, 1, false); 2164 2165 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2166 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2167 } 2168 } 2169 2170 if (output_if & VOP_OUTPUT_IF_MIPI1) { 2171 if (cstate->crtc_id == 2) 2172 val = 0; 2173 else if (cstate->crtc_id == 3) 2174 val = 1; 2175 else 2176 val = 3; /*VP1*/ 2177 if (conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE) 2178 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2179 RK3588_MIPI_DSI1_MODE_SEL_SHIFT, 1, false); 2180 2181 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_MIPI1_EN_SHIFT, 2182 1, false); 2183 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, MIPI1_MUX_SHIFT, 2184 val, false); 2185 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, MIPI1_PIXCLK_DIV_SHIFT, 2186 if_pixclk_div, false); 2187 2188 if (conn_state->hold_mode) { 2189 /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */ 2190 if (vop2->version == VOP_VERSION_RK3588 && val == 3) 2191 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2192 EN_MASK, EDPI_TE_EN, 0, false); 2193 else 2194 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2195 EN_MASK, EDPI_TE_EN, 1, false); 2196 2197 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2198 EN_MASK, EDPI_WMS_HOLD_EN, 1, false); 2199 } 2200 } 2201 2202 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2203 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2204 MIPI_DUAL_EN_SHIFT, 1, false); 2205 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2206 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2207 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2208 false); 2209 switch (conn_state->type) { 2210 case DRM_MODE_CONNECTOR_DisplayPort: 2211 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2212 RK3588_DP_DUAL_EN_SHIFT, 1, false); 2213 break; 2214 case DRM_MODE_CONNECTOR_eDP: 2215 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2216 RK3588_EDP_DUAL_EN_SHIFT, 1, false); 2217 break; 2218 case DRM_MODE_CONNECTOR_HDMIA: 2219 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2220 RK3588_HDMI_DUAL_EN_SHIFT, 1, false); 2221 break; 2222 case DRM_MODE_CONNECTOR_DSI: 2223 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2224 RK3568_MIPI_DUAL_EN_SHIFT, 1, false); 2225 break; 2226 default: 2227 break; 2228 } 2229 } 2230 2231 if (output_if & VOP_OUTPUT_IF_eDP0) { 2232 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP0_EN_SHIFT, 2233 1, false); 2234 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2235 cstate->crtc_id, false); 2236 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2237 if_dclk_div, false); 2238 2239 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2240 if_pixclk_div, false); 2241 2242 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2243 RK3588_GRF_EDP0_ENABLE_SHIFT, 1); 2244 } 2245 2246 if (output_if & VOP_OUTPUT_IF_eDP1) { 2247 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_EDP1_EN_SHIFT, 2248 1, false); 2249 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2250 cstate->crtc_id, false); 2251 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2252 if_dclk_div, false); 2253 2254 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2255 if_pixclk_div, false); 2256 2257 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2258 RK3588_GRF_EDP1_ENABLE_SHIFT, 1); 2259 } 2260 2261 if (output_if & VOP_OUTPUT_IF_HDMI0) { 2262 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI0_EN_SHIFT, 2263 1, false); 2264 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP0_MUX_SHIFT, 2265 cstate->crtc_id, false); 2266 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_DCLK_DIV_SHIFT, 2267 if_dclk_div, false); 2268 2269 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP0_PIXCLK_DIV_SHIFT, 2270 if_pixclk_div, false); 2271 2272 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2273 RK3588_GRF_HDMITX0_ENABLE_SHIFT, 1); 2274 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2275 HDMI_SYNC_POL_MASK, 2276 HDMI0_SYNC_POL_SHIFT, val); 2277 } 2278 2279 if (output_if & VOP_OUTPUT_IF_HDMI1) { 2280 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_HDMI1_EN_SHIFT, 2281 1, false); 2282 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_HDMI_EDP1_MUX_SHIFT, 2283 cstate->crtc_id, false); 2284 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_DCLK_DIV_SHIFT, 2285 if_dclk_div, false); 2286 2287 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, 3, HDMI_EDP1_PIXCLK_DIV_SHIFT, 2288 if_pixclk_div, false); 2289 2290 vop2_grf_writel(vop2, vop2->vop_grf, RK3588_GRF_VOP_CON2, EN_MASK, 2291 RK3588_GRF_HDMITX1_ENABLE_SHIFT, 1); 2292 vop2_grf_writel(vop2, vop2->vo1_grf, RK3588_GRF_VO1_CON0, 2293 HDMI_SYNC_POL_MASK, 2294 HDMI1_SYNC_POL_SHIFT, val); 2295 } 2296 2297 if (output_if & VOP_OUTPUT_IF_DP0) { 2298 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP0_EN_SHIFT, 2299 1, false); 2300 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP0_MUX_SHIFT, 2301 cstate->crtc_id, false); 2302 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2303 RK3588_DP0_PIN_POL_SHIFT, val, false); 2304 } 2305 2306 if (output_if & VOP_OUTPUT_IF_DP1) { 2307 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RK3588_DP1_EN_SHIFT, 2308 1, false); 2309 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, RK3588_DP1_MUX_SHIFT, 2310 cstate->crtc_id, false); 2311 vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3588_IF_PIN_POL_MASK, 2312 RK3588_DP1_PIN_POL_SHIFT, val, false); 2313 } 2314 2315 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2316 DCLK_CORE_DIV_SHIFT, cstate->dclk_core_div, false); 2317 vop2_mask_write(vop2, RK3588_VP0_CLK_CTRL + vp_offset, 0x3, 2318 DCLK_OUT_DIV_SHIFT, cstate->dclk_out_div, false); 2319 2320 return dclk_rate; 2321 } 2322 2323 static unsigned long rk3568_vop2_if_cfg(struct display_state *state) 2324 { 2325 struct crtc_state *cstate = &state->crtc_state; 2326 struct connector_state *conn_state = &state->conn_state; 2327 struct drm_display_mode *mode = &conn_state->mode; 2328 struct vop2 *vop2 = cstate->private; 2329 u32 vp_offset = (cstate->crtc_id * 0x100); 2330 bool dclk_inv; 2331 u32 val; 2332 2333 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 2334 val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE); 2335 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE); 2336 2337 if (conn_state->output_if & VOP_OUTPUT_IF_RGB) { 2338 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2339 1, false); 2340 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2341 RGB_MUX_SHIFT, cstate->crtc_id, false); 2342 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2343 GRF_RGB_DCLK_INV_SHIFT, dclk_inv); 2344 } 2345 2346 if (conn_state->output_if & VOP_OUTPUT_IF_BT1120) { 2347 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT, 2348 1, false); 2349 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, 2350 BT1120_EN_SHIFT, 1, false); 2351 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2352 RGB_MUX_SHIFT, cstate->crtc_id, false); 2353 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2354 GRF_BT1120_CLK_INV_SHIFT, !dclk_inv); 2355 } 2356 2357 if (conn_state->output_if & VOP_OUTPUT_IF_BT656) { 2358 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT, 2359 1, false); 2360 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2361 RGB_MUX_SHIFT, cstate->crtc_id, false); 2362 vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK, 2363 GRF_BT656_CLK_INV_SHIFT, !dclk_inv); 2364 } 2365 2366 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) { 2367 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT, 2368 1, false); 2369 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2370 LVDS0_MUX_SHIFT, cstate->crtc_id, false); 2371 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2372 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2373 } 2374 2375 if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) { 2376 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS1_EN_SHIFT, 2377 1, false); 2378 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2379 LVDS1_MUX_SHIFT, cstate->crtc_id, false); 2380 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2381 IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false); 2382 } 2383 2384 if (conn_state->output_flags & 2385 (ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE | 2386 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)) { 2387 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2388 LVDS_DUAL_EN_SHIFT, 1, false); 2389 if (conn_state->output_flags & 2390 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2391 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2392 LVDS_DUAL_LEFT_RIGHT_EN_SHIFT, 1, 2393 false); 2394 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2395 vop2_mask_write(vop2, RK3568_DSP_IF_CTRL, EN_MASK, 2396 LVDS_DUAL_SWAP_EN_SHIFT, 1, false); 2397 } 2398 2399 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) { 2400 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT, 2401 1, false); 2402 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2403 MIPI0_MUX_SHIFT, cstate->crtc_id, false); 2404 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2405 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2406 } 2407 2408 if (conn_state->output_if & VOP_OUTPUT_IF_MIPI1) { 2409 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI1_EN_SHIFT, 2410 1, false); 2411 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2412 MIPI1_MUX_SHIFT, cstate->crtc_id, false); 2413 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2414 IF_CRTL_MIPI_DCLK_POL_SHIT, dclk_inv, false); 2415 } 2416 2417 if (conn_state->output_flags & 2418 ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2419 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, EN_MASK, 2420 MIPI_DUAL_EN_SHIFT, 1, false); 2421 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) 2422 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2423 EN_MASK, MIPI_DUAL_SWAP_EN_SHIFT, 1, 2424 false); 2425 } 2426 2427 if (conn_state->output_if & VOP_OUTPUT_IF_eDP0) { 2428 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, EDP0_EN_SHIFT, 2429 1, false); 2430 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2431 EDP0_MUX_SHIFT, cstate->crtc_id, false); 2432 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2433 IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false); 2434 } 2435 2436 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) { 2437 vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT, 2438 1, false); 2439 vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK, 2440 HDMI0_MUX_SHIFT, cstate->crtc_id, false); 2441 vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK, 2442 IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false); 2443 vop2_mask_write(vop2, RK3568_DSP_IF_POL, 2444 IF_CRTL_HDMI_PIN_POL_MASK, 2445 IF_CRTL_HDMI_PIN_POL_SHIT, val, false); 2446 } 2447 2448 return mode->clock; 2449 } 2450 2451 static void vop2_post_color_swap(struct display_state *state) 2452 { 2453 struct crtc_state *cstate = &state->crtc_state; 2454 struct connector_state *conn_state = &state->conn_state; 2455 struct vop2 *vop2 = cstate->private; 2456 u32 vp_offset = (cstate->crtc_id * 0x100); 2457 u32 output_type = conn_state->type; 2458 u32 data_swap = 0; 2459 2460 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 2461 data_swap = DSP_RB_SWAP; 2462 2463 if (vop2->version == VOP_VERSION_RK3588 && 2464 (output_type == DRM_MODE_CONNECTOR_HDMIA || 2465 output_type == DRM_MODE_CONNECTOR_eDP) && 2466 (conn_state->bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 2467 conn_state->bus_format == MEDIA_BUS_FMT_YUV10_1X30)) 2468 data_swap |= DSP_RG_SWAP; 2469 2470 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, 2471 DATA_SWAP_MASK, DATA_SWAP_SHIFT, data_swap, false); 2472 } 2473 2474 static void vop2_clk_set_parent(struct clk *clk, struct clk *parent) 2475 { 2476 int ret = 0; 2477 2478 if (parent->dev) 2479 ret = clk_set_parent(clk, parent); 2480 if (ret < 0) 2481 debug("failed to set %s as parent for %s\n", 2482 parent->dev->name, clk->dev->name); 2483 } 2484 2485 static ulong vop2_clk_set_rate(struct clk *clk, ulong rate) 2486 { 2487 int ret = 0; 2488 2489 if (clk->dev) 2490 ret = clk_set_rate(clk, rate); 2491 if (ret < 0) 2492 debug("failed to set %s rate %lu \n", clk->dev->name, rate); 2493 2494 return ret; 2495 } 2496 2497 static void vop2_calc_dsc_cru_cfg(struct display_state *state, 2498 int *dsc_txp_clk_div, int *dsc_pxl_clk_div, 2499 int *dsc_cds_clk_div, u64 dclk_rate) 2500 { 2501 struct crtc_state *cstate = &state->crtc_state; 2502 2503 *dsc_txp_clk_div = dclk_rate / cstate->dsc_txp_clk_rate; 2504 *dsc_pxl_clk_div = dclk_rate / cstate->dsc_pxl_clk_rate; 2505 *dsc_cds_clk_div = dclk_rate / cstate->dsc_cds_clk_rate; 2506 2507 *dsc_txp_clk_div = ilog2(*dsc_txp_clk_div); 2508 *dsc_pxl_clk_div = ilog2(*dsc_pxl_clk_div); 2509 *dsc_cds_clk_div = ilog2(*dsc_cds_clk_div); 2510 } 2511 2512 static void vop2_load_pps(struct display_state *state, struct vop2 *vop2, u8 dsc_id) 2513 { 2514 struct crtc_state *cstate = &state->crtc_state; 2515 struct drm_dsc_picture_parameter_set *pps = &cstate->pps; 2516 struct drm_dsc_picture_parameter_set config_pps; 2517 const struct vop2_data *vop2_data = vop2->data; 2518 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2519 u32 *pps_val = (u32 *)&config_pps; 2520 u32 decoder_regs_offset = (dsc_id * 0x100); 2521 int i = 0; 2522 2523 memcpy(&config_pps, pps, sizeof(config_pps)); 2524 2525 if ((config_pps.pps_3 & 0xf) > dsc_data->max_linebuf_depth) { 2526 config_pps.pps_3 &= 0xf0; 2527 config_pps.pps_3 |= dsc_data->max_linebuf_depth; 2528 printf("DSC%d max_linebuf_depth is: %d, current set value is: %d\n", 2529 dsc_id, dsc_data->max_linebuf_depth, config_pps.pps_3 & 0xf); 2530 } 2531 2532 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 2533 config_pps.rc_range_parameters[i] = 2534 (pps->rc_range_parameters[i] >> 3 & 0x1f) | 2535 ((pps->rc_range_parameters[i] >> 14 & 0x3) << 5) | 2536 ((pps->rc_range_parameters[i] >> 0 & 0x7) << 7) | 2537 ((pps->rc_range_parameters[i] >> 8 & 0x3f) << 10); 2538 } 2539 2540 for (i = 0; i < ROCKCHIP_DSC_PPS_SIZE_BYTE / 4; i++) 2541 vop2_writel(vop2, RK3588_DSC_8K_PPS0_3 + decoder_regs_offset + i * 4, *pps_val++); 2542 } 2543 2544 static void vop2_dsc_enable(struct display_state *state, struct vop2 *vop2, u8 dsc_id, u64 dclk_rate) 2545 { 2546 struct connector_state *conn_state = &state->conn_state; 2547 struct drm_display_mode *mode = &conn_state->mode; 2548 struct crtc_state *cstate = &state->crtc_state; 2549 struct rockchip_dsc_sink_cap *dsc_sink_cap = &cstate->dsc_sink_cap; 2550 const struct vop2_data *vop2_data = vop2->data; 2551 const struct vop2_dsc_data *dsc_data = &vop2_data->dsc[dsc_id]; 2552 bool mipi_ds_mode = false; 2553 u8 dsc_interface_mode = 0; 2554 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2555 u16 hdisplay = mode->crtc_hdisplay; 2556 u16 htotal = mode->crtc_htotal; 2557 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2558 u16 vdisplay = mode->crtc_vdisplay; 2559 u16 vtotal = mode->crtc_vtotal; 2560 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2561 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2562 u16 vact_end = vact_st + vdisplay; 2563 u32 ctrl_regs_offset = (dsc_id * 0x30); 2564 u32 decoder_regs_offset = (dsc_id * 0x100); 2565 u32 backup_regs_offset = 0; 2566 int dsc_txp_clk_div = 0; 2567 int dsc_pxl_clk_div = 0; 2568 int dsc_cds_clk_div = 0; 2569 2570 if (!vop2->data->nr_dscs) { 2571 printf("Unsupported DSC\n"); 2572 return; 2573 } 2574 2575 if (cstate->dsc_slice_num > dsc_data->max_slice_num) 2576 printf("DSC%d supported max slice is: %d, current is: %d\n", 2577 dsc_data->id, dsc_data->max_slice_num, cstate->dsc_slice_num); 2578 2579 if (dsc_data->pd_id) { 2580 if (vop2_power_domain_on(vop2, dsc_data->pd_id)) 2581 printf("open dsc%d pd fail\n", dsc_id); 2582 } 2583 2584 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, EN_MASK, 2585 SCAN_TIMING_PARA_IMD_EN_SHIFT, 1, false); 2586 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PORT_SEL_MASK, 2587 DSC_PORT_SEL_SHIFT, cstate->crtc_id, false); 2588 if (conn_state->output_if & (VOP_OUTPUT_IF_HDMI0 | VOP_OUTPUT_IF_HDMI1)) { 2589 dsc_interface_mode = VOP_DSC_IF_HDMI; 2590 } else { 2591 mipi_ds_mode = !!(conn_state->output_flags & ROCKCHIP_OUTPUT_MIPI_DS_MODE); 2592 if (mipi_ds_mode) 2593 dsc_interface_mode = VOP_DSC_IF_MIPI_DS_MODE; 2594 else 2595 dsc_interface_mode = VOP_DSC_IF_MIPI_VIDEO_MODE; 2596 } 2597 2598 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2599 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2600 DSC_MAN_MODE_SHIFT, 0, false); 2601 else 2602 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_MAN_MODE_MASK, 2603 DSC_MAN_MODE_SHIFT, 1, false); 2604 2605 vop2_calc_dsc_cru_cfg(state, &dsc_txp_clk_div, &dsc_pxl_clk_div, &dsc_cds_clk_div, dclk_rate); 2606 2607 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_INTERFACE_MODE_MASK, 2608 DSC_INTERFACE_MODE_SHIFT, dsc_interface_mode, false); 2609 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PIXEL_NUM_MASK, 2610 DSC_PIXEL_NUM_SHIFT, cstate->dsc_pixel_num >> 1, false); 2611 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_TXP_CLK_DIV_MASK, 2612 DSC_TXP_CLK_DIV_SHIFT, dsc_txp_clk_div, false); 2613 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_PXL_CLK_DIV_MASK, 2614 DSC_PXL_CLK_DIV_SHIFT, dsc_pxl_clk_div, false); 2615 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2616 DSC_CDS_CLK_DIV_SHIFT, dsc_cds_clk_div, false); 2617 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, EN_MASK, 2618 DSC_SCAN_EN_SHIFT, !mipi_ds_mode, false); 2619 vop2_mask_write(vop2, RK3588_DSC_8K_SYS_CTRL + ctrl_regs_offset, DSC_CDS_CLK_DIV_MASK, 2620 DSC_HALT_EN_SHIFT, mipi_ds_mode, false); 2621 2622 if (!mipi_ds_mode) { 2623 u16 dsc_hsync, dsc_htotal, dsc_hact_st, dsc_hact_end; 2624 u32 target_bpp = dsc_sink_cap->target_bits_per_pixel_x16; 2625 u64 dsc_cds_rate = cstate->dsc_cds_clk_rate; 2626 u32 v_pixclk_mhz = mode->crtc_clock / 1000; /* video timing pixclk */ 2627 u32 dly_num, dsc_cds_rate_mhz, val = 0; 2628 int k = 1; 2629 2630 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) 2631 k = 2; 2632 2633 if (target_bpp >> 4 < dsc_data->min_bits_per_pixel) 2634 printf("Unsupported bpp less than: %d\n", dsc_data->min_bits_per_pixel); 2635 2636 /* 2637 * dly_num = delay_line_num * T(one-line) / T (dsc_cds) 2638 * T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz 2639 * T (dsc_cds) = 1 / dsc_cds_rate_mhz 2640 * delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay 2641 * delay_line_num = 4 - BPP / 8 2642 * = (64 - target_bpp / 8) / 16 2643 * 2644 * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2645 */ 2646 do_div(dsc_cds_rate, 1000000); /* hz to Mhz */ 2647 dsc_cds_rate_mhz = dsc_cds_rate; 2648 dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16; 2649 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK, 2650 DSC_INIT_DLY_MODE_SHIFT, 0, false); 2651 vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK, 2652 DSC_INIT_DLY_NUM_SHIFT, dly_num, false); 2653 2654 dsc_hsync = hsync_len / 2; 2655 /* 2656 * htotal / dclk_core = dsc_htotal /cds_clk 2657 * 2658 * dclk_core = DCLK / (1 << dclk_core->div_val) 2659 * cds_clk = txp_clk / (1 << dsc_cds_clk->div_val) 2660 * txp_clk = DCLK / (1 << dsc_txp_clk->div_val) 2661 * 2662 * dsc_htotal = htotal * (1 << dclk_core->div_val) / 2663 * ((1 << dsc_txp_clk->div_val) * (1 << dsc_cds_clk->div_val)) 2664 */ 2665 dsc_htotal = htotal * (1 << cstate->dclk_core_div) / 2666 ((1 << dsc_txp_clk_div) * (1 << dsc_cds_clk_div)); 2667 val = dsc_htotal << 16 | dsc_hsync; 2668 vop2_mask_write(vop2, RK3588_DSC_8K_HTOTAL_HS_END + ctrl_regs_offset, DSC_HTOTAL_PW_MASK, 2669 DSC_HTOTAL_PW_SHIFT, val, false); 2670 2671 dsc_hact_st = hact_st / 2; 2672 dsc_hact_end = (hdisplay / k * target_bpp >> 4) / 24 + dsc_hact_st; 2673 val = dsc_hact_end << 16 | dsc_hact_st; 2674 vop2_mask_write(vop2, RK3588_DSC_8K_HACT_ST_END + ctrl_regs_offset, DSC_HACT_ST_END_MASK, 2675 DSC_HACT_ST_END_SHIFT, val, false); 2676 2677 vop2_mask_write(vop2, RK3588_DSC_8K_VTOTAL_VS_END + ctrl_regs_offset, DSC_VTOTAL_PW_MASK, 2678 DSC_VTOTAL_PW_SHIFT, vtotal << 16 | vsync_len, false); 2679 vop2_mask_write(vop2, RK3588_DSC_8K_VACT_ST_END + ctrl_regs_offset, DSC_VACT_ST_END_MASK, 2680 DSC_VACT_ST_END_SHIFT, vact_end << 16 | vact_st, false); 2681 } 2682 2683 vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK, 2684 RST_DEASSERT_SHIFT, 1, false); 2685 udelay(10); 2686 /* read current dsc core register and backup to regsbak */ 2687 backup_regs_offset = RK3588_DSC_8K_CTRL0; 2688 vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset); 2689 2690 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2691 DSC_EN_SHIFT, 1, false); 2692 vop2_load_pps(state, vop2, dsc_id); 2693 2694 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2695 DSC_RBIT_SHIFT, 1, false); 2696 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2697 DSC_RBYT_SHIFT, 0, false); 2698 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2699 DSC_FLAL_SHIFT, 1, false); 2700 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2701 DSC_MER_SHIFT, 1, false); 2702 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2703 DSC_EPB_SHIFT, 0, false); 2704 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2705 DSC_EPL_SHIFT, 1, false); 2706 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2707 DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false); 2708 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2709 DSC_SBO_SHIFT, 1, false); 2710 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2711 DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false); 2712 vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK, 2713 DSC_PPS_UPD_SHIFT, 1, false); 2714 2715 printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n", 2716 dsc_id, 2717 cstate->dsc_txp_clk_rate, dsc_txp_clk_div, 2718 cstate->dsc_pxl_clk_rate, dsc_pxl_clk_div, 2719 cstate->dsc_cds_clk_rate, dsc_cds_clk_div); 2720 } 2721 2722 static bool is_extend_pll(struct display_state *state, struct udevice **clk_dev) 2723 { 2724 struct crtc_state *cstate = &state->crtc_state; 2725 struct vop2 *vop2 = cstate->private; 2726 struct udevice *vp_dev, *dev; 2727 struct ofnode_phandle_args args; 2728 char vp_name[10]; 2729 int ret; 2730 2731 if (vop2->version != VOP_VERSION_RK3588) 2732 return false; 2733 2734 sprintf(vp_name, "port@%d", cstate->crtc_id); 2735 if (uclass_find_device_by_name(UCLASS_VIDEO_CRTC, vp_name, &vp_dev)) { 2736 debug("warn: can't get vp device\n"); 2737 return false; 2738 } 2739 2740 ret = dev_read_phandle_with_args(vp_dev, "assigned-clock-parents", "#clock-cells", 0, 2741 0, &args); 2742 if (ret) { 2743 debug("assigned-clock-parents's node not define\n"); 2744 return false; 2745 } 2746 2747 if (uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &dev)) { 2748 debug("warn: can't get clk device\n"); 2749 return false; 2750 } 2751 2752 if (!strcmp(dev->name, "hdmiphypll_clk0") || !strcmp(dev->name, "hdmiphypll_clk1")) { 2753 printf("%s: clk dev :%s: vp port:%s\n", __func__, dev->name, vp_dev->name); 2754 if (clk_dev) 2755 *clk_dev = dev; 2756 return true; 2757 } 2758 2759 return false; 2760 } 2761 2762 static int rockchip_vop2_init(struct display_state *state) 2763 { 2764 struct crtc_state *cstate = &state->crtc_state; 2765 struct connector_state *conn_state = &state->conn_state; 2766 struct drm_display_mode *mode = &conn_state->mode; 2767 struct vop2 *vop2 = cstate->private; 2768 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 2769 u16 hdisplay = mode->crtc_hdisplay; 2770 u16 htotal = mode->crtc_htotal; 2771 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 2772 u16 hact_end = hact_st + hdisplay; 2773 u16 vdisplay = mode->crtc_vdisplay; 2774 u16 vtotal = mode->crtc_vtotal; 2775 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 2776 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 2777 u16 vact_end = vact_st + vdisplay; 2778 bool yuv_overlay = false; 2779 u32 vp_offset = (cstate->crtc_id * 0x100); 2780 u32 line_flag_offset = (cstate->crtc_id * 4); 2781 u32 val, act_end; 2782 u8 dither_down_en = 0; 2783 u8 pre_dither_down_en = 0; 2784 u8 dclk_div_factor = 0; 2785 char output_type_name[30] = {0}; 2786 char dclk_name[9]; 2787 struct clk dclk; 2788 struct clk hdmi0_phy_pll; 2789 struct clk hdmi1_phy_pll; 2790 struct clk hdmi_phy_pll; 2791 struct udevice *disp_dev; 2792 unsigned long dclk_rate; 2793 int ret; 2794 2795 printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n", 2796 mode->crtc_hdisplay, mode->crtc_vdisplay, 2797 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 2798 mode->vrefresh, 2799 get_output_if_name(conn_state->output_if, output_type_name), 2800 cstate->crtc_id); 2801 2802 if (mode->hdisplay > VOP2_MAX_VP_OUTPUT_WIDTH) { 2803 cstate->splice_mode = true; 2804 cstate->splice_crtc_id = vop2->data->vp_data[cstate->crtc_id].splice_vp_id; 2805 if (!cstate->splice_crtc_id) { 2806 printf("%s: Splice mode is unsupported by vp%d\n", 2807 __func__, cstate->crtc_id); 2808 return -EINVAL; 2809 } 2810 2811 vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, EN_MASK, 2812 PORT_MERGE_EN_SHIFT, 1, false); 2813 } 2814 2815 vop2_initial(vop2, state); 2816 if (vop2->version == VOP_VERSION_RK3588) 2817 dclk_rate = rk3588_vop2_if_cfg(state); 2818 else 2819 dclk_rate = rk3568_vop2_if_cfg(state); 2820 2821 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 2822 !(cstate->feature & VOP_FEATURE_OUTPUT_10BIT)) 2823 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 2824 2825 vop2_post_color_swap(state); 2826 2827 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, OUT_MODE_MASK, 2828 OUT_MODE_SHIFT, conn_state->output_mode, false); 2829 2830 switch (conn_state->bus_format) { 2831 case MEDIA_BUS_FMT_RGB565_1X16: 2832 dither_down_en = 1; 2833 break; 2834 case MEDIA_BUS_FMT_RGB666_1X18: 2835 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 2836 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 2837 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 2838 dither_down_en = 1; 2839 break; 2840 case MEDIA_BUS_FMT_YUV8_1X24: 2841 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2842 dither_down_en = 0; 2843 pre_dither_down_en = 1; 2844 break; 2845 case MEDIA_BUS_FMT_YUV10_1X30: 2846 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2847 case MEDIA_BUS_FMT_RGB888_1X24: 2848 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 2849 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 2850 default: 2851 dither_down_en = 0; 2852 pre_dither_down_en = 0; 2853 break; 2854 } 2855 2856 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 2857 pre_dither_down_en = 0; 2858 else 2859 pre_dither_down_en = 1; 2860 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2861 DITHER_DOWN_EN_SHIFT, dither_down_en, false); 2862 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2863 PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false); 2864 2865 yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0; 2866 vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id, 2867 yuv_overlay, false); 2868 2869 cstate->yuv_overlay = yuv_overlay; 2870 2871 vop2_writel(vop2, RK3568_VP0_DSP_HTOTAL_HS_END + vp_offset, 2872 (htotal << 16) | hsync_len); 2873 val = hact_st << 16; 2874 val |= hact_end; 2875 vop2_writel(vop2, RK3568_VP0_DSP_HACT_ST_END + vp_offset, val); 2876 val = vact_st << 16; 2877 val |= vact_end; 2878 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END + vp_offset, val); 2879 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2880 u16 vact_st_f1 = vtotal + vact_st + 1; 2881 u16 vact_end_f1 = vact_st_f1 + vdisplay; 2882 2883 val = vact_st_f1 << 16 | vact_end_f1; 2884 vop2_writel(vop2, RK3568_VP0_DSP_VACT_ST_END_F1 + vp_offset, 2885 val); 2886 2887 val = vtotal << 16 | (vtotal + vsync_len); 2888 vop2_writel(vop2, RK3568_VP0_DSP_VS_ST_END_F1 + vp_offset, val); 2889 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2890 INTERLACE_EN_SHIFT, 1, false); 2891 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2892 DSP_FILED_POL, 1, false); 2893 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2894 P2I_EN_SHIFT, 1, false); 2895 vtotal += vtotal + 1; 2896 act_end = vact_end_f1; 2897 } else { 2898 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2899 INTERLACE_EN_SHIFT, 0, false); 2900 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2901 P2I_EN_SHIFT, 0, false); 2902 act_end = vact_end; 2903 } 2904 vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset, 2905 (vtotal << 16) | vsync_len); 2906 2907 if (vop2->version == VOP_VERSION_RK3568) { 2908 if (mode->flags & DRM_MODE_FLAG_DBLCLK || 2909 conn_state->output_if & VOP_OUTPUT_IF_BT656) 2910 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2911 CORE_DCLK_DIV_EN_SHIFT, 1, false); 2912 else 2913 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2914 CORE_DCLK_DIV_EN_SHIFT, 0, false); 2915 } 2916 2917 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420) 2918 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2919 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0x3, false); 2920 else 2921 vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset, 2922 DCLK_DIV2_MASK, DCLK_DIV2_SHIFT, 0, false); 2923 2924 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2925 OVL_MODE_SEL_SHIFT + cstate->crtc_id, yuv_overlay, false); 2926 2927 if (yuv_overlay) 2928 val = 0x20010200; 2929 else 2930 val = 0; 2931 vop2_writel(vop2, RK3568_VP0_DSP_BG + vp_offset, val); 2932 if (cstate->splice_mode) { 2933 vop2_mask_write(vop2, RK3568_OVL_CTRL, OVL_MODE_SEL_MASK, 2934 OVL_MODE_SEL_SHIFT + cstate->splice_crtc_id, 2935 yuv_overlay, false); 2936 vop2_writel(vop2, RK3568_VP0_DSP_BG + (cstate->splice_crtc_id * 0x100), val); 2937 } 2938 2939 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 2940 POST_DSP_OUT_R2Y_SHIFT, yuv_overlay, false); 2941 2942 vop2_tv_config_update(state, vop2); 2943 vop2_post_config(state, vop2); 2944 2945 if (cstate->dsc_enable) { 2946 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 2947 vop2_dsc_enable(state, vop2, 0, dclk_rate); 2948 vop2_dsc_enable(state, vop2, 1, dclk_rate); 2949 } else { 2950 vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate); 2951 } 2952 } 2953 2954 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id); 2955 ret = clk_get_by_name(cstate->dev, dclk_name, &dclk); 2956 if (ret) { 2957 printf("%s: Failed to get dclk ret=%d\n", __func__, ret); 2958 return ret; 2959 } 2960 2961 ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev); 2962 if (!ret) { 2963 ret = clk_get_by_name(disp_dev, "hdmi0_phy_pll", &hdmi0_phy_pll); 2964 if (ret) 2965 debug("%s: hdmi0_phy_pll may not define\n", __func__); 2966 ret = clk_get_by_name(disp_dev, "hdmi1_phy_pll", &hdmi1_phy_pll); 2967 if (ret) 2968 debug("%s: hdmi1_phy_pll may not define\n", __func__); 2969 } else { 2970 hdmi0_phy_pll.dev = NULL; 2971 hdmi1_phy_pll.dev = NULL; 2972 debug("%s: Faile to find display-subsystem node\n", __func__); 2973 } 2974 2975 if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) { 2976 if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) 2977 vop2_clk_set_parent(&dclk, &hdmi0_phy_pll); 2978 else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1) 2979 vop2_clk_set_parent(&dclk, &hdmi1_phy_pll); 2980 2981 /* 2982 * uboot clk driver won't set dclk parent's rate when use 2983 * hdmi phypll as dclk source. 2984 * So set dclk rate is meaningless. Set hdmi phypll rate 2985 * directly. 2986 */ 2987 if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI0) && hdmi0_phy_pll.dev) { 2988 ret = vop2_clk_set_rate(&hdmi0_phy_pll, dclk_rate * 1000); 2989 } else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) { 2990 ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000); 2991 } else { 2992 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 2993 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 2994 else 2995 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 2996 } 2997 } else { 2998 if (is_extend_pll(state, &hdmi_phy_pll.dev)) 2999 ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000); 3000 else 3001 ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000); 3002 } 3003 3004 if (IS_ERR_VALUE(ret)) { 3005 printf("%s: Failed to set vp%d dclk[%ld KHZ] ret=%d\n", 3006 __func__, cstate->crtc_id, dclk_rate, ret); 3007 return ret; 3008 } else { 3009 dclk_div_factor = mode->clock / dclk_rate; 3010 mode->crtc_clock = ret * dclk_div_factor / 1000; 3011 printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock); 3012 } 3013 3014 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3015 RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false); 3016 vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK, 3017 RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false); 3018 3019 return 0; 3020 } 3021 3022 static void vop2_setup_scale(struct vop2 *vop2, struct vop2_win_data *win, 3023 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 3024 uint32_t dst_h) 3025 { 3026 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 3027 uint16_t hscl_filter_mode, vscl_filter_mode; 3028 uint8_t gt2 = 0, gt4 = 0; 3029 uint32_t xfac = 0, yfac = 0; 3030 uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC; 3031 uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3032 uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL; 3033 uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL; 3034 u32 win_offset = win->reg_offset; 3035 3036 if (src_h >= (4 * dst_h)) 3037 gt4 = 1; 3038 else if (src_h >= (2 * dst_h)) 3039 gt2 = 1; 3040 3041 if (gt4) 3042 src_h >>= 2; 3043 else if (gt2) 3044 src_h >>= 1; 3045 3046 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 3047 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 3048 3049 if (yrgb_hor_scl_mode == SCALE_UP) 3050 hscl_filter_mode = hsu_filter_mode; 3051 else 3052 hscl_filter_mode = hsd_filter_mode; 3053 3054 if (yrgb_ver_scl_mode == SCALE_UP) 3055 vscl_filter_mode = vsu_filter_mode; 3056 else 3057 vscl_filter_mode = vsd_filter_mode; 3058 3059 /* 3060 * RK3568 VOP Esmart/Smart dsp_w should be even pixel 3061 * at scale down mode 3062 */ 3063 if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) { 3064 printf("win dst_w[%d] should align as 2 pixel\n", dst_w); 3065 dst_w += 1; 3066 } 3067 3068 xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w); 3069 yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h); 3070 3071 if (win->type == CLUSTER_LAYER) { 3072 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset, 3073 yfac << 16 | xfac); 3074 3075 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3076 YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false); 3077 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3078 YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false); 3079 3080 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3081 YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3082 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset, 3083 YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3084 3085 } else { 3086 vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset, 3087 yfac << 16 | xfac); 3088 3089 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3090 YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false); 3091 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3092 YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false); 3093 3094 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3095 YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false); 3096 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3097 YRGB_YSCL_MODE_MASK, YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false); 3098 3099 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3100 YRGB_XSCL_FILTER_MODE_MASK, YRGB_XSCL_FILTER_MODE_SHIFT, 3101 hscl_filter_mode, false); 3102 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset, 3103 YRGB_YSCL_FILTER_MODE_MASK, YRGB_YSCL_FILTER_MODE_SHIFT, 3104 vscl_filter_mode, false); 3105 } 3106 } 3107 3108 static void vop2_axi_config(struct vop2 *vop2, struct vop2_win_data *win) 3109 { 3110 u32 win_offset = win->reg_offset; 3111 3112 if (win->type == CLUSTER_LAYER) { 3113 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, CLUSTER_AXI_ID_MASK, 3114 CLUSTER_AXI_ID_SHIFT, win->axi_id, false); 3115 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_YRGB_ID_MASK, 3116 CLUSTER_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3117 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL2 + win_offset, CLUSTER_AXI_UV_ID_MASK, 3118 CLUSTER_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3119 } else { 3120 vop2_mask_write(vop2, RK3568_ESMART0_AXI_CTRL + win_offset, ESMART_AXI_ID_MASK, 3121 ESMART_AXI_ID_SHIFT, win->axi_id, false); 3122 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_YRGB_ID_MASK, 3123 ESMART_AXI_YRGB_ID_SHIFT, win->axi_yrgb_id, false); 3124 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, ESMART_AXI_UV_ID_MASK, 3125 ESMART_AXI_UV_ID_SHIFT, win->axi_uv_id, false); 3126 } 3127 } 3128 3129 static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win) 3130 { 3131 struct crtc_state *cstate = &state->crtc_state; 3132 struct connector_state *conn_state = &state->conn_state; 3133 struct drm_display_mode *mode = &conn_state->mode; 3134 struct vop2 *vop2 = cstate->private; 3135 int src_w = cstate->src_rect.w; 3136 int src_h = cstate->src_rect.h; 3137 int crtc_x = cstate->crtc_rect.x; 3138 int crtc_y = cstate->crtc_rect.y; 3139 int crtc_w = cstate->crtc_rect.w; 3140 int crtc_h = cstate->crtc_rect.h; 3141 int xvir = cstate->xvir; 3142 int y_mirror = 0; 3143 int csc_mode; 3144 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3145 /* offset of the right window in splice mode */ 3146 u32 splice_pixel_offset = 0; 3147 u32 splice_yrgb_offset = 0; 3148 u32 win_offset = win->reg_offset; 3149 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3150 3151 if (win->splice_mode_right) { 3152 src_w = cstate->right_src_rect.w; 3153 src_h = cstate->right_src_rect.h; 3154 crtc_x = cstate->right_crtc_rect.x; 3155 crtc_y = cstate->right_crtc_rect.y; 3156 crtc_w = cstate->right_crtc_rect.w; 3157 crtc_h = cstate->right_crtc_rect.h; 3158 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3159 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3160 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3161 } 3162 3163 act_info = (src_h - 1) << 16; 3164 act_info |= (src_w - 1) & 0xffff; 3165 3166 dsp_info = (crtc_h - 1) << 16; 3167 dsp_info |= (crtc_w - 1) & 0xffff; 3168 3169 dsp_stx = crtc_x; 3170 dsp_sty = crtc_y; 3171 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3172 3173 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3174 y_mirror = 1; 3175 else 3176 y_mirror = 0; 3177 3178 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3179 3180 if (vop2->version == VOP_VERSION_RK3588) 3181 vop2_axi_config(vop2, win); 3182 3183 if (y_mirror) 3184 printf("WARN: y mirror is unsupported by cluster window\n"); 3185 3186 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, 3187 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3188 false); 3189 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_VIR + win_offset, xvir); 3190 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_YRGB_MST + win_offset, 3191 cstate->dma_addr + splice_yrgb_offset); 3192 3193 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_ACT_INFO + win_offset, act_info); 3194 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_INFO + win_offset, dsp_info); 3195 vop2_writel(vop2, RK3568_CLUSTER0_WIN0_DSP_ST + win_offset, dsp_st); 3196 3197 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false); 3198 3199 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3200 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, 3201 CLUSTER_RGB2YUV_EN_SHIFT, 3202 is_yuv_output(conn_state->bus_format), false); 3203 vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK, 3204 CLUSTER_CSC_MODE_SHIFT, csc_mode, false); 3205 vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false); 3206 3207 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3208 } 3209 3210 static void vop2_set_smart_win(struct display_state *state, struct vop2_win_data *win) 3211 { 3212 struct crtc_state *cstate = &state->crtc_state; 3213 struct connector_state *conn_state = &state->conn_state; 3214 struct drm_display_mode *mode = &conn_state->mode; 3215 struct vop2 *vop2 = cstate->private; 3216 int src_w = cstate->src_rect.w; 3217 int src_h = cstate->src_rect.h; 3218 int crtc_x = cstate->crtc_rect.x; 3219 int crtc_y = cstate->crtc_rect.y; 3220 int crtc_w = cstate->crtc_rect.w; 3221 int crtc_h = cstate->crtc_rect.h; 3222 int xvir = cstate->xvir; 3223 int y_mirror = 0; 3224 int csc_mode; 3225 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 3226 /* offset of the right window in splice mode */ 3227 u32 splice_pixel_offset = 0; 3228 u32 splice_yrgb_offset = 0; 3229 u32 win_offset = win->reg_offset; 3230 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3231 3232 if (win->splice_mode_right) { 3233 src_w = cstate->right_src_rect.w; 3234 src_h = cstate->right_src_rect.h; 3235 crtc_x = cstate->right_crtc_rect.x; 3236 crtc_y = cstate->right_crtc_rect.y; 3237 crtc_w = cstate->right_crtc_rect.w; 3238 crtc_h = cstate->right_crtc_rect.h; 3239 splice_pixel_offset = cstate->right_src_rect.x - cstate->src_rect.x; 3240 splice_yrgb_offset = splice_pixel_offset * (state->logo.bpp >> 3); 3241 cfg_done = CFG_DONE_EN | BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3242 } 3243 3244 /* 3245 * This is workaround solution for IC design: 3246 * esmart can't support scale down when actual_w % 16 == 1. 3247 */ 3248 if (src_w > crtc_w && (src_w & 0xf) == 1) { 3249 printf("WARN: vp%d unsupported act_w[%d] mode 16 = 1 when scale down\n", cstate->crtc_id, src_w); 3250 src_w -= 1; 3251 } 3252 3253 act_info = (src_h - 1) << 16; 3254 act_info |= (src_w - 1) & 0xffff; 3255 3256 dsp_info = (crtc_h - 1) << 16; 3257 dsp_info |= (crtc_w - 1) & 0xffff; 3258 3259 dsp_stx = crtc_x; 3260 dsp_sty = crtc_y; 3261 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 3262 3263 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 3264 y_mirror = 1; 3265 else 3266 y_mirror = 0; 3267 3268 vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h); 3269 3270 if (vop2->version == VOP_VERSION_RK3588) 3271 vop2_axi_config(vop2, win); 3272 3273 if (y_mirror) 3274 cstate->dma_addr += (src_h - 1) * xvir * 4; 3275 vop2_mask_write(vop2, RK3568_ESMART0_CTRL1 + win_offset, EN_MASK, 3276 YMIRROR_EN_SHIFT, y_mirror, false); 3277 3278 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, 3279 WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format, 3280 false); 3281 vop2_writel(vop2, RK3568_ESMART0_REGION0_VIR + win_offset, xvir); 3282 vop2_writel(vop2, RK3568_ESMART0_REGION0_YRGB_MST + win_offset, 3283 cstate->dma_addr + splice_yrgb_offset); 3284 3285 vop2_writel(vop2, RK3568_ESMART0_REGION0_ACT_INFO + win_offset, 3286 act_info); 3287 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_INFO + win_offset, 3288 dsp_info); 3289 vop2_writel(vop2, RK3568_ESMART0_REGION0_DSP_ST + win_offset, dsp_st); 3290 3291 vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK, 3292 WIN_EN_SHIFT, 1, false); 3293 3294 csc_mode = vop2_convert_csc_mode(conn_state->color_space); 3295 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK, 3296 RGB2YUV_EN_SHIFT, 3297 is_yuv_output(conn_state->bus_format), false); 3298 vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK, 3299 CSC_MODE_SHIFT, csc_mode, false); 3300 3301 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3302 } 3303 3304 static void vop2_calc_display_rect_for_splice(struct display_state *state) 3305 { 3306 struct crtc_state *cstate = &state->crtc_state; 3307 struct connector_state *conn_state = &state->conn_state; 3308 struct drm_display_mode *mode = &conn_state->mode; 3309 struct display_rect *src_rect = &cstate->src_rect; 3310 struct display_rect *dst_rect = &cstate->crtc_rect; 3311 struct display_rect left_src, left_dst, right_src, right_dst; 3312 u16 half_hdisplay = mode->crtc_hdisplay >> 1; 3313 int left_src_w, left_dst_w, right_dst_w; 3314 3315 left_dst_w = min_t(u16, half_hdisplay, dst_rect->x + dst_rect->w) - dst_rect->x; 3316 if (left_dst_w < 0) 3317 left_dst_w = 0; 3318 right_dst_w = dst_rect->w - left_dst_w; 3319 3320 if (!right_dst_w) 3321 left_src_w = src_rect->w; 3322 else 3323 left_src_w = src_rect->x + src_rect->w - src_rect->w / 2; 3324 3325 left_src.x = src_rect->x; 3326 left_src.w = left_src_w; 3327 left_dst.x = dst_rect->x; 3328 left_dst.w = left_dst_w; 3329 right_src.x = left_src.x + left_src.w; 3330 right_src.w = src_rect->x + src_rect->w - left_src.x - left_src.w; 3331 right_dst.x = dst_rect->x + left_dst_w - half_hdisplay; 3332 right_dst.w = right_dst_w; 3333 3334 left_src.y = src_rect->y; 3335 left_src.h = src_rect->h; 3336 left_dst.y = dst_rect->y; 3337 left_dst.h = dst_rect->h; 3338 right_src.y = src_rect->y; 3339 right_src.h = src_rect->h; 3340 right_dst.y = dst_rect->y; 3341 right_dst.h = dst_rect->h; 3342 3343 memcpy(&cstate->src_rect, &left_src, sizeof(struct display_rect)); 3344 memcpy(&cstate->crtc_rect, &left_dst, sizeof(struct display_rect)); 3345 memcpy(&cstate->right_src_rect, &right_src, sizeof(struct display_rect)); 3346 memcpy(&cstate->right_crtc_rect, &right_dst, sizeof(struct display_rect)); 3347 } 3348 3349 static int rockchip_vop2_set_plane(struct display_state *state) 3350 { 3351 struct crtc_state *cstate = &state->crtc_state; 3352 struct vop2 *vop2 = cstate->private; 3353 struct vop2_win_data *win_data; 3354 struct vop2_win_data *splice_win_data; 3355 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3356 char plane_name[10] = {0}; 3357 3358 if (cstate->crtc_rect.w > cstate->max_output.width) { 3359 printf("ERROR: output w[%d] exceeded max width[%d]\n", 3360 cstate->crtc_rect.w, cstate->max_output.width); 3361 return -EINVAL; 3362 } 3363 3364 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3365 if (!win_data) { 3366 printf("invalid win id %d\n", primary_plane_id); 3367 return -ENODEV; 3368 } 3369 3370 if (vop2->version == VOP_VERSION_RK3588) { 3371 if (vop2_power_domain_on(vop2, win_data->pd_id)) 3372 printf("open vp%d plane pd fail\n", cstate->crtc_id); 3373 } 3374 3375 if (cstate->splice_mode) { 3376 if (win_data->splice_win_id) { 3377 splice_win_data = vop2_find_win_by_phys_id(vop2, win_data->splice_win_id); 3378 splice_win_data->splice_mode_right = true; 3379 3380 if (vop2_power_domain_on(vop2, splice_win_data->pd_id)) 3381 printf("splice mode: open vp%d plane pd fail\n", cstate->splice_crtc_id); 3382 3383 vop2_calc_display_rect_for_splice(state); 3384 if (win_data->type == CLUSTER_LAYER) 3385 vop2_set_cluster_win(state, splice_win_data); 3386 else 3387 vop2_set_smart_win(state, splice_win_data); 3388 } else { 3389 printf("ERROR: splice mode is unsupported by plane %s\n", 3390 get_plane_name(primary_plane_id, plane_name)); 3391 return -EINVAL; 3392 } 3393 } 3394 3395 if (win_data->type == CLUSTER_LAYER) 3396 vop2_set_cluster_win(state, win_data); 3397 else 3398 vop2_set_smart_win(state, win_data); 3399 3400 printf("VOP VP%d enable %s[%dx%d->%dx%d@%dx%d] fmt[%d] addr[0x%x]\n", 3401 cstate->crtc_id, get_plane_name(primary_plane_id, plane_name), 3402 cstate->src_rect.w, cstate->src_rect.h, cstate->crtc_rect.w, cstate->crtc_rect.h, 3403 cstate->crtc_rect.x, cstate->crtc_rect.y, cstate->format, 3404 cstate->dma_addr); 3405 3406 return 0; 3407 } 3408 3409 static int rockchip_vop2_prepare(struct display_state *state) 3410 { 3411 return 0; 3412 } 3413 3414 static void vop2_dsc_cfg_done(struct display_state *state) 3415 { 3416 struct connector_state *conn_state = &state->conn_state; 3417 struct crtc_state *cstate = &state->crtc_state; 3418 struct vop2 *vop2 = cstate->private; 3419 u8 dsc_id = cstate->dsc_id; 3420 u32 ctrl_regs_offset = (dsc_id * 0x30); 3421 3422 if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) { 3423 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE, EN_MASK, 3424 DSC_CFG_DONE_SHIFT, 1, false); 3425 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + 0x30, EN_MASK, 3426 DSC_CFG_DONE_SHIFT, 1, false); 3427 } else { 3428 vop2_mask_write(vop2, RK3588_DSC_8K_CFG_DONE + ctrl_regs_offset, EN_MASK, 3429 DSC_CFG_DONE_SHIFT, 1, false); 3430 } 3431 } 3432 3433 static int rockchip_vop2_enable(struct display_state *state) 3434 { 3435 struct crtc_state *cstate = &state->crtc_state; 3436 struct vop2 *vop2 = cstate->private; 3437 u32 vp_offset = (cstate->crtc_id * 0x100); 3438 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3439 3440 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3441 STANDBY_EN_SHIFT, 0, false); 3442 3443 if (cstate->splice_mode) 3444 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3445 3446 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3447 3448 if (cstate->dsc_enable) 3449 vop2_dsc_cfg_done(state); 3450 3451 return 0; 3452 } 3453 3454 static int rockchip_vop2_disable(struct display_state *state) 3455 { 3456 struct crtc_state *cstate = &state->crtc_state; 3457 struct vop2 *vop2 = cstate->private; 3458 u32 vp_offset = (cstate->crtc_id * 0x100); 3459 u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16); 3460 3461 vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK, 3462 STANDBY_EN_SHIFT, 1, false); 3463 3464 if (cstate->splice_mode) 3465 cfg_done |= BIT(cstate->splice_crtc_id) | (BIT(cstate->splice_crtc_id) << 16); 3466 3467 vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done); 3468 3469 return 0; 3470 } 3471 3472 static int rockchip_vop2_get_cursor_plane(struct display_state *state, u32 plane_mask, int cursor_plane) 3473 { 3474 struct crtc_state *cstate = &state->crtc_state; 3475 struct vop2 *vop2 = cstate->private; 3476 int i = 0; 3477 int correct_cursor_plane = -1; 3478 int plane_type = -1; 3479 3480 if (cursor_plane < 0) 3481 return -1; 3482 3483 if (plane_mask & (1 << cursor_plane)) 3484 return cursor_plane; 3485 3486 /* Get current cursor plane type */ 3487 for (i = 0; i < vop2->data->nr_layers; i++) { 3488 if (vop2->data->plane_table[i].plane_id == cursor_plane) { 3489 plane_type = vop2->data->plane_table[i].plane_type; 3490 break; 3491 } 3492 } 3493 3494 /* Get the other same plane type plane id */ 3495 for (i = 0; i < vop2->data->nr_layers; i++) { 3496 if (vop2->data->plane_table[i].plane_type == plane_type && 3497 vop2->data->plane_table[i].plane_id != cursor_plane) { 3498 correct_cursor_plane = vop2->data->plane_table[i].plane_id; 3499 break; 3500 } 3501 } 3502 3503 /* To check whether the new correct_cursor_plane is attach to current vp */ 3504 if (correct_cursor_plane < 0 || !(plane_mask & (1 << correct_cursor_plane))) { 3505 printf("error: faild to find correct plane as cursor plane\n"); 3506 return -1; 3507 } 3508 3509 printf("vp%d adjust cursor plane from %d to %d\n", 3510 cstate->crtc_id, cursor_plane, correct_cursor_plane); 3511 3512 return correct_cursor_plane; 3513 } 3514 3515 static int rockchip_vop2_fixup_dts(struct display_state *state, void *blob) 3516 { 3517 struct crtc_state *cstate = &state->crtc_state; 3518 struct vop2 *vop2 = cstate->private; 3519 ofnode vp_node; 3520 struct device_node *port_parent_node = cstate->ports_node; 3521 static bool vop_fix_dts; 3522 const char *path; 3523 u32 plane_mask = 0; 3524 int vp_id = 0; 3525 int cursor_plane_id = -1; 3526 3527 if (vop_fix_dts) 3528 return 0; 3529 3530 ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) { 3531 path = vp_node.np->full_name; 3532 plane_mask = vop2->vp_plane_mask[vp_id].plane_mask; 3533 3534 if (cstate->crtc->assign_plane) 3535 continue; 3536 cursor_plane_id = rockchip_vop2_get_cursor_plane(state, plane_mask, 3537 cstate->crtc->vps[vp_id].cursor_plane); 3538 printf("vp%d, plane_mask:0x%x, primary-id:%d, curser-id:%d\n", 3539 vp_id, plane_mask, 3540 vop2->vp_plane_mask[vp_id].primary_plane_id, 3541 cursor_plane_id); 3542 3543 do_fixup_by_path_u32(blob, path, "rockchip,plane-mask", 3544 plane_mask, 1); 3545 do_fixup_by_path_u32(blob, path, "rockchip,primary-plane", 3546 vop2->vp_plane_mask[vp_id].primary_plane_id, 1); 3547 if (cursor_plane_id >= 0) 3548 do_fixup_by_path_u32(blob, path, "cursor-win-id", 3549 cursor_plane_id, 1); 3550 vp_id++; 3551 } 3552 3553 vop_fix_dts = true; 3554 3555 return 0; 3556 } 3557 3558 static int rockchip_vop2_check(struct display_state *state) 3559 { 3560 struct crtc_state *cstate = &state->crtc_state; 3561 struct rockchip_crtc *crtc = cstate->crtc; 3562 3563 if (crtc->splice_mode && cstate->crtc_id == crtc->splice_crtc_id) { 3564 printf("WARN: VP%d is busy in splice mode\n", cstate->crtc_id); 3565 return -ENOTSUPP; 3566 } 3567 3568 if (cstate->splice_mode) { 3569 crtc->splice_mode = true; 3570 crtc->splice_crtc_id = cstate->splice_crtc_id; 3571 } 3572 3573 return 0; 3574 } 3575 3576 static int rockchip_vop2_mode_valid(struct display_state *state) 3577 { 3578 struct connector_state *conn_state = &state->conn_state; 3579 struct crtc_state *cstate = &state->crtc_state; 3580 struct drm_display_mode *mode = &conn_state->mode; 3581 struct videomode vm; 3582 3583 drm_display_mode_to_videomode(mode, &vm); 3584 3585 if (vm.hactive < 32 || vm.vactive < 32 || 3586 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 3587 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 3588 printf("ERROR: VP%d: unsupported display timing\n", cstate->crtc_id); 3589 return -EINVAL; 3590 } 3591 3592 return 0; 3593 } 3594 3595 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 3596 3597 static int rockchip_vop2_plane_check(struct display_state *state) 3598 { 3599 struct crtc_state *cstate = &state->crtc_state; 3600 struct vop2 *vop2 = cstate->private; 3601 struct display_rect *src = &cstate->src_rect; 3602 struct display_rect *dst = &cstate->crtc_rect; 3603 struct vop2_win_data *win_data; 3604 int min_scale, max_scale; 3605 int hscale, vscale; 3606 u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id; 3607 3608 win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id); 3609 if (!win_data) { 3610 printf("ERROR: invalid win id %d\n", primary_plane_id); 3611 return -ENODEV; 3612 } 3613 3614 min_scale = FRAC_16_16(1, win_data->max_downscale_factor); 3615 max_scale = FRAC_16_16(win_data->max_upscale_factor, 1); 3616 3617 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 3618 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 3619 if (hscale < 0 || vscale < 0) { 3620 printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name); 3621 return -ERANGE; 3622 } 3623 3624 return 0; 3625 } 3626 static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3627 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3628 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3629 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3630 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3631 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3632 {ROCKCHIP_VOP2_SMART0, SMART_LAYER}, 3633 }; 3634 3635 static struct vop2_vp_plane_mask rk356x_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3636 { /* one display policy */ 3637 {/* main display */ 3638 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3639 .attached_layers_nr = 6, 3640 .attached_layers = { 3641 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0, 3642 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3643 }, 3644 }, 3645 {/* second display */}, 3646 {/* third display */}, 3647 {/* fourth display */}, 3648 }, 3649 3650 { /* two display policy */ 3651 {/* main display */ 3652 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3653 .attached_layers_nr = 3, 3654 .attached_layers = { 3655 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3656 }, 3657 }, 3658 3659 {/* second display */ 3660 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3661 .attached_layers_nr = 3, 3662 .attached_layers = { 3663 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_SMART1 3664 }, 3665 }, 3666 {/* third display */}, 3667 {/* fourth display */}, 3668 }, 3669 3670 { /* three display policy */ 3671 {/* main display */ 3672 .primary_plane_id = ROCKCHIP_VOP2_SMART0, 3673 .attached_layers_nr = 3, 3674 .attached_layers = { 3675 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_SMART0 3676 }, 3677 }, 3678 3679 {/* second display */ 3680 .primary_plane_id = ROCKCHIP_VOP2_SMART1, 3681 .attached_layers_nr = 2, 3682 .attached_layers = { 3683 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_SMART1 3684 }, 3685 }, 3686 3687 {/* third display */ 3688 .primary_plane_id = ROCKCHIP_VOP2_ESMART1, 3689 .attached_layers_nr = 1, 3690 .attached_layers = { ROCKCHIP_VOP2_ESMART1 }, 3691 }, 3692 3693 {/* fourth display */}, 3694 }, 3695 3696 {/* reserved for four display policy */}, 3697 }; 3698 3699 static struct vop2_win_data rk3568_win_data[6] = { 3700 { 3701 .name = "Cluster0", 3702 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3703 .type = CLUSTER_LAYER, 3704 .win_sel_port_offset = 0, 3705 .layer_sel_win_id = 0, 3706 .reg_offset = 0, 3707 .max_upscale_factor = 4, 3708 .max_downscale_factor = 4, 3709 }, 3710 3711 { 3712 .name = "Cluster1", 3713 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3714 .type = CLUSTER_LAYER, 3715 .win_sel_port_offset = 1, 3716 .layer_sel_win_id = 1, 3717 .reg_offset = 0x200, 3718 .max_upscale_factor = 4, 3719 .max_downscale_factor = 4, 3720 }, 3721 3722 { 3723 .name = "Esmart0", 3724 .phys_id = ROCKCHIP_VOP2_ESMART0, 3725 .type = ESMART_LAYER, 3726 .win_sel_port_offset = 4, 3727 .layer_sel_win_id = 2, 3728 .reg_offset = 0, 3729 .max_upscale_factor = 8, 3730 .max_downscale_factor = 8, 3731 }, 3732 3733 { 3734 .name = "Esmart1", 3735 .phys_id = ROCKCHIP_VOP2_ESMART1, 3736 .type = ESMART_LAYER, 3737 .win_sel_port_offset = 5, 3738 .layer_sel_win_id = 6, 3739 .reg_offset = 0x200, 3740 .max_upscale_factor = 8, 3741 .max_downscale_factor = 8, 3742 }, 3743 3744 { 3745 .name = "Smart0", 3746 .phys_id = ROCKCHIP_VOP2_SMART0, 3747 .type = SMART_LAYER, 3748 .win_sel_port_offset = 6, 3749 .layer_sel_win_id = 3, 3750 .reg_offset = 0x400, 3751 .max_upscale_factor = 8, 3752 .max_downscale_factor = 8, 3753 }, 3754 3755 { 3756 .name = "Smart1", 3757 .phys_id = ROCKCHIP_VOP2_SMART1, 3758 .type = SMART_LAYER, 3759 .win_sel_port_offset = 7, 3760 .layer_sel_win_id = 7, 3761 .reg_offset = 0x600, 3762 .max_upscale_factor = 8, 3763 .max_downscale_factor = 8, 3764 }, 3765 }; 3766 3767 static struct vop2_vp_data rk3568_vp_data[3] = { 3768 { 3769 .feature = VOP_FEATURE_OUTPUT_10BIT, 3770 .pre_scan_max_dly = 42, 3771 .max_output = {4096, 2304}, 3772 }, 3773 { 3774 .feature = 0, 3775 .pre_scan_max_dly = 40, 3776 .max_output = {2048, 1536}, 3777 }, 3778 { 3779 .feature = 0, 3780 .pre_scan_max_dly = 40, 3781 .max_output = {1920, 1080}, 3782 }, 3783 }; 3784 3785 const struct vop2_data rk3568_vop = { 3786 .version = VOP_VERSION_RK3568, 3787 .nr_vps = 3, 3788 .vp_data = rk3568_vp_data, 3789 .win_data = rk3568_win_data, 3790 .plane_mask = rk356x_vp_plane_mask[0], 3791 .plane_table = rk356x_plane_table, 3792 .nr_layers = 6, 3793 .nr_mixers = 5, 3794 .nr_gammas = 1, 3795 }; 3796 3797 static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = { 3798 {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER}, 3799 {ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER}, 3800 {ROCKCHIP_VOP2_CLUSTER2, CLUSTER_LAYER}, 3801 {ROCKCHIP_VOP2_CLUSTER3, CLUSTER_LAYER}, 3802 {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER}, 3803 {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER}, 3804 {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER}, 3805 {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER}, 3806 }; 3807 3808 static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = { 3809 { /* one display policy */ 3810 {/* main display */ 3811 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3812 .attached_layers_nr = 8, 3813 .attached_layers = { 3814 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2, 3815 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART3, 3816 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3 3817 }, 3818 }, 3819 {/* second display */}, 3820 {/* third display */}, 3821 {/* fourth display */}, 3822 }, 3823 3824 { /* two display policy */ 3825 {/* main display */ 3826 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3827 .attached_layers_nr = 4, 3828 .attached_layers = { 3829 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, 3830 ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 3831 }, 3832 }, 3833 3834 {/* second display */ 3835 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3836 .attached_layers_nr = 4, 3837 .attached_layers = { 3838 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2, 3839 ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 3840 }, 3841 }, 3842 {/* third display */}, 3843 {/* fourth display */}, 3844 }, 3845 3846 { /* three display policy */ 3847 {/* main display */ 3848 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3849 .attached_layers_nr = 3, 3850 .attached_layers = { 3851 ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0 3852 }, 3853 }, 3854 3855 {/* second display */ 3856 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3857 .attached_layers_nr = 3, 3858 .attached_layers = { 3859 ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1 3860 }, 3861 }, 3862 3863 {/* third display */ 3864 .primary_plane_id = ROCKCHIP_VOP2_ESMART2, 3865 .attached_layers_nr = 2, 3866 .attached_layers = { ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3 }, 3867 }, 3868 3869 {/* fourth display */}, 3870 }, 3871 3872 { /* four display policy */ 3873 {/* main display */ 3874 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0, 3875 .attached_layers_nr = 2, 3876 .attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 }, 3877 }, 3878 3879 {/* second display */ 3880 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1, 3881 .attached_layers_nr = 2, 3882 .attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 }, 3883 }, 3884 3885 {/* third display */ 3886 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2, 3887 .attached_layers_nr = 2, 3888 .attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 }, 3889 }, 3890 3891 {/* fourth display */ 3892 .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3, 3893 .attached_layers_nr = 2, 3894 .attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 }, 3895 }, 3896 }, 3897 3898 }; 3899 3900 static struct vop2_win_data rk3588_win_data[8] = { 3901 { 3902 .name = "Cluster0", 3903 .phys_id = ROCKCHIP_VOP2_CLUSTER0, 3904 .splice_win_id = ROCKCHIP_VOP2_CLUSTER1, 3905 .type = CLUSTER_LAYER, 3906 .win_sel_port_offset = 0, 3907 .layer_sel_win_id = 0, 3908 .reg_offset = 0, 3909 .axi_id = 0, 3910 .axi_yrgb_id = 2, 3911 .axi_uv_id = 3, 3912 .pd_id = VOP2_PD_CLUSTER0, 3913 .max_upscale_factor = 4, 3914 .max_downscale_factor = 4, 3915 }, 3916 3917 { 3918 .name = "Cluster1", 3919 .phys_id = ROCKCHIP_VOP2_CLUSTER1, 3920 .type = CLUSTER_LAYER, 3921 .win_sel_port_offset = 1, 3922 .layer_sel_win_id = 1, 3923 .reg_offset = 0x200, 3924 .axi_id = 0, 3925 .axi_yrgb_id = 6, 3926 .axi_uv_id = 7, 3927 .pd_id = VOP2_PD_CLUSTER1, 3928 .max_upscale_factor = 4, 3929 .max_downscale_factor = 4, 3930 }, 3931 3932 { 3933 .name = "Cluster2", 3934 .phys_id = ROCKCHIP_VOP2_CLUSTER2, 3935 .splice_win_id = ROCKCHIP_VOP2_CLUSTER3, 3936 .type = CLUSTER_LAYER, 3937 .win_sel_port_offset = 2, 3938 .layer_sel_win_id = 4, 3939 .reg_offset = 0x400, 3940 .axi_id = 1, 3941 .axi_yrgb_id = 2, 3942 .axi_uv_id = 3, 3943 .pd_id = VOP2_PD_CLUSTER2, 3944 .max_upscale_factor = 4, 3945 .max_downscale_factor = 4, 3946 }, 3947 3948 { 3949 .name = "Cluster3", 3950 .phys_id = ROCKCHIP_VOP2_CLUSTER3, 3951 .type = CLUSTER_LAYER, 3952 .win_sel_port_offset = 3, 3953 .layer_sel_win_id = 5, 3954 .reg_offset = 0x600, 3955 .axi_id = 1, 3956 .axi_yrgb_id = 6, 3957 .axi_uv_id = 7, 3958 .pd_id = VOP2_PD_CLUSTER3, 3959 .max_upscale_factor = 4, 3960 .max_downscale_factor = 4, 3961 }, 3962 3963 { 3964 .name = "Esmart0", 3965 .phys_id = ROCKCHIP_VOP2_ESMART0, 3966 .splice_win_id = ROCKCHIP_VOP2_ESMART1, 3967 .type = ESMART_LAYER, 3968 .win_sel_port_offset = 4, 3969 .layer_sel_win_id = 2, 3970 .reg_offset = 0, 3971 .axi_id = 0, 3972 .axi_yrgb_id = 0x0a, 3973 .axi_uv_id = 0x0b, 3974 .max_upscale_factor = 8, 3975 .max_downscale_factor = 8, 3976 }, 3977 3978 { 3979 .name = "Esmart1", 3980 .phys_id = ROCKCHIP_VOP2_ESMART1, 3981 .type = ESMART_LAYER, 3982 .win_sel_port_offset = 5, 3983 .layer_sel_win_id = 3, 3984 .reg_offset = 0x200, 3985 .axi_id = 0, 3986 .axi_yrgb_id = 0x0c, 3987 .axi_uv_id = 0x0d, 3988 .pd_id = VOP2_PD_ESMART, 3989 .max_upscale_factor = 8, 3990 .max_downscale_factor = 8, 3991 }, 3992 3993 { 3994 .name = "Esmart2", 3995 .phys_id = ROCKCHIP_VOP2_ESMART2, 3996 .splice_win_id = ROCKCHIP_VOP2_ESMART3, 3997 .type = ESMART_LAYER, 3998 .win_sel_port_offset = 6, 3999 .layer_sel_win_id = 6, 4000 .reg_offset = 0x400, 4001 .axi_id = 1, 4002 .axi_yrgb_id = 0x0a, 4003 .axi_uv_id = 0x0b, 4004 .pd_id = VOP2_PD_ESMART, 4005 .max_upscale_factor = 8, 4006 .max_downscale_factor = 8, 4007 }, 4008 4009 { 4010 .name = "Esmart3", 4011 .phys_id = ROCKCHIP_VOP2_ESMART3, 4012 .type = ESMART_LAYER, 4013 .win_sel_port_offset = 7, 4014 .layer_sel_win_id = 7, 4015 .reg_offset = 0x600, 4016 .axi_id = 1, 4017 .axi_yrgb_id = 0x0c, 4018 .axi_uv_id = 0x0d, 4019 .pd_id = VOP2_PD_ESMART, 4020 .max_upscale_factor = 8, 4021 .max_downscale_factor = 8, 4022 }, 4023 }; 4024 4025 static struct dsc_error_info dsc_ecw[] = { 4026 {0x00000000, "no error detected by DSC encoder"}, 4027 {0x0030ffff, "bits per component error"}, 4028 {0x0040ffff, "multiple mode error"}, 4029 {0x0050ffff, "line buffer depth error"}, 4030 {0x0060ffff, "minor version error"}, 4031 {0x0070ffff, "picture height error"}, 4032 {0x0080ffff, "picture width error"}, 4033 {0x0090ffff, "number of slices error"}, 4034 {0x00c0ffff, "slice height Error "}, 4035 {0x00d0ffff, "slice width error"}, 4036 {0x00e0ffff, "second line BPG offset error"}, 4037 {0x00f0ffff, "non second line BPG offset error"}, 4038 {0x0100ffff, "PPS ID error"}, 4039 {0x0110ffff, "bits per pixel (BPP) Error"}, 4040 {0x0120ffff, "buffer flow error"}, /* dsc_buffer_flow */ 4041 4042 {0x01510001, "slice 0 RC buffer model overflow error"}, 4043 {0x01510002, "slice 1 RC buffer model overflow error"}, 4044 {0x01510004, "slice 2 RC buffer model overflow error"}, 4045 {0x01510008, "slice 3 RC buffer model overflow error"}, 4046 {0x01510010, "slice 4 RC buffer model overflow error"}, 4047 {0x01510020, "slice 5 RC buffer model overflow error"}, 4048 {0x01510040, "slice 6 RC buffer model overflow error"}, 4049 {0x01510080, "slice 7 RC buffer model overflow error"}, 4050 4051 {0x01610001, "slice 0 RC buffer model underflow error"}, 4052 {0x01610002, "slice 1 RC buffer model underflow error"}, 4053 {0x01610004, "slice 2 RC buffer model underflow error"}, 4054 {0x01610008, "slice 3 RC buffer model underflow error"}, 4055 {0x01610010, "slice 4 RC buffer model underflow error"}, 4056 {0x01610020, "slice 5 RC buffer model underflow error"}, 4057 {0x01610040, "slice 6 RC buffer model underflow error"}, 4058 {0x01610080, "slice 7 RC buffer model underflow error"}, 4059 4060 {0xffffffff, "unsuccessful RESET cycle status"}, 4061 {0x00a0ffff, "ICH full error precision settings error"}, 4062 {0x0020ffff, "native mode"}, 4063 }; 4064 4065 static struct dsc_error_info dsc_buffer_flow[] = { 4066 {0x00000000, "rate buffer status"}, 4067 {0x00000001, "line buffer status"}, 4068 {0x00000002, "decoder model status"}, 4069 {0x00000003, "pixel buffer status"}, 4070 {0x00000004, "balance fifo buffer status"}, 4071 {0x00000005, "syntax element fifo status"}, 4072 }; 4073 4074 static struct vop2_dsc_data rk3588_dsc_data[] = { 4075 { 4076 .id = ROCKCHIP_VOP2_DSC_8K, 4077 .pd_id = VOP2_PD_DSC_8K, 4078 .max_slice_num = 8, 4079 .max_linebuf_depth = 11, 4080 .min_bits_per_pixel = 8, 4081 .dsc_txp_clk_src_name = "dsc_8k_txp_clk_src", 4082 .dsc_txp_clk_name = "dsc_8k_txp_clk", 4083 .dsc_pxl_clk_name = "dsc_8k_pxl_clk", 4084 .dsc_cds_clk_name = "dsc_8k_cds_clk", 4085 }, 4086 4087 { 4088 .id = ROCKCHIP_VOP2_DSC_4K, 4089 .pd_id = VOP2_PD_DSC_4K, 4090 .max_slice_num = 2, 4091 .max_linebuf_depth = 11, 4092 .min_bits_per_pixel = 8, 4093 .dsc_txp_clk_src_name = "dsc_4k_txp_clk_src", 4094 .dsc_txp_clk_name = "dsc_4k_txp_clk", 4095 .dsc_pxl_clk_name = "dsc_4k_pxl_clk", 4096 .dsc_cds_clk_name = "dsc_4k_cds_clk", 4097 }, 4098 }; 4099 4100 static struct vop2_vp_data rk3588_vp_data[4] = { 4101 { 4102 .splice_vp_id = 1, 4103 .feature = VOP_FEATURE_OUTPUT_10BIT, 4104 .pre_scan_max_dly = 54, 4105 .max_dclk = 600000, 4106 .max_output = {7680, 4320}, 4107 }, 4108 { 4109 .feature = VOP_FEATURE_OUTPUT_10BIT, 4110 .pre_scan_max_dly = 54, 4111 .max_dclk = 600000, 4112 .max_output = {4096, 2304}, 4113 }, 4114 { 4115 .feature = VOP_FEATURE_OUTPUT_10BIT, 4116 .pre_scan_max_dly = 52, 4117 .max_dclk = 600000, 4118 .max_output = {4096, 2304}, 4119 }, 4120 { 4121 .feature = 0, 4122 .pre_scan_max_dly = 52, 4123 .max_dclk = 200000, 4124 .max_output = {1920, 1080}, 4125 }, 4126 }; 4127 4128 static struct vop2_power_domain_data rk3588_vop_pd_data[] = { 4129 { 4130 .id = VOP2_PD_CLUSTER0, 4131 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER0), 4132 }, 4133 { 4134 .id = VOP2_PD_CLUSTER1, 4135 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER1), 4136 .parent_id = VOP2_PD_CLUSTER0, 4137 }, 4138 { 4139 .id = VOP2_PD_CLUSTER2, 4140 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER2), 4141 .parent_id = VOP2_PD_CLUSTER0, 4142 }, 4143 { 4144 .id = VOP2_PD_CLUSTER3, 4145 .module_id_mask = BIT(ROCKCHIP_VOP2_CLUSTER3), 4146 .parent_id = VOP2_PD_CLUSTER0, 4147 }, 4148 { 4149 .id = VOP2_PD_ESMART, 4150 .module_id_mask = BIT(ROCKCHIP_VOP2_ESMART1) | 4151 BIT(ROCKCHIP_VOP2_ESMART2) | 4152 BIT(ROCKCHIP_VOP2_ESMART3), 4153 }, 4154 { 4155 .id = VOP2_PD_DSC_8K, 4156 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_8K), 4157 }, 4158 { 4159 .id = VOP2_PD_DSC_4K, 4160 .module_id_mask = BIT(ROCKCHIP_VOP2_DSC_4K), 4161 }, 4162 }; 4163 4164 const struct vop2_data rk3588_vop = { 4165 .version = VOP_VERSION_RK3588, 4166 .nr_vps = 4, 4167 .vp_data = rk3588_vp_data, 4168 .win_data = rk3588_win_data, 4169 .plane_mask = rk3588_vp_plane_mask[0], 4170 .plane_table = rk3588_plane_table, 4171 .pd = rk3588_vop_pd_data, 4172 .dsc = rk3588_dsc_data, 4173 .dsc_error_ecw = dsc_ecw, 4174 .dsc_error_buffer_flow = dsc_buffer_flow, 4175 .nr_layers = 8, 4176 .nr_mixers = 7, 4177 .nr_gammas = 4, 4178 .nr_pd = ARRAY_SIZE(rk3588_vop_pd_data), 4179 .nr_dscs = 2, 4180 .nr_dsc_ecw = ARRAY_SIZE(dsc_ecw), 4181 .nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow), 4182 }; 4183 4184 const struct rockchip_crtc_funcs rockchip_vop2_funcs = { 4185 .preinit = rockchip_vop2_preinit, 4186 .prepare = rockchip_vop2_prepare, 4187 .init = rockchip_vop2_init, 4188 .set_plane = rockchip_vop2_set_plane, 4189 .enable = rockchip_vop2_enable, 4190 .disable = rockchip_vop2_disable, 4191 .fixup_dts = rockchip_vop2_fixup_dts, 4192 .check = rockchip_vop2_check, 4193 .mode_valid = rockchip_vop2_mode_valid, 4194 .plane_check = rockchip_vop2_plane_check, 4195 }; 4196