1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <boot_rkimg.h> 9 #include <asm/io.h> 10 #include <dm/device.h> 11 #include <linux/dw_hdmi.h> 12 #include <linux/hdmi.h> 13 #include <linux/media-bus-format.h> 14 #include "rockchip_display.h" 15 #include "rockchip_crtc.h" 16 #include "rockchip_connector.h" 17 #include "dw_hdmi.h" 18 #include "rockchip_dw_hdmi.h" 19 20 #define HDMI_SEL_LCDC(x, bit) ((((x) & 1) << bit) | (1 << (16 + bit))) 21 #define RK3288_GRF_SOC_CON6 0x025C 22 #define RK3288_HDMI_LCDC_SEL BIT(4) 23 #define RK3399_GRF_SOC_CON20 0x6250 24 #define RK3399_HDMI_LCDC_SEL BIT(6) 25 26 #define RK3228_IO_3V_DOMAIN ((7 << 4) | (7 << (4 + 16))) 27 #define RK3328_IO_3V_DOMAIN (7 << (9 + 16)) 28 #define RK3328_IO_5V_DOMAIN ((7 << 9) | (3 << (9 + 16))) 29 #define RK3328_IO_CTRL_BY_HDMI ((1 << 13) | (1 << (13 + 16))) 30 #define RK3328_IO_DDC_IN_MSK ((3 << 10) | (3 << (10 + 16))) 31 #define RK3228_IO_DDC_IN_MSK ((3 << 13) | (3 << (13 + 16))) 32 #define RK3228_GRF_SOC_CON2 0x0408 33 #define RK3228_GRF_SOC_CON6 0x0418 34 #define RK3328_GRF_SOC_CON2 0x0408 35 #define RK3328_GRF_SOC_CON3 0x040c 36 #define RK3328_GRF_SOC_CON4 0x0410 37 38 #define RK3568_GRF_VO_CON1 0x0364 39 #define RK3568_HDMI_SDAIN_MSK ((1 << 15) | (1 << (15 + 16))) 40 #define RK3568_HDMI_SCLIN_MSK ((1 << 14) | (1 << (14 + 16))) 41 42 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = { 43 { 44 30666000, { 45 { 0x00b3, 0x0000 }, 46 { 0x2153, 0x0000 }, 47 { 0x40f3, 0x0000 }, 48 }, 49 }, { 50 36800000, { 51 { 0x00b3, 0x0000 }, 52 { 0x2153, 0x0000 }, 53 { 0x40a2, 0x0001 }, 54 }, 55 }, { 56 46000000, { 57 { 0x00b3, 0x0000 }, 58 { 0x2142, 0x0001 }, 59 { 0x40a2, 0x0001 }, 60 }, 61 }, { 62 61333000, { 63 { 0x0072, 0x0001 }, 64 { 0x2142, 0x0001 }, 65 { 0x40a2, 0x0001 }, 66 }, 67 }, { 68 73600000, { 69 { 0x0072, 0x0001 }, 70 { 0x2142, 0x0001 }, 71 { 0x4061, 0x0002 }, 72 }, 73 }, { 74 92000000, { 75 { 0x0072, 0x0001 }, 76 { 0x2145, 0x0002 }, 77 { 0x4061, 0x0002 }, 78 }, 79 }, { 80 122666000, { 81 { 0x0051, 0x0002 }, 82 { 0x2145, 0x0002 }, 83 { 0x4061, 0x0002 }, 84 }, 85 }, { 86 147200000, { 87 { 0x0051, 0x0002 }, 88 { 0x2145, 0x0002 }, 89 { 0x4064, 0x0003 }, 90 }, 91 }, { 92 184000000, { 93 { 0x0051, 0x0002 }, 94 { 0x214c, 0x0003 }, 95 { 0x4064, 0x0003 }, 96 }, 97 }, { 98 226666000, { 99 { 0x0040, 0x0003 }, 100 { 0x214c, 0x0003 }, 101 { 0x4064, 0x0003 }, 102 }, 103 }, { 104 272000000, { 105 { 0x0040, 0x0003 }, 106 { 0x214c, 0x0003 }, 107 { 0x5a64, 0x0003 }, 108 }, 109 }, { 110 340000000, { 111 { 0x0040, 0x0003 }, 112 { 0x3b4c, 0x0003 }, 113 { 0x5a64, 0x0003 }, 114 }, 115 }, { 116 600000000, { 117 { 0x1a40, 0x0003 }, 118 { 0x3b4c, 0x0003 }, 119 { 0x5a64, 0x0003 }, 120 }, 121 }, { 122 ~0UL, { 123 { 0x0000, 0x0000 }, 124 { 0x0000, 0x0000 }, 125 { 0x0000, 0x0000 }, 126 }, 127 } 128 }; 129 130 static const struct dw_hdmi_mpll_config rockchip_mpll_cfg_420[] = { 131 { 132 30666000, { 133 { 0x00b7, 0x0000 }, 134 { 0x2157, 0x0000 }, 135 { 0x40f7, 0x0000 }, 136 }, 137 }, { 138 92000000, { 139 { 0x00b7, 0x0000 }, 140 { 0x2143, 0x0001 }, 141 { 0x40a3, 0x0001 }, 142 }, 143 }, { 144 184000000, { 145 { 0x0073, 0x0001 }, 146 { 0x2146, 0x0002 }, 147 { 0x4062, 0x0002 }, 148 }, 149 }, { 150 340000000, { 151 { 0x0052, 0x0003 }, 152 { 0x214d, 0x0003 }, 153 { 0x4065, 0x0003 }, 154 }, 155 }, { 156 600000000, { 157 { 0x0041, 0x0003 }, 158 { 0x3b4d, 0x0003 }, 159 { 0x5a65, 0x0003 }, 160 }, 161 }, { 162 ~0UL, { 163 { 0x0000, 0x0000 }, 164 { 0x0000, 0x0000 }, 165 { 0x0000, 0x0000 }, 166 }, 167 } 168 }; 169 170 static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = { 171 /* pixelclk bpp8 bpp10 bpp12 */ 172 { 173 600000000, { 0x0000, 0x0000, 0x0000 }, 174 }, { 175 ~0UL, { 0x0000, 0x0000, 0x0000}, 176 } 177 }; 178 179 static const struct dw_hdmi_phy_config rockchip_phy_config[] = { 180 /*pixelclk symbol term vlev*/ 181 { 74250000, 0x8009, 0x0004, 0x0272}, 182 { 165000000, 0x802b, 0x0004, 0x0209}, 183 { 297000000, 0x8039, 0x0005, 0x028d}, 184 { 594000000, 0x8039, 0x0000, 0x019d}, 185 { ~0UL, 0x0000, 0x0000, 0x0000}, 186 { ~0UL, 0x0000, 0x0000, 0x0000} 187 }; 188 189 static unsigned int drm_rk_select_color(struct hdmi_edid_data *edid_data, 190 struct base_screen_info *screen_info, 191 enum dw_hdmi_devtype dev_type) 192 { 193 struct drm_display_info *info = &edid_data->display_info; 194 struct drm_display_mode *mode = edid_data->preferred_mode; 195 int max_tmds_clock = info->max_tmds_clock; 196 bool support_dc = false; 197 bool mode_420 = drm_mode_is_420(info, mode); 198 unsigned int color_depth = 8; 199 unsigned int base_color = DRM_HDMI_OUTPUT_YCBCR444; 200 unsigned int color_format = DRM_HDMI_OUTPUT_DEFAULT_RGB; 201 unsigned long tmdsclock, pixclock = mode->clock; 202 203 if (screen_info) 204 base_color = screen_info->format; 205 206 switch (base_color) { 207 case DRM_HDMI_OUTPUT_YCBCR_HQ: 208 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 209 color_format = DRM_HDMI_OUTPUT_YCBCR444; 210 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 211 color_format = DRM_HDMI_OUTPUT_YCBCR422; 212 else if (mode_420) 213 color_format = DRM_HDMI_OUTPUT_YCBCR420; 214 break; 215 case DRM_HDMI_OUTPUT_YCBCR_LQ: 216 if (mode_420) 217 color_format = DRM_HDMI_OUTPUT_YCBCR420; 218 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 219 color_format = DRM_HDMI_OUTPUT_YCBCR422; 220 else if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 221 color_format = DRM_HDMI_OUTPUT_YCBCR444; 222 break; 223 case DRM_HDMI_OUTPUT_YCBCR420: 224 if (mode_420) 225 color_format = DRM_HDMI_OUTPUT_YCBCR420; 226 break; 227 case DRM_HDMI_OUTPUT_YCBCR422: 228 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) 229 color_format = DRM_HDMI_OUTPUT_YCBCR422; 230 break; 231 case DRM_HDMI_OUTPUT_YCBCR444: 232 if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) 233 color_format = DRM_HDMI_OUTPUT_YCBCR444; 234 break; 235 case DRM_HDMI_OUTPUT_DEFAULT_RGB: 236 default: 237 break; 238 } 239 240 if (color_format == DRM_HDMI_OUTPUT_DEFAULT_RGB && 241 info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) 242 support_dc = true; 243 if (color_format == DRM_HDMI_OUTPUT_YCBCR444 && 244 (info->edid_hdmi_dc_modes & 245 (DRM_EDID_HDMI_DC_Y444 | DRM_EDID_HDMI_DC_30))) 246 support_dc = true; 247 if (color_format == DRM_HDMI_OUTPUT_YCBCR422) 248 support_dc = true; 249 if (color_format == DRM_HDMI_OUTPUT_YCBCR420 && 250 info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) 251 support_dc = true; 252 253 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 254 pixclock *= 2; 255 256 if (screen_info && screen_info->depth == 10) 257 color_depth = screen_info->depth; 258 259 if (color_format == DRM_HDMI_OUTPUT_YCBCR422 || color_depth == 8) 260 tmdsclock = pixclock; 261 else 262 tmdsclock = pixclock * color_depth / 8; 263 264 if (color_format == DRM_HDMI_OUTPUT_YCBCR420) 265 tmdsclock /= 2; 266 267 if (!max_tmds_clock) 268 max_tmds_clock = 340000; 269 270 switch (dev_type) { 271 case RK3368_HDMI: 272 max_tmds_clock = min(max_tmds_clock, 340000); 273 break; 274 case RK3328_HDMI: 275 case RK3228_HDMI: 276 max_tmds_clock = min(max_tmds_clock, 371250); 277 break; 278 default: 279 max_tmds_clock = min(max_tmds_clock, 594000); 280 break; 281 } 282 283 if (tmdsclock > max_tmds_clock) { 284 if (max_tmds_clock >= 594000) { 285 color_depth = 8; 286 } else if (max_tmds_clock > 340000) { 287 if (drm_mode_is_420(info, mode)) 288 color_format = DRM_HDMI_OUTPUT_YCBCR420; 289 } else { 290 color_depth = 8; 291 if (drm_mode_is_420(info, mode)) 292 color_format = DRM_HDMI_OUTPUT_YCBCR420; 293 } 294 } 295 296 if (color_depth > 8 && support_dc) { 297 if (dev_type == RK3288_HDMI) 298 return MEDIA_BUS_FMT_RGB101010_1X30; 299 switch (color_format) { 300 case DRM_HDMI_OUTPUT_YCBCR444: 301 return MEDIA_BUS_FMT_YUV10_1X30; 302 case DRM_HDMI_OUTPUT_YCBCR422: 303 return MEDIA_BUS_FMT_UYVY10_1X20; 304 case DRM_HDMI_OUTPUT_YCBCR420: 305 return MEDIA_BUS_FMT_UYYVYY10_0_5X30; 306 default: 307 return MEDIA_BUS_FMT_RGB101010_1X30; 308 } 309 } else { 310 if (dev_type == RK3288_HDMI) 311 return MEDIA_BUS_FMT_RGB888_1X24; 312 switch (color_format) { 313 case DRM_HDMI_OUTPUT_YCBCR444: 314 return MEDIA_BUS_FMT_YUV8_1X24; 315 case DRM_HDMI_OUTPUT_YCBCR422: 316 return MEDIA_BUS_FMT_UYVY8_1X16; 317 case DRM_HDMI_OUTPUT_YCBCR420: 318 return MEDIA_BUS_FMT_UYYVYY8_0_5X24; 319 default: 320 return MEDIA_BUS_FMT_RGB888_1X24; 321 } 322 } 323 } 324 325 void drm_rk_selete_output(struct hdmi_edid_data *edid_data, 326 unsigned int *bus_format, 327 struct overscan *overscan, 328 enum dw_hdmi_devtype dev_type) 329 { 330 int ret, i, screen_size; 331 struct base_disp_info base_parameter; 332 const struct base_overscan *scan; 333 struct base_screen_info *screen_info = NULL; 334 int max_scan = 100; 335 int min_scan = 51; 336 struct blk_desc *dev_desc; 337 disk_partition_t part_info; 338 char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN); 339 340 overscan->left_margin = max_scan; 341 overscan->right_margin = max_scan; 342 overscan->top_margin = max_scan; 343 overscan->bottom_margin = max_scan; 344 345 if (dev_type == RK3288_HDMI) 346 *bus_format = MEDIA_BUS_FMT_RGB888_1X24; 347 else 348 *bus_format = MEDIA_BUS_FMT_YUV8_1X24; 349 350 dev_desc = rockchip_get_bootdev(); 351 if (!dev_desc) { 352 printf("%s: Could not find device\n", __func__); 353 return; 354 } 355 356 if (part_get_info_by_name(dev_desc, "baseparameter", &part_info) < 0) { 357 printf("Could not find baseparameter partition\n"); 358 return; 359 } 360 361 ret = blk_dread(dev_desc, part_info.start, 1, 362 (void *)baseparameter_buf); 363 if (ret < 0) { 364 printf("read baseparameter failed\n"); 365 return; 366 } 367 368 memcpy(&base_parameter, baseparameter_buf, sizeof(base_parameter)); 369 scan = &base_parameter.scan; 370 371 if (scan->leftscale < min_scan && scan->leftscale > 0) 372 overscan->left_margin = min_scan; 373 else if (scan->leftscale < max_scan && scan->leftscale > 0) 374 overscan->left_margin = scan->leftscale; 375 376 if (scan->rightscale < min_scan && scan->rightscale > 0) 377 overscan->right_margin = min_scan; 378 else if (scan->rightscale < max_scan && scan->rightscale > 0) 379 overscan->right_margin = scan->rightscale; 380 381 if (scan->topscale < min_scan && scan->topscale > 0) 382 overscan->top_margin = min_scan; 383 else if (scan->topscale < max_scan && scan->topscale > 0) 384 overscan->top_margin = scan->topscale; 385 386 if (scan->bottomscale < min_scan && scan->bottomscale > 0) 387 overscan->bottom_margin = min_scan; 388 else if (scan->bottomscale < max_scan && scan->bottomscale > 0) 389 overscan->bottom_margin = scan->bottomscale; 390 391 screen_size = sizeof(base_parameter.screen_list) / 392 sizeof(base_parameter.screen_list[0]); 393 394 for (i = 0; i < screen_size; i++) { 395 if (base_parameter.screen_list[i].type == 396 DRM_MODE_CONNECTOR_HDMIA) { 397 screen_info = &base_parameter.screen_list[i]; 398 break; 399 } 400 } 401 402 if (screen_info) 403 printf("base_parameter.mode:%dx%d\n", 404 screen_info->mode.hdisplay, 405 screen_info->mode.vdisplay); 406 drm_rk_select_mode(edid_data, screen_info); 407 408 *bus_format = drm_rk_select_color(edid_data, screen_info, 409 dev_type); 410 } 411 412 void inno_dw_hdmi_set_domain(void *grf, int status) 413 { 414 if (status) 415 writel(RK3328_IO_5V_DOMAIN, grf + RK3328_GRF_SOC_CON4); 416 else 417 writel(RK3328_IO_3V_DOMAIN, grf + RK3328_GRF_SOC_CON4); 418 } 419 420 void dw_hdmi_set_iomux(void *grf, int dev_type) 421 { 422 switch (dev_type) { 423 case RK3328_HDMI: 424 writel(RK3328_IO_DDC_IN_MSK, grf + RK3328_GRF_SOC_CON2); 425 writel(RK3328_IO_CTRL_BY_HDMI, grf + RK3328_GRF_SOC_CON3); 426 break; 427 case RK3228_HDMI: 428 writel(RK3228_IO_3V_DOMAIN, grf + RK3228_GRF_SOC_CON6); 429 writel(RK3228_IO_DDC_IN_MSK, grf + RK3228_GRF_SOC_CON2); 430 break; 431 case RK3568_HDMI: 432 writel(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK, 433 grf + RK3568_GRF_VO_CON1); 434 break; 435 default: 436 break; 437 } 438 } 439 440 static const struct dw_hdmi_phy_ops inno_dw_hdmi_phy_ops = { 441 .init = inno_dw_hdmi_phy_init, 442 .disable = inno_dw_hdmi_phy_disable, 443 .read_hpd = inno_dw_hdmi_phy_read_hpd, 444 .mode_valid = inno_dw_hdmi_mode_valid, 445 }; 446 447 static const struct rockchip_connector_funcs rockchip_dw_hdmi_funcs = { 448 .init = rockchip_dw_hdmi_init, 449 .deinit = rockchip_dw_hdmi_deinit, 450 .prepare = rockchip_dw_hdmi_prepare, 451 .enable = rockchip_dw_hdmi_enable, 452 .disable = rockchip_dw_hdmi_disable, 453 .get_timing = rockchip_dw_hdmi_get_timing, 454 .detect = rockchip_dw_hdmi_detect, 455 .get_edid = rockchip_dw_hdmi_get_edid, 456 }; 457 458 const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { 459 .vop_sel_bit = 4, 460 .grf_vop_sel_reg = RK3288_GRF_SOC_CON6, 461 .mpll_cfg = rockchip_mpll_cfg, 462 .cur_ctr = rockchip_cur_ctr, 463 .phy_config = rockchip_phy_config, 464 .dev_type = RK3288_HDMI, 465 }; 466 467 const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { 468 .vop_sel_bit = 0, 469 .grf_vop_sel_reg = 0, 470 .phy_ops = &inno_dw_hdmi_phy_ops, 471 .phy_name = "inno_dw_hdmi_phy2", 472 .dev_type = RK3328_HDMI, 473 }; 474 475 const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { 476 .vop_sel_bit = 0, 477 .grf_vop_sel_reg = 0, 478 .phy_ops = &inno_dw_hdmi_phy_ops, 479 .phy_name = "inno_dw_hdmi_phy", 480 .dev_type = RK3228_HDMI, 481 }; 482 483 const struct dw_hdmi_plat_data rk3368_hdmi_drv_data = { 484 .mpll_cfg = rockchip_mpll_cfg, 485 .cur_ctr = rockchip_cur_ctr, 486 .phy_config = rockchip_phy_config, 487 .mpll_cfg_420 = rockchip_mpll_cfg_420, 488 .dev_type = RK3368_HDMI, 489 }; 490 491 const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { 492 .vop_sel_bit = 6, 493 .grf_vop_sel_reg = RK3399_GRF_SOC_CON20, 494 .mpll_cfg = rockchip_mpll_cfg, 495 .cur_ctr = rockchip_cur_ctr, 496 .phy_config = rockchip_phy_config, 497 .mpll_cfg_420 = rockchip_mpll_cfg_420, 498 .dev_type = RK3399_HDMI, 499 }; 500 501 const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { 502 .vop_sel_bit = 0, 503 .grf_vop_sel_reg = 0, 504 .mpll_cfg = rockchip_mpll_cfg, 505 .cur_ctr = rockchip_cur_ctr, 506 .phy_config = rockchip_phy_config, 507 .mpll_cfg_420 = rockchip_mpll_cfg_420, 508 .dev_type = RK3568_HDMI, 509 }; 510 511 static int rockchip_dw_hdmi_probe(struct udevice *dev) 512 { 513 return 0; 514 } 515 516 static const struct rockchip_connector rk3568_dw_hdmi_data = { 517 .funcs = &rockchip_dw_hdmi_funcs, 518 .data = &rk3568_hdmi_drv_data, 519 }; 520 521 static const struct rockchip_connector rk3399_dw_hdmi_data = { 522 .funcs = &rockchip_dw_hdmi_funcs, 523 .data = &rk3399_hdmi_drv_data, 524 }; 525 526 static const struct rockchip_connector rk3368_dw_hdmi_data = { 527 .funcs = &rockchip_dw_hdmi_funcs, 528 .data = &rk3368_hdmi_drv_data, 529 }; 530 531 static const struct rockchip_connector rk3288_dw_hdmi_data = { 532 .funcs = &rockchip_dw_hdmi_funcs, 533 .data = &rk3288_hdmi_drv_data, 534 }; 535 536 static const struct rockchip_connector rk3328_dw_hdmi_data = { 537 .funcs = &rockchip_dw_hdmi_funcs, 538 .data = &rk3328_hdmi_drv_data, 539 }; 540 541 static const struct rockchip_connector rk3228_dw_hdmi_data = { 542 .funcs = &rockchip_dw_hdmi_funcs, 543 .data = &rk3228_hdmi_drv_data, 544 }; 545 546 static const struct udevice_id rockchip_dw_hdmi_ids[] = { 547 { 548 .compatible = "rockchip,rk3568-dw-hdmi", 549 .data = (ulong)&rk3568_dw_hdmi_data, 550 }, { 551 .compatible = "rockchip,rk3399-dw-hdmi", 552 .data = (ulong)&rk3399_dw_hdmi_data, 553 }, { 554 .compatible = "rockchip,rk3368-dw-hdmi", 555 .data = (ulong)&rk3368_dw_hdmi_data, 556 }, { 557 .compatible = "rockchip,rk3288-dw-hdmi", 558 .data = (ulong)&rk3288_dw_hdmi_data, 559 }, { 560 .compatible = "rockchip,rk3328-dw-hdmi", 561 .data = (ulong)&rk3328_dw_hdmi_data, 562 }, { 563 .compatible = "rockchip,rk3128-inno-hdmi", 564 .data = (ulong)&rk3228_dw_hdmi_data, 565 }, { 566 .compatible = "rockchip,rk3228-dw-hdmi", 567 .data = (ulong)&rk3228_dw_hdmi_data, 568 }, {} 569 }; 570 571 U_BOOT_DRIVER(rockchip_dw_hdmi) = { 572 .name = "rockchip_dw_hdmi", 573 .id = UCLASS_DISPLAY, 574 .of_match = rockchip_dw_hdmi_ids, 575 .probe = rockchip_dw_hdmi_probe, 576 }; 577