1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. 3 * 4 * (C) Copyright 2010 5 * Petr Stetiar <ynezz@true.cz> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 * 9 * Contains stolen code from ddcprobe project which is: 10 * Copyright (C) Nalin Dahyabhai <bigfun@pobox.com> 11 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 12 */ 13 14 #include <common.h> 15 #include <compiler.h> 16 #include <div64.h> 17 #include <drm_modes.h> 18 #include <edid.h> 19 #include <errno.h> 20 #include <fdtdec.h> 21 #include <hexdump.h> 22 #include <malloc.h> 23 #include <linux/compat.h> 24 #include <linux/ctype.h> 25 #include <linux/fb.h> 26 #include <linux/hdmi.h> 27 #include <linux/string.h> 28 29 #define EDID_EST_TIMINGS 16 30 #define EDID_STD_TIMINGS 8 31 #define EDID_DETAILED_TIMINGS 4 32 #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) 33 #define BITMAP_FIRST_WORD_MASK(start) (~0UL << ((start) & (BITS_PER_LONG - 1))) 34 #define BITMAP_LAST_WORD_MASK(nbits) (~0UL >> (-(nbits) & (BITS_PER_LONG - 1))) 35 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 36 #define version_greater(edid, maj, min) \ 37 (((edid)->version > (maj)) || \ 38 ((edid)->version == (maj) && (edid)->revision > (min))) 39 40 /* 41 * EDID blocks out in the wild have a variety of bugs, try to collect 42 * them here (note that userspace may work around broken monitors first, 43 * but fixes should make their way here so that the kernel "just works" 44 * on as many displays as possible). 45 */ 46 47 /* First detailed mode wrong, use largest 60Hz mode */ 48 #define EDID_QUIRK_PREFER_LARGE_60 BIT(0) 49 /* Reported 135MHz pixel clock is too high, needs adjustment */ 50 #define EDID_QUIRK_135_CLOCK_TOO_HIGH BIT(1) 51 /* Prefer the largest mode at 75 Hz */ 52 #define EDID_QUIRK_PREFER_LARGE_75 BIT(2) 53 /* Detail timing is in cm not mm */ 54 #define EDID_QUIRK_DETAILED_IN_CM BIT(3) 55 /* Detailed timing descriptors have bogus size values, so just take the 56 * maximum size and use that. 57 */ 58 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE BIT(4) 59 /* Monitor forgot to set the first detailed is preferred bit. */ 60 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED BIT(5) 61 /* use +hsync +vsync for detailed mode */ 62 #define EDID_QUIRK_DETAILED_SYNC_PP BIT(6) 63 /* Force reduced-blanking timings for detailed modes */ 64 #define EDID_QUIRK_FORCE_REDUCED_BLANKING BIT(7) 65 /* Force 8bpc */ 66 #define EDID_QUIRK_FORCE_8BPC BIT(8) 67 /* Force 12bpc */ 68 #define EDID_QUIRK_FORCE_12BPC BIT(9) 69 /* Force 6bpc */ 70 #define EDID_QUIRK_FORCE_6BPC BIT(10) 71 /* Force 10bpc */ 72 #define EDID_QUIRK_FORCE_10BPC BIT(11) 73 74 struct detailed_mode_closure { 75 struct edid *edid; 76 struct hdmi_edid_data *data; 77 bool preferred; 78 u32 quirks; 79 int modes; 80 }; 81 82 #define LEVEL_DMT 0 83 #define LEVEL_GTF 1 84 #define LEVEL_GTF2 2 85 #define LEVEL_CVT 3 86 87 static struct edid_quirk { 88 char vendor[4]; 89 int product_id; 90 u32 quirks; 91 } edid_quirk_list[] = { 92 /* Acer AL1706 */ 93 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 94 /* Acer F51 */ 95 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 96 /* Unknown Acer */ 97 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 98 99 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 100 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 101 102 /* Belinea 10 15 55 */ 103 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 104 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 105 106 /* Envision Peripherals, Inc. EN-7100e */ 107 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 108 /* Envision EN2028 */ 109 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 110 111 /* Funai Electronics PM36B */ 112 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 113 EDID_QUIRK_DETAILED_IN_CM }, 114 115 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 116 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 117 118 /* LG Philips LCD LP154W01-A5 */ 119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 122 /* Philips 107p5 CRT */ 123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 124 125 /* Proview AY765C */ 126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 127 128 /* Samsung SyncMaster 205BW. Note: irony */ 129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 130 /* Samsung SyncMaster 22[5-6]BW */ 131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 133 134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 136 137 /* ViewSonic VA2026w */ 138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 139 140 /* Medion MD 30217 PG */ 141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 142 143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 145 146 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 147 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 148 }; 149 150 /* 151 * Probably taken from CEA-861 spec. 152 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 153 * 154 * Index using the VIC. 155 */ 156 /* 157 * From CEA/CTA-861 spec. 158 * Do not access directly, instead always use cea_mode_for_vic(). 159 */ 160 static const struct drm_display_mode edid_cea_modes_1[] = { 161 /* 1 - 640x480@60Hz */ 162 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 163 752, 800, 480, 490, 492, 525, 0, 164 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 166 /* 2 - 720x480@60Hz */ 167 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 168 798, 858, 480, 489, 495, 525, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 170 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 171 /* 3 - 720x480@60Hz */ 172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 173 798, 858, 480, 489, 495, 525, 0, 174 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 175 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 176 /* 4 - 1280x720@60Hz */ 177 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 178 1430, 1650, 720, 725, 730, 750, 0, 179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 180 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 181 /* 5 - 1920x1080i@60Hz */ 182 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 183 2052, 2200, 1080, 1084, 1094, 1125, 0, 184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 185 DRM_MODE_FLAG_INTERLACE), 186 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 187 /* 6 - 720(1440)x480i@60Hz */ 188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 189 801, 858, 480, 488, 494, 525, 0, 190 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 191 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 192 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 193 /* 7 - 720(1440)x480i@60Hz */ 194 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 195 801, 858, 480, 488, 494, 525, 0, 196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 197 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 198 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 199 /* 8 - 720(1440)x240@60Hz */ 200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 201 801, 858, 240, 244, 247, 262, 0, 202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 203 DRM_MODE_FLAG_DBLCLK), 204 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 205 /* 9 - 720(1440)x240@60Hz */ 206 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 207 801, 858, 240, 244, 247, 262, 0, 208 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 209 DRM_MODE_FLAG_DBLCLK), 210 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 211 /* 10 - 2880x480i@60Hz */ 212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 213 3204, 3432, 480, 488, 494, 525, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 215 DRM_MODE_FLAG_INTERLACE), 216 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 217 /* 11 - 2880x480i@60Hz */ 218 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 219 3204, 3432, 480, 488, 494, 525, 0, 220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 221 DRM_MODE_FLAG_INTERLACE), 222 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 223 /* 12 - 2880x240@60Hz */ 224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 225 3204, 3432, 240, 244, 247, 262, 0, 226 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 227 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 228 /* 13 - 2880x240@60Hz */ 229 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 230 3204, 3432, 240, 244, 247, 262, 0, 231 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 232 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 233 /* 14 - 1440x480@60Hz */ 234 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 235 1596, 1716, 480, 489, 495, 525, 0, 236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 237 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 238 /* 15 - 1440x480@60Hz */ 239 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 240 1596, 1716, 480, 489, 495, 525, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 242 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 243 /* 16 - 1920x1080@60Hz */ 244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 245 2052, 2200, 1080, 1084, 1089, 1125, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 247 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 248 /* 17 - 720x576@50Hz */ 249 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 250 796, 864, 576, 581, 586, 625, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 252 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 253 /* 18 - 720x576@50Hz */ 254 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 255 796, 864, 576, 581, 586, 625, 0, 256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 257 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 258 /* 19 - 1280x720@50Hz */ 259 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 260 1760, 1980, 720, 725, 730, 750, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 262 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 263 /* 20 - 1920x1080i@50Hz */ 264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 265 2492, 2640, 1080, 1084, 1094, 1125, 0, 266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 267 DRM_MODE_FLAG_INTERLACE), 268 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 269 /* 21 - 720(1440)x576i@50Hz */ 270 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 271 795, 864, 576, 580, 586, 625, 0, 272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 273 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 274 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 275 /* 22 - 720(1440)x576i@50Hz */ 276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 277 795, 864, 576, 580, 586, 625, 0, 278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 279 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 280 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 281 /* 23 - 720(1440)x288@50Hz */ 282 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 283 795, 864, 288, 290, 293, 312, 0, 284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 285 DRM_MODE_FLAG_DBLCLK), 286 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 287 /* 24 - 720(1440)x288@50Hz */ 288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 289 795, 864, 288, 290, 293, 312, 0, 290 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 291 DRM_MODE_FLAG_DBLCLK), 292 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 293 /* 25 - 2880x576i@50Hz */ 294 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 295 3180, 3456, 576, 580, 586, 625, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 297 DRM_MODE_FLAG_INTERLACE), 298 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 299 /* 26 - 2880x576i@50Hz */ 300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 301 3180, 3456, 576, 580, 586, 625, 0, 302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 303 DRM_MODE_FLAG_INTERLACE), 304 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 305 /* 27 - 2880x288@50Hz */ 306 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 307 3180, 3456, 288, 290, 293, 312, 0, 308 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 309 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 310 /* 28 - 2880x288@50Hz */ 311 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 312 3180, 3456, 288, 290, 293, 312, 0, 313 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 314 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 315 /* 29 - 1440x576@50Hz */ 316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 317 1592, 1728, 576, 581, 586, 625, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 319 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 320 /* 30 - 1440x576@50Hz */ 321 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 322 1592, 1728, 576, 581, 586, 625, 0, 323 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 324 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 325 /* 31 - 1920x1080@50Hz */ 326 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 327 2492, 2640, 1080, 1084, 1089, 1125, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 329 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 330 /* 32 - 1920x1080@24Hz */ 331 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 332 2602, 2750, 1080, 1084, 1089, 1125, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 334 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 335 /* 33 - 1920x1080@25Hz */ 336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 337 2492, 2640, 1080, 1084, 1089, 1125, 0, 338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 339 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 340 /* 34 - 1920x1080@30Hz */ 341 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 342 2052, 2200, 1080, 1084, 1089, 1125, 0, 343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 344 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 345 /* 35 - 2880x480@60Hz */ 346 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 347 3192, 3432, 480, 489, 495, 525, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 349 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 350 /* 36 - 2880x480@60Hz */ 351 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 352 3192, 3432, 480, 489, 495, 525, 0, 353 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 354 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 355 /* 37 - 2880x576@50Hz */ 356 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 357 3184, 3456, 576, 581, 586, 625, 0, 358 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 359 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 360 /* 38 - 2880x576@50Hz */ 361 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 362 3184, 3456, 576, 581, 586, 625, 0, 363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 364 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 365 /* 39 - 1920x1080i@50Hz */ 366 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 367 2120, 2304, 1080, 1126, 1136, 1250, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 369 DRM_MODE_FLAG_INTERLACE), 370 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 371 /* 40 - 1920x1080i@100Hz */ 372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 373 2492, 2640, 1080, 1084, 1094, 1125, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 375 DRM_MODE_FLAG_INTERLACE), 376 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 377 /* 41 - 1280x720@100Hz */ 378 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 379 1760, 1980, 720, 725, 730, 750, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 381 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 382 /* 42 - 720x576@100Hz */ 383 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 384 796, 864, 576, 581, 586, 625, 0, 385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 386 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 387 /* 43 - 720x576@100Hz */ 388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 389 796, 864, 576, 581, 586, 625, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 391 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 392 /* 44 - 720(1440)x576i@100Hz */ 393 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 394 795, 864, 576, 580, 586, 625, 0, 395 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 396 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 397 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 398 /* 45 - 720(1440)x576i@100Hz */ 399 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 400 795, 864, 576, 580, 586, 625, 0, 401 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 402 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 403 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 404 /* 46 - 1920x1080i@120Hz */ 405 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 406 2052, 2200, 1080, 1084, 1094, 1125, 0, 407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 408 DRM_MODE_FLAG_INTERLACE), 409 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 410 /* 47 - 1280x720@120Hz */ 411 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 412 1430, 1650, 720, 725, 730, 750, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 414 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 415 /* 48 - 720x480@120Hz */ 416 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 417 798, 858, 480, 489, 495, 525, 0, 418 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 419 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 420 /* 49 - 720x480@120Hz */ 421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 422 798, 858, 480, 489, 495, 525, 0, 423 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 424 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 425 /* 50 - 720(1440)x480i@120Hz */ 426 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 427 801, 858, 480, 488, 494, 525, 0, 428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 429 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 430 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 431 /* 51 - 720(1440)x480i@120Hz */ 432 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 433 801, 858, 480, 488, 494, 525, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 435 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 436 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 437 /* 52 - 720x576@200Hz */ 438 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 439 796, 864, 576, 581, 586, 625, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 441 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 442 /* 53 - 720x576@200Hz */ 443 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 444 796, 864, 576, 581, 586, 625, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 446 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 447 /* 54 - 720(1440)x576i@200Hz */ 448 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 449 795, 864, 576, 580, 586, 625, 0, 450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 451 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 452 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 453 /* 55 - 720(1440)x576i@200Hz */ 454 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 455 795, 864, 576, 580, 586, 625, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 457 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 458 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 459 /* 56 - 720x480@240Hz */ 460 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 461 798, 858, 480, 489, 495, 525, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 463 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 464 /* 57 - 720x480@240Hz */ 465 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 466 798, 858, 480, 489, 495, 525, 0, 467 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 468 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 469 /* 58 - 720(1440)x480i@240 */ 470 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 471 801, 858, 480, 488, 494, 525, 0, 472 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 473 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 474 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 475 /* 59 - 720(1440)x480i@240 */ 476 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 477 801, 858, 480, 488, 494, 525, 0, 478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 479 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 480 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 481 /* 60 - 1280x720@24Hz */ 482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 483 3080, 3300, 720, 725, 730, 750, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 485 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 486 /* 61 - 1280x720@25Hz */ 487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 488 3740, 3960, 720, 725, 730, 750, 0, 489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 490 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 491 /* 62 - 1280x720@30Hz */ 492 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 493 3080, 3300, 720, 725, 730, 750, 0, 494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 495 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 496 /* 63 - 1920x1080@120Hz */ 497 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 498 2052, 2200, 1080, 1084, 1089, 1125, 0, 499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 500 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 501 /* 64 - 1920x1080@100Hz */ 502 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 503 2492, 2640, 1080, 1084, 1089, 1125, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 505 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 506 /* 65 - 1280x720@24Hz */ 507 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 508 3080, 3300, 720, 725, 730, 750, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 510 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 511 /* 66 - 1280x720@25Hz */ 512 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 513 3740, 3960, 720, 725, 730, 750, 0, 514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 515 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 516 /* 67 - 1280x720@30Hz */ 517 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 518 3080, 3300, 720, 725, 730, 750, 0, 519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 520 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 521 /* 68 - 1280x720@50Hz */ 522 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 523 1760, 1980, 720, 725, 730, 750, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 525 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 526 /* 69 - 1280x720@60Hz */ 527 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 528 1430, 1650, 720, 725, 730, 750, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 530 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 531 /* 70 - 1280x720@100Hz */ 532 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 533 1760, 1980, 720, 725, 730, 750, 0, 534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 535 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 536 /* 71 - 1280x720@120Hz */ 537 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 538 1430, 1650, 720, 725, 730, 750, 0, 539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 540 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 541 /* 72 - 1920x1080@24Hz */ 542 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 543 2602, 2750, 1080, 1084, 1089, 1125, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 545 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 546 /* 73 - 1920x1080@25Hz */ 547 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 548 2492, 2640, 1080, 1084, 1089, 1125, 0, 549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 550 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 551 /* 74 - 1920x1080@30Hz */ 552 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 553 2052, 2200, 1080, 1084, 1089, 1125, 0, 554 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 555 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 556 /* 75 - 1920x1080@50Hz */ 557 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 558 2492, 2640, 1080, 1084, 1089, 1125, 0, 559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 560 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 561 /* 76 - 1920x1080@60Hz */ 562 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 563 2052, 2200, 1080, 1084, 1089, 1125, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 565 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 566 /* 77 - 1920x1080@100Hz */ 567 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 568 2492, 2640, 1080, 1084, 1089, 1125, 0, 569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 570 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 571 /* 78 - 1920x1080@120Hz */ 572 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 573 2052, 2200, 1080, 1084, 1089, 1125, 0, 574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 575 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 576 /* 79 - 1680x720@24Hz */ 577 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 578 3080, 3300, 720, 725, 730, 750, 0, 579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 580 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 581 /* 80 - 1680x720@25Hz */ 582 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 583 2948, 3168, 720, 725, 730, 750, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 585 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 586 /* 81 - 1680x720@30Hz */ 587 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 588 2420, 2640, 720, 725, 730, 750, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 590 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 591 /* 82 - 1680x720@50Hz */ 592 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 593 1980, 2200, 720, 725, 730, 750, 0, 594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 595 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 596 /* 83 - 1680x720@60Hz */ 597 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 598 1980, 2200, 720, 725, 730, 750, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 600 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 601 /* 84 - 1680x720@100Hz */ 602 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 603 1780, 2000, 720, 725, 730, 825, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 605 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 606 /* 85 - 1680x720@120Hz */ 607 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 608 1780, 2000, 720, 725, 730, 825, 0, 609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 610 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 611 /* 86 - 2560x1080@24Hz */ 612 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 613 3602, 3750, 1080, 1084, 1089, 1100, 0, 614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 615 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 616 /* 87 - 2560x1080@25Hz */ 617 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 618 3052, 3200, 1080, 1084, 1089, 1125, 0, 619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 620 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 621 /* 88 - 2560x1080@30Hz */ 622 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 623 3372, 3520, 1080, 1084, 1089, 1125, 0, 624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 625 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 626 /* 89 - 2560x1080@50Hz */ 627 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 628 3152, 3300, 1080, 1084, 1089, 1125, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 630 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 631 /* 90 - 2560x1080@60Hz */ 632 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 633 2852, 3000, 1080, 1084, 1089, 1100, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 635 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 636 /* 91 - 2560x1080@100Hz */ 637 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 638 2822, 2970, 1080, 1084, 1089, 1250, 0, 639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 640 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 641 /* 92 - 2560x1080@120Hz */ 642 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 643 3152, 3300, 1080, 1084, 1089, 1250, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 645 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 646 /* 93 - 3840x2160p@24Hz 16:9 */ 647 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 648 5204, 5500, 2160, 2168, 2178, 2250, 0, 649 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 650 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 651 /* 94 - 3840x2160p@25Hz 16:9 */ 652 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 653 4984, 5280, 2160, 2168, 2178, 2250, 0, 654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 655 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 656 /* 95 - 3840x2160p@30Hz 16:9 */ 657 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 658 4104, 4400, 2160, 2168, 2178, 2250, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 660 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 96 - 3840x2160p@50Hz 16:9 */ 662 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 663 4984, 5280, 2160, 2168, 2178, 2250, 0, 664 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 665 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 666 /* 97 - 3840x2160p@60Hz 16:9 */ 667 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 668 4104, 4400, 2160, 2168, 2178, 2250, 0, 669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 670 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 671 /* 98 - 4096x2160p@24Hz 256:135 */ 672 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 673 5204, 5500, 2160, 2168, 2178, 2250, 0, 674 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 675 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 676 /* 99 - 4096x2160p@25Hz 256:135 */ 677 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 678 5152, 5280, 2160, 2168, 2178, 2250, 0, 679 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 680 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 681 /* 100 - 4096x2160p@30Hz 256:135 */ 682 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 683 4272, 4400, 2160, 2168, 2178, 2250, 0, 684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 685 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 686 /* 101 - 4096x2160p@50Hz 256:135 */ 687 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 688 5152, 5280, 2160, 2168, 2178, 2250, 0, 689 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 690 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 691 /* 102 - 4096x2160p@60Hz 256:135 */ 692 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 693 4272, 4400, 2160, 2168, 2178, 2250, 0, 694 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 696 /* 103 - 3840x2160p@24Hz 64:27 */ 697 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 698 5204, 5500, 2160, 2168, 2178, 2250, 0, 699 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 700 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 701 /* 104 - 3840x2160p@25Hz 64:27 */ 702 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 703 4104, 4400, 2160, 2168, 2178, 2250, 0, 704 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 705 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 706 /* 105 - 3840x2160p@30Hz 64:27 */ 707 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 708 4104, 4400, 2160, 2168, 2178, 2250, 0, 709 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 710 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 711 /* 106 - 3840x2160p@50Hz 64:27 */ 712 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 713 4984, 5280, 2160, 2168, 2178, 2250, 0, 714 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 715 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 716 /* 107 - 3840x2160p@60Hz 64:27 */ 717 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 718 4104, 4400, 2160, 2168, 2178, 2250, 0, 719 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 721 /* 108 - 1280x720@48Hz 16:9 */ 722 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 723 2280, 2500, 720, 725, 730, 750, 0, 724 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 725 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 726 /* 109 - 1280x720@48Hz 64:27 */ 727 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 728 2280, 2500, 720, 725, 730, 750, 0, 729 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 730 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 731 /* 110 - 1680x720@48Hz 64:27 */ 732 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 733 2530, 2750, 720, 725, 730, 750, 0, 734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 735 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 736 /* 111 - 1920x1080@48Hz 16:9 */ 737 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 738 2602, 2750, 1080, 1084, 1089, 1125, 0, 739 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 740 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 112 - 1920x1080@48Hz 64:27 */ 742 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 743 2602, 2750, 1080, 1084, 1089, 1125, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 745 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 746 /* 113 - 2560x1080@48Hz 64:27 */ 747 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 748 3602, 3750, 1080, 1084, 1089, 1100, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 750 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 751 /* 114 - 3840x2160@48Hz 16:9 */ 752 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 753 5204, 5500, 2160, 2168, 2178, 2250, 0, 754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 755 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 756 /* 115 - 4096x2160@48Hz 256:135 */ 757 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 758 5204, 5500, 2160, 2168, 2178, 2250, 0, 759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 760 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 761 /* 116 - 3840x2160@48Hz 64:27 */ 762 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 763 5204, 5500, 2160, 2168, 2178, 2250, 0, 764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 765 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 766 /* 117 - 3840x2160@100Hz 16:9 */ 767 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 768 4984, 5280, 2160, 2168, 2178, 2250, 0, 769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 770 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 771 /* 118 - 3840x2160@120Hz 16:9 */ 772 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 773 4104, 4400, 2160, 2168, 2178, 2250, 0, 774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 775 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 119 - 3840x2160@100Hz 64:27 */ 777 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 778 4984, 5280, 2160, 2168, 2178, 2250, 0, 779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 780 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 781 /* 120 - 3840x2160@120Hz 64:27 */ 782 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 783 4104, 4400, 2160, 2168, 2178, 2250, 0, 784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 785 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 786 /* 121 - 5120x2160@24Hz 64:27 */ 787 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 788 7204, 7500, 2160, 2168, 2178, 2200, 0, 789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 790 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 791 /* 122 - 5120x2160@25Hz 64:27 */ 792 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 793 6904, 7200, 2160, 2168, 2178, 2200, 0, 794 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 795 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 796 /* 123 - 5120x2160@30Hz 64:27 */ 797 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 798 5872, 6000, 2160, 2168, 2178, 2200, 0, 799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 800 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 801 /* 124 - 5120x2160@48Hz 64:27 */ 802 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 803 5954, 6250, 2160, 2168, 2178, 2475, 0, 804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 805 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 806 /* 125 - 5120x2160@50Hz 64:27 */ 807 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 808 6304, 6600, 2160, 2168, 2178, 2250, 0, 809 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 811 /* 126 - 5120x2160@60Hz 64:27 */ 812 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 813 5372, 5500, 2160, 2168, 2178, 2250, 0, 814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 815 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 816 /* 127 - 5120x2160@100Hz 64:27 */ 817 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 818 6304, 6600, 2160, 2168, 2178, 2250, 0, 819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 820 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 821 }; 822 823 static const struct drm_display_mode edid_cea_modes_193[] = { 824 /* 193 - 5120x2160@120Hz 64:27 */ 825 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 826 5372, 5500, 2160, 2168, 2178, 2250, 0, 827 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 828 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 829 /* 194 - 7680x4320@24Hz 16:9 */ 830 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 831 10408, 11000, 4320, 4336, 4356, 4500, 0, 832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 833 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 195 - 7680x4320@25Hz 16:9 */ 835 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 836 10208, 10800, 4320, 4336, 4356, 4400, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 196 - 7680x4320@30Hz 16:9 */ 840 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 841 8408, 9000, 4320, 4336, 4356, 4400, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 197 - 7680x4320@48Hz 16:9 */ 845 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 846 10408, 11000, 4320, 4336, 4356, 4500, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 198 - 7680x4320@50Hz 16:9 */ 850 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 851 10208, 10800, 4320, 4336, 4356, 4400, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 853 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 199 - 7680x4320@60Hz 16:9 */ 855 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 856 8408, 9000, 4320, 4336, 4356, 4400, 0, 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 859 /* 200 - 7680x4320@100Hz 16:9 */ 860 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 861 9968, 10560, 4320, 4336, 4356, 4500, 0, 862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 863 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 201 - 7680x4320@120Hz 16:9 */ 865 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 866 8208, 8800, 4320, 4336, 4356, 4500, 0, 867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 868 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 869 /* 202 - 7680x4320@24Hz 64:27 */ 870 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 871 10408, 11000, 4320, 4336, 4356, 4500, 0, 872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 873 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 874 /* 203 - 7680x4320@25Hz 64:27 */ 875 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 876 10208, 10800, 4320, 4336, 4356, 4400, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 878 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 879 /* 204 - 7680x4320@30Hz 64:27 */ 880 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 881 8408, 9000, 4320, 4336, 4356, 4400, 0, 882 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 883 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 884 /* 205 - 7680x4320@48Hz 64:27 */ 885 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 886 10408, 11000, 4320, 4336, 4356, 4500, 0, 887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 888 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 889 /* 206 - 7680x4320@50Hz 64:27 */ 890 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 891 10208, 10800, 4320, 4336, 4356, 4400, 0, 892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 893 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 894 /* 207 - 7680x4320@60Hz 64:27 */ 895 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 896 8408, 9000, 4320, 4336, 4356, 4400, 0, 897 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 898 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 899 /* 208 - 7680x4320@100Hz 64:27 */ 900 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 901 9968, 10560, 4320, 4336, 4356, 4500, 0, 902 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 903 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 904 /* 209 - 7680x4320@120Hz 64:27 */ 905 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 906 8208, 8800, 4320, 4336, 4356, 4500, 0, 907 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 908 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 909 /* 210 - 10240x4320@24Hz 64:27 */ 910 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 911 11908, 12500, 4320, 4336, 4356, 4950, 0, 912 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 913 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 914 /* 211 - 10240x4320@25Hz 64:27 */ 915 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 916 12908, 13500, 4320, 4336, 4356, 4400, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 919 /* 212 - 10240x4320@30Hz 64:27 */ 920 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 921 10704, 11000, 4320, 4336, 4356, 4500, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 924 /* 213 - 10240x4320@48Hz 64:27 */ 925 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 926 11908, 12500, 4320, 4336, 4356, 4950, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 929 /* 214 - 10240x4320@50Hz 64:27 */ 930 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 931 12908, 13500, 4320, 4336, 4356, 4400, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 934 /* 215 - 10240x4320@60Hz 64:27 */ 935 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 936 10704, 11000, 4320, 4336, 4356, 4500, 0, 937 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 938 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 939 /* 216 - 10240x4320@100Hz 64:27 */ 940 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 941 12608, 13200, 4320, 4336, 4356, 4500, 0, 942 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 943 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 944 /* 217 - 10240x4320@120Hz 64:27 */ 945 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 946 10704, 11000, 4320, 4336, 4356, 4500, 0, 947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 949 /* 218 - 4096x2160@100Hz 256:135 */ 950 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 951 4984, 5280, 2160, 2168, 2178, 2250, 0, 952 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 953 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 954 /* 219 - 4096x2160@120Hz 256:135 */ 955 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 956 4272, 4400, 2160, 2168, 2178, 2250, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 958 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 959 }; 960 961 /* 962 * HDMI 1.4 4k modes. Index using the VIC. 963 */ 964 static const struct drm_display_mode edid_4k_modes[] = { 965 /* 0 - dummy, VICs start at 1 */ 966 { }, 967 /* 1 - 3840x2160@30Hz */ 968 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 969 3840, 4016, 4104, 4400, 970 2160, 2168, 2178, 2250, 0, 971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 972 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 973 /* 2 - 3840x2160@25Hz */ 974 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 975 3840, 4896, 4984, 5280, 976 2160, 2168, 2178, 2250, 0, 977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 978 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 979 /* 3 - 3840x2160@24Hz */ 980 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 981 3840, 5116, 5204, 5500, 982 2160, 2168, 2178, 2250, 0, 983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 984 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 985 /* 4 - 4096x2160@24Hz (SMPTE) */ 986 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 987 4096, 5116, 5204, 5500, 988 2160, 2168, 2178, 2250, 0, 989 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 990 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 991 }; 992 993 /* 994 * Autogenerated from the DMT spec. 995 * This table is copied from xfree86/modes/xf86EdidModes.c. 996 */ 997 static const struct drm_display_mode drm_dmt_modes[] = { 998 /* 0x01 - 640x350@85Hz */ 999 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1000 736, 832, 350, 382, 385, 445, 0, 1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1002 /* 0x02 - 640x400@85Hz */ 1003 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 1004 736, 832, 400, 401, 404, 445, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1006 /* 0x03 - 720x400@85Hz */ 1007 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 1008 828, 936, 400, 401, 404, 446, 0, 1009 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1010 /* 0x04 - 640x480@60Hz */ 1011 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1012 752, 800, 480, 490, 492, 525, 0, 1013 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1014 /* 0x05 - 640x480@72Hz */ 1015 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1016 704, 832, 480, 489, 492, 520, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1018 /* 0x06 - 640x480@75Hz */ 1019 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1020 720, 840, 480, 481, 484, 500, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1022 /* 0x07 - 640x480@85Hz */ 1023 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 1024 752, 832, 480, 481, 484, 509, 0, 1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1026 /* 0x08 - 800x600@56Hz */ 1027 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1028 896, 1024, 600, 601, 603, 625, 0, 1029 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1030 /* 0x09 - 800x600@60Hz */ 1031 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1032 968, 1056, 600, 601, 605, 628, 0, 1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1034 /* 0x0a - 800x600@72Hz */ 1035 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1036 976, 1040, 600, 637, 643, 666, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1038 /* 0x0b - 800x600@75Hz */ 1039 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1040 896, 1056, 600, 601, 604, 625, 0, 1041 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1042 /* 0x0c - 800x600@85Hz */ 1043 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 1044 896, 1048, 600, 601, 604, 631, 0, 1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1046 /* 0x0d - 800x600@120Hz RB */ 1047 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 1048 880, 960, 600, 603, 607, 636, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1050 /* 0x0e - 848x480@60Hz */ 1051 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 1052 976, 1088, 480, 486, 494, 517, 0, 1053 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1054 /* 0x0f - 1024x768@43Hz, interlace */ 1055 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1056 1208, 1264, 768, 768, 772, 817, 0, 1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1058 DRM_MODE_FLAG_INTERLACE) }, 1059 /* 0x10 - 1024x768@60Hz */ 1060 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1061 1184, 1344, 768, 771, 777, 806, 0, 1062 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1063 /* 0x11 - 1024x768@70Hz */ 1064 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1065 1184, 1328, 768, 771, 777, 806, 0, 1066 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1067 /* 0x12 - 1024x768@75Hz */ 1068 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1069 1136, 1312, 768, 769, 772, 800, 0, 1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1071 /* 0x13 - 1024x768@85Hz */ 1072 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 1073 1168, 1376, 768, 769, 772, 808, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1075 /* 0x14 - 1024x768@120Hz RB */ 1076 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 1077 1104, 1184, 768, 771, 775, 813, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1079 /* 0x15 - 1152x864@75Hz */ 1080 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1081 1344, 1600, 864, 865, 868, 900, 0, 1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1083 /* 0x55 - 1280x720@60Hz */ 1084 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1085 1430, 1650, 720, 725, 730, 750, 0, 1086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1087 /* 0x16 - 1280x768@60Hz RB */ 1088 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 1089 1360, 1440, 768, 771, 778, 790, 0, 1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1091 /* 0x17 - 1280x768@60Hz */ 1092 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 1093 1472, 1664, 768, 771, 778, 798, 0, 1094 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1095 /* 0x18 - 1280x768@75Hz */ 1096 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 1097 1488, 1696, 768, 771, 778, 805, 0, 1098 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1099 /* 0x19 - 1280x768@85Hz */ 1100 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 1101 1496, 1712, 768, 771, 778, 809, 0, 1102 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1103 /* 0x1a - 1280x768@120Hz RB */ 1104 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 1105 1360, 1440, 768, 771, 778, 813, 0, 1106 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1107 /* 0x1b - 1280x800@60Hz RB */ 1108 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 1109 1360, 1440, 800, 803, 809, 823, 0, 1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1111 /* 0x1c - 1280x800@60Hz */ 1112 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 1113 1480, 1680, 800, 803, 809, 831, 0, 1114 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1115 /* 0x1d - 1280x800@75Hz */ 1116 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 1117 1488, 1696, 800, 803, 809, 838, 0, 1118 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1119 /* 0x1e - 1280x800@85Hz */ 1120 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 1121 1496, 1712, 800, 803, 809, 843, 0, 1122 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1123 /* 0x1f - 1280x800@120Hz RB */ 1124 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 1125 1360, 1440, 800, 803, 809, 847, 0, 1126 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1127 /* 0x20 - 1280x960@60Hz */ 1128 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 1129 1488, 1800, 960, 961, 964, 1000, 0, 1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1131 /* 0x21 - 1280x960@85Hz */ 1132 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 1133 1504, 1728, 960, 961, 964, 1011, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1135 /* 0x22 - 1280x960@120Hz RB */ 1136 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 1137 1360, 1440, 960, 963, 967, 1017, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1139 /* 0x23 - 1280x1024@60Hz */ 1140 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 1141 1440, 1688, 1024, 1025, 1028, 1066, 0, 1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1143 /* 0x24 - 1280x1024@75Hz */ 1144 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1145 1440, 1688, 1024, 1025, 1028, 1066, 0, 1146 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1147 /* 0x25 - 1280x1024@85Hz */ 1148 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 1149 1504, 1728, 1024, 1025, 1028, 1072, 0, 1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1151 /* 0x26 - 1280x1024@120Hz RB */ 1152 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 1153 1360, 1440, 1024, 1027, 1034, 1084, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1155 /* 0x27 - 1360x768@60Hz */ 1156 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 1157 1536, 1792, 768, 771, 777, 795, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1159 /* 0x28 - 1360x768@120Hz RB */ 1160 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 1161 1440, 1520, 768, 771, 776, 813, 0, 1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1163 /* 0x51 - 1366x768@60Hz */ 1164 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 1165 1579, 1792, 768, 771, 774, 798, 0, 1166 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1167 /* 0x56 - 1366x768@60Hz */ 1168 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 1169 1436, 1500, 768, 769, 772, 800, 0, 1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1171 /* 0x29 - 1400x1050@60Hz RB */ 1172 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 1173 1480, 1560, 1050, 1053, 1057, 1080, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1175 /* 0x2a - 1400x1050@60Hz */ 1176 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 1177 1632, 1864, 1050, 1053, 1057, 1089, 0, 1178 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1179 /* 0x2b - 1400x1050@75Hz */ 1180 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 1181 1648, 1896, 1050, 1053, 1057, 1099, 0, 1182 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1183 /* 0x2c - 1400x1050@85Hz */ 1184 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 1185 1656, 1912, 1050, 1053, 1057, 1105, 0, 1186 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1187 /* 0x2d - 1400x1050@120Hz RB */ 1188 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 1189 1480, 1560, 1050, 1053, 1057, 1112, 0, 1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1191 /* 0x2e - 1440x900@60Hz RB */ 1192 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 1193 1520, 1600, 900, 903, 909, 926, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1195 /* 0x2f - 1440x900@60Hz */ 1196 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 1197 1672, 1904, 900, 903, 909, 934, 0, 1198 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1199 /* 0x30 - 1440x900@75Hz */ 1200 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 1201 1688, 1936, 900, 903, 909, 942, 0, 1202 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1203 /* 0x31 - 1440x900@85Hz */ 1204 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 1205 1696, 1952, 900, 903, 909, 948, 0, 1206 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1207 /* 0x32 - 1440x900@120Hz RB */ 1208 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 1209 1520, 1600, 900, 903, 909, 953, 0, 1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1211 /* 0x53 - 1600x900@60Hz */ 1212 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 1213 1704, 1800, 900, 901, 904, 1000, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1215 /* 0x33 - 1600x1200@60Hz */ 1216 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 1217 1856, 2160, 1200, 1201, 1204, 1250, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1219 /* 0x34 - 1600x1200@65Hz */ 1220 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 1221 1856, 2160, 1200, 1201, 1204, 1250, 0, 1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1223 /* 0x35 - 1600x1200@70Hz */ 1224 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 1225 1856, 2160, 1200, 1201, 1204, 1250, 0, 1226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1227 /* 0x36 - 1600x1200@75Hz */ 1228 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 1229 1856, 2160, 1200, 1201, 1204, 1250, 0, 1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1231 /* 0x37 - 1600x1200@85Hz */ 1232 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 1233 1856, 2160, 1200, 1201, 1204, 1250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1235 /* 0x38 - 1600x1200@120Hz RB */ 1236 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 1237 1680, 1760, 1200, 1203, 1207, 1271, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1239 /* 0x39 - 1680x1050@60Hz RB */ 1240 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 1241 1760, 1840, 1050, 1053, 1059, 1080, 0, 1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1243 /* 0x3a - 1680x1050@60Hz */ 1244 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 1245 1960, 2240, 1050, 1053, 1059, 1089, 0, 1246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1247 /* 0x3b - 1680x1050@75Hz */ 1248 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 1249 1976, 2272, 1050, 1053, 1059, 1099, 0, 1250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1251 /* 0x3c - 1680x1050@85Hz */ 1252 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 1253 1984, 2288, 1050, 1053, 1059, 1105, 0, 1254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1255 /* 0x3d - 1680x1050@120Hz RB */ 1256 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 1257 1760, 1840, 1050, 1053, 1059, 1112, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1259 /* 0x3e - 1792x1344@60Hz */ 1260 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 1261 2120, 2448, 1344, 1345, 1348, 1394, 0, 1262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1263 /* 0x3f - 1792x1344@75Hz */ 1264 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 1265 2104, 2456, 1344, 1345, 1348, 1417, 0, 1266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1267 /* 0x40 - 1792x1344@120Hz RB */ 1268 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 1269 1872, 1952, 1344, 1347, 1351, 1423, 0, 1270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1271 /* 0x41 - 1856x1392@60Hz */ 1272 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 1273 2176, 2528, 1392, 1393, 1396, 1439, 0, 1274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1275 /* 0x42 - 1856x1392@75Hz */ 1276 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 1277 2208, 2560, 1392, 1393, 1396, 1500, 0, 1278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1279 /* 0x43 - 1856x1392@120Hz RB */ 1280 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 1281 1936, 2016, 1392, 1395, 1399, 1474, 0, 1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1283 /* 0x52 - 1920x1080@60Hz */ 1284 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1285 2052, 2200, 1080, 1084, 1089, 1125, 0, 1286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1287 /* 0x44 - 1920x1200@60Hz RB */ 1288 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 1289 2000, 2080, 1200, 1203, 1209, 1235, 0, 1290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1291 /* 0x45 - 1920x1200@60Hz */ 1292 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 1293 2256, 2592, 1200, 1203, 1209, 1245, 0, 1294 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1295 /* 0x46 - 1920x1200@75Hz */ 1296 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 1297 2264, 2608, 1200, 1203, 1209, 1255, 0, 1298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1299 /* 0x47 - 1920x1200@85Hz */ 1300 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 1301 2272, 2624, 1200, 1203, 1209, 1262, 0, 1302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1303 /* 0x48 - 1920x1200@120Hz RB */ 1304 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 1305 2000, 2080, 1200, 1203, 1209, 1271, 0, 1306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1307 /* 0x49 - 1920x1440@60Hz */ 1308 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 1309 2256, 2600, 1440, 1441, 1444, 1500, 0, 1310 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1311 /* 0x4a - 1920x1440@75Hz */ 1312 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 1313 2288, 2640, 1440, 1441, 1444, 1500, 0, 1314 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1315 /* 0x4b - 1920x1440@120Hz RB */ 1316 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 1317 2000, 2080, 1440, 1443, 1447, 1525, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1319 /* 0x54 - 2048x1152@60Hz */ 1320 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 1321 2154, 2250, 1152, 1153, 1156, 1200, 0, 1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1323 /* 0x4c - 2560x1600@60Hz RB */ 1324 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 1325 2640, 2720, 1600, 1603, 1609, 1646, 0, 1326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1327 /* 0x4d - 2560x1600@60Hz */ 1328 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 1329 3032, 3504, 1600, 1603, 1609, 1658, 0, 1330 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1331 /* 0x4e - 2560x1600@75Hz */ 1332 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 1333 3048, 3536, 1600, 1603, 1609, 1672, 0, 1334 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1335 /* 0x4f - 2560x1600@85Hz */ 1336 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 1337 3048, 3536, 1600, 1603, 1609, 1682, 0, 1338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1339 /* 0x50 - 2560x1600@120Hz RB */ 1340 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 1341 2640, 2720, 1600, 1603, 1609, 1694, 0, 1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1343 /* 0x57 - 4096x2160@60Hz RB */ 1344 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 1345 4136, 4176, 2160, 2208, 2216, 2222, 0, 1346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1347 /* 0x58 - 4096x2160@59.94Hz RB */ 1348 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 1349 4136, 4176, 2160, 2208, 2216, 2222, 0, 1350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1351 }; 1352 1353 /* 1354 * These more or less come from the DMT spec. The 720x400 modes are 1355 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 1356 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 1357 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 1358 * mode. 1359 * 1360 * The DMT modes have been fact-checked; the rest are mild guesses. 1361 */ 1362 static const struct drm_display_mode edid_est_modes[] = { 1363 /* 800x600@60Hz */ 1364 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 1365 968, 1056, 600, 601, 605, 628, 0, 1366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1367 /* 800x600@56Hz */ 1368 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 1369 896, 1024, 600, 601, 603, 625, 0, 1370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1371 /* 640x480@75Hz */ 1372 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 1373 720, 840, 480, 481, 484, 500, 0, 1374 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1375 /* 640x480@72Hz */ 1376 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 1377 704, 832, 480, 489, 492, 520, 0, 1378 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1379 /* 640x480@67Hz */ 1380 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 1381 768, 864, 480, 483, 486, 525, 0, 1382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1383 /* 640x480@60Hz */ 1384 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 1385 752, 800, 480, 490, 492, 525, 0, 1386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1387 /* 720x400@88Hz */ 1388 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 1389 846, 900, 400, 421, 423, 449, 0, 1390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1391 /* 720x400@70Hz */ 1392 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 1393 846, 900, 400, 412, 414, 449, 0, 1394 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1395 /* 1280x1024@75Hz */ 1396 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 1397 1440, 1688, 1024, 1025, 1028, 1066, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1399 /* 1024x768@75Hz */ 1400 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 1401 1136, 1312, 768, 769, 772, 800, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1403 /* 1024x768@70Hz */ 1404 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 1405 1184, 1328, 768, 771, 777, 806, 0, 1406 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1407 /* 1024x768@60Hz */ 1408 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1409 1184, 1344, 768, 771, 777, 806, 0, 1410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1411 /* 1024x768@43Hz */ 1412 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 1413 1208, 1264, 768, 768, 776, 817, 0, 1414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1415 DRM_MODE_FLAG_INTERLACE) }, 1416 /* 832x624@75Hz */ 1417 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 1418 928, 1152, 624, 625, 628, 667, 0, 1419 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1420 /* 800x600@75Hz */ 1421 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 1422 896, 1056, 600, 601, 604, 625, 0, 1423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1424 /* 800x600@72Hz */ 1425 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 1426 976, 1040, 600, 637, 643, 666, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1428 /* 1152x864@75Hz */ 1429 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 1430 1344, 1600, 864, 865, 868, 900, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 1432 }; 1433 1434 static const struct drm_display_mode resolution_white[] = { 1435 /* 0. vic:2 - 720x480@60Hz */ 1436 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 1437 798, 858, 480, 489, 495, 525, 0, 1438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1439 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1440 /* 1. vic:3 - 720x480@60Hz */ 1441 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 1442 798, 858, 480, 489, 495, 525, 0, 1443 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1444 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1445 /* 1024x768@60Hz */ 1446 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 1447 1184, 1344, 768, 771, 777, 806, 0, 1448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 1449 /* 2. vic:4 - 1280x720@60Hz */ 1450 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1451 1430, 1650, 720, 725, 730, 750, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1454 /* 3. vic:5 - 1920x1080i@60Hz */ 1455 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1456 2052, 2200, 1080, 1084, 1094, 1125, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1458 DRM_MODE_FLAG_INTERLACE), 1459 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1460 /* 4. vic:6 - 720(1440)x480i@60Hz */ 1461 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 1462 801, 858, 480, 488, 494, 525, 0, 1463 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1464 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1465 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1466 /* 5. vic:16 - 1920x1080@60Hz */ 1467 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1468 2052, 2200, 1080, 1084, 1089, 1125, 0, 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1470 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1471 /* 6. vic:17 - 720x576@50Hz */ 1472 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1473 796, 864, 576, 581, 586, 625, 0, 1474 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1475 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1476 /* 7. vic:18 - 720x576@50Hz */ 1477 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 1478 796, 864, 576, 581, 586, 625, 0, 1479 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1480 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1481 /* 8. vic:19 - 1280x720@50Hz */ 1482 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1483 1760, 1980, 720, 725, 730, 750, 0, 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1485 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1486 /* 9. vic:20 - 1920x1080i@50Hz */ 1487 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1488 2492, 2640, 1080, 1084, 1094, 1125, 0, 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 1490 DRM_MODE_FLAG_INTERLACE), 1491 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1492 /* 10. vic:21 - 720(1440)x576i@50Hz */ 1493 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 1494 795, 864, 576, 580, 586, 625, 0, 1495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1496 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1497 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1498 /* 11. vic:31 - 1920x1080@50Hz */ 1499 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1500 2492, 2640, 1080, 1084, 1089, 1125, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1503 /* 12. vic:32 - 1920x1080@24Hz */ 1504 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1505 2602, 2750, 1080, 1084, 1089, 1125, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1508 /* 13. vic:33 - 1920x1080@25Hz */ 1509 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1510 2492, 2640, 1080, 1084, 1089, 1125, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1513 /* 14. vic:34 - 1920x1080@30Hz */ 1514 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1515 2052, 2200, 1080, 1084, 1089, 1125, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1518 /* 15. vic:39 - 1920x1080i@50Hz */ 1519 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 1520 2120, 2304, 1080, 1126, 1136, 1250, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 1522 DRM_MODE_FLAG_INTERLACE), 1523 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1524 /* 16. vic:60 - 1280x720@24Hz */ 1525 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1526 3080, 3300, 720, 725, 730, 750, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1529 /* 17. vic:61 - 1280x720@25Hz */ 1530 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1531 3740, 3960, 720, 725, 730, 750, 0, 1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1533 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1534 /* 18. vic:62 - 1280x720@30Hz */ 1535 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1536 3080, 3300, 720, 725, 730, 750, 0, 1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1538 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1539 /* 19. vic:93 - 3840x2160p@24Hz 16:9 */ 1540 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1541 5204, 5500, 2160, 2168, 2178, 2250, 0, 1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1543 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1544 /* 20. vic:94 - 3840x2160p@25Hz 16:9 */ 1545 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1546 4984, 5280, 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 21. vic:95 - 3840x2160p@30Hz 16:9 */ 1550 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1551 4104, 4400, 2160, 2168, 2178, 2250, 0, 1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1553 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1554 /* 22. vic:96 - 3840x2160p@50Hz 16:9 */ 1555 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1556 4984, 5280, 2160, 2168, 2178, 2250, 0, 1557 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1558 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1559 /* 23. vic:97 - 3840x2160p@60Hz 16:9 */ 1560 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1561 4104, 4400, 2160, 2168, 2178, 2250, 0, 1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1563 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1564 /* 24. vic:98 - 4096x2160p@24Hz 256:135 */ 1565 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1566 5204, 5500, 2160, 2168, 2178, 2250, 0, 1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1568 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1569 /* 25. vic:99 - 4096x2160p@25Hz 256:135 */ 1570 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1571 5152, 5280, 2160, 2168, 2178, 2250, 0, 1572 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1573 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1574 /* 26. vic:100 - 4096x2160p@30Hz 256:135 */ 1575 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1576 4272, 4400, 2160, 2168, 2178, 2250, 0, 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1578 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1579 /* 27. vic:101 - 4096x2160p@50Hz 256:135 */ 1580 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1581 5152, 5280, 2160, 2168, 2178, 2250, 0, 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1583 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1584 /* 28. vic:102 - 4096x2160p@60Hz 256:135 */ 1585 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1586 4272, 4400, 2160, 2168, 2178, 2250, 0, 1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1588 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1589 /* 29. vic:118 - 3840x2160@120Hz 16:9 */ 1590 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1591 4104, 4400, 2160, 2168, 2178, 2250, 0, 1592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1593 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1594 /* 30. vic:196 - 7680x4320@30Hz 16:9 */ 1595 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1596 8408, 9000, 4320, 4336, 4356, 4400, 0, 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1598 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1599 /* 31. vic:198 - 7680x4320@50Hz 16:9 */ 1600 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1601 10208, 10800, 4320, 4336, 4356, 4400, 0, 1602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1603 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1604 /* 32. vic:199 - 7680x4320@60Hz 16:9 */ 1605 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1606 8408, 9000, 4320, 4336, 4356, 4400, 0, 1607 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1608 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1609 }; 1610 1611 struct minimode { 1612 short w; 1613 short h; 1614 short r; 1615 short rb; 1616 }; 1617 1618 static const struct minimode est3_modes[] = { 1619 /* byte 6 */ 1620 { 640, 350, 85, 0 }, 1621 { 640, 400, 85, 0 }, 1622 { 720, 400, 85, 0 }, 1623 { 640, 480, 85, 0 }, 1624 { 848, 480, 60, 0 }, 1625 { 800, 600, 85, 0 }, 1626 { 1024, 768, 85, 0 }, 1627 { 1152, 864, 75, 0 }, 1628 /* byte 7 */ 1629 { 1280, 768, 60, 1 }, 1630 { 1280, 768, 60, 0 }, 1631 { 1280, 768, 75, 0 }, 1632 { 1280, 768, 85, 0 }, 1633 { 1280, 960, 60, 0 }, 1634 { 1280, 960, 85, 0 }, 1635 { 1280, 1024, 60, 0 }, 1636 { 1280, 1024, 85, 0 }, 1637 /* byte 8 */ 1638 { 1360, 768, 60, 0 }, 1639 { 1440, 900, 60, 1 }, 1640 { 1440, 900, 60, 0 }, 1641 { 1440, 900, 75, 0 }, 1642 { 1440, 900, 85, 0 }, 1643 { 1400, 1050, 60, 1 }, 1644 { 1400, 1050, 60, 0 }, 1645 { 1400, 1050, 75, 0 }, 1646 /* byte 9 */ 1647 { 1400, 1050, 85, 0 }, 1648 { 1680, 1050, 60, 1 }, 1649 { 1680, 1050, 60, 0 }, 1650 { 1680, 1050, 75, 0 }, 1651 { 1680, 1050, 85, 0 }, 1652 { 1600, 1200, 60, 0 }, 1653 { 1600, 1200, 65, 0 }, 1654 { 1600, 1200, 70, 0 }, 1655 /* byte 10 */ 1656 { 1600, 1200, 75, 0 }, 1657 { 1600, 1200, 85, 0 }, 1658 { 1792, 1344, 60, 0 }, 1659 { 1792, 1344, 75, 0 }, 1660 { 1856, 1392, 60, 0 }, 1661 { 1856, 1392, 75, 0 }, 1662 { 1920, 1200, 60, 1 }, 1663 { 1920, 1200, 60, 0 }, 1664 /* byte 11 */ 1665 { 1920, 1200, 75, 0 }, 1666 { 1920, 1200, 85, 0 }, 1667 { 1920, 1440, 60, 0 }, 1668 { 1920, 1440, 75, 0 }, 1669 }; 1670 1671 static const struct minimode extra_modes[] = { 1672 { 1024, 576, 60, 0 }, 1673 { 1366, 768, 60, 0 }, 1674 { 1600, 900, 60, 0 }, 1675 { 1680, 945, 60, 0 }, 1676 { 1920, 1080, 60, 0 }, 1677 { 2048, 1152, 60, 0 }, 1678 { 2048, 1536, 60, 0 }, 1679 }; 1680 1681 static const struct drm_display_mode *cea_mode_for_vic(u8 vic) 1682 { 1683 if (!vic) 1684 return NULL; 1685 else if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 1686 return &edid_cea_modes_1[vic - 1]; 1687 else if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 1688 return &edid_cea_modes_193[vic - 193]; 1689 1690 return NULL; 1691 } 1692 1693 static u8 cea_num_vics(void) 1694 { 1695 return 193 + ARRAY_SIZE(edid_cea_modes_193); 1696 } 1697 1698 static u8 cea_next_vic(u8 vic) 1699 { 1700 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 1701 vic = 193; 1702 1703 return vic; 1704 } 1705 1706 int edid_check_info(struct edid1_info *edid_info) 1707 { 1708 if ((edid_info == NULL) || (edid_info->version == 0)) 1709 return -1; 1710 1711 if (memcmp(edid_info->header, "\x0\xff\xff\xff\xff\xff\xff\x0", 8)) 1712 return -1; 1713 1714 if (edid_info->version == 0xff && edid_info->revision == 0xff) 1715 return -1; 1716 1717 return 0; 1718 } 1719 1720 int edid_check_checksum(u8 *edid_block) 1721 { 1722 u8 checksum = 0; 1723 int i; 1724 1725 for (i = 0; i < 128; i++) 1726 checksum += edid_block[i]; 1727 1728 return (checksum == 0) ? 0 : -EINVAL; 1729 } 1730 1731 int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, 1732 unsigned int *hmax, unsigned int *vmin, 1733 unsigned int *vmax) 1734 { 1735 int i; 1736 struct edid_monitor_descriptor *monitor; 1737 1738 *hmin = *hmax = *vmin = *vmax = 0; 1739 if (edid_check_info(edid)) 1740 return -1; 1741 1742 for (i = 0; i < ARRAY_SIZE(edid->monitor_details.descriptor); i++) { 1743 monitor = &edid->monitor_details.descriptor[i]; 1744 if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) { 1745 *hmin = monitor->data.range_data.horizontal_min; 1746 *hmax = monitor->data.range_data.horizontal_max; 1747 *vmin = monitor->data.range_data.vertical_min; 1748 *vmax = monitor->data.range_data.vertical_max; 1749 return 0; 1750 } 1751 } 1752 return -1; 1753 } 1754 1755 /* Set all parts of a timing entry to the same value */ 1756 static void set_entry(struct timing_entry *entry, u32 value) 1757 { 1758 entry->min = value; 1759 entry->typ = value; 1760 entry->max = value; 1761 } 1762 1763 /** 1764 * decode_timing() - Decoding an 18-byte detailed timing record 1765 * 1766 * @buf: Pointer to EDID detailed timing record 1767 * @timing: Place to put timing 1768 */ 1769 static void decode_timing(u8 *buf, struct display_timing *timing) 1770 { 1771 uint x_mm, y_mm; 1772 unsigned int ha, hbl, hso, hspw, hborder; 1773 unsigned int va, vbl, vso, vspw, vborder; 1774 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1775 1776 /* Edid contains pixel clock in terms of 10KHz */ 1777 set_entry(&timing->pixelclock, (buf[0] + (buf[1] << 8)) * 10000); 1778 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1779 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1780 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1781 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1782 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1783 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1784 hborder = buf[15]; 1785 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1786 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1787 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1788 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1789 vborder = buf[16]; 1790 1791 set_entry(&timing->hactive, ha); 1792 set_entry(&timing->hfront_porch, hso); 1793 set_entry(&timing->hback_porch, hbl - hso - hspw); 1794 set_entry(&timing->hsync_len, hspw); 1795 1796 set_entry(&timing->vactive, va); 1797 set_entry(&timing->vfront_porch, vso); 1798 set_entry(&timing->vback_porch, vbl - vso - vspw); 1799 set_entry(&timing->vsync_len, vspw); 1800 1801 timing->flags = 0; 1802 if (EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t)) 1803 timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; 1804 else 1805 timing->flags |= DISPLAY_FLAGS_HSYNC_LOW; 1806 if (EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t)) 1807 timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; 1808 else 1809 timing->flags |= DISPLAY_FLAGS_VSYNC_LOW; 1810 1811 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1812 timing->flags = DISPLAY_FLAGS_INTERLACED; 1813 1814 debug("Detailed mode clock %u Hz, %d mm x %d mm\n" 1815 " %04x %04x %04x %04x hborder %x\n" 1816 " %04x %04x %04x %04x vborder %x\n", 1817 timing->pixelclock.typ, 1818 x_mm, y_mm, 1819 ha, ha + hso, ha + hso + hspw, 1820 ha + hbl, hborder, 1821 va, va + vso, va + vso + vspw, 1822 va + vbl, vborder); 1823 } 1824 1825 /** 1826 * decode_mode() - Decoding an 18-byte detailed timing record 1827 * 1828 * @buf: Pointer to EDID detailed timing record 1829 * @timing: Place to put timing 1830 */ 1831 static void decode_mode(u8 *buf, struct drm_display_mode *mode) 1832 { 1833 uint x_mm, y_mm; 1834 unsigned int ha, hbl, hso, hspw, hborder; 1835 unsigned int va, vbl, vso, vspw, vborder; 1836 struct edid_detailed_timing *t = (struct edid_detailed_timing *)buf; 1837 1838 x_mm = (buf[12] + ((buf[14] & 0xf0) << 4)); 1839 y_mm = (buf[13] + ((buf[14] & 0x0f) << 8)); 1840 ha = (buf[2] + ((buf[4] & 0xf0) << 4)); 1841 hbl = (buf[3] + ((buf[4] & 0x0f) << 8)); 1842 hso = (buf[8] + ((buf[11] & 0xc0) << 2)); 1843 hspw = (buf[9] + ((buf[11] & 0x30) << 4)); 1844 hborder = buf[15]; 1845 va = (buf[5] + ((buf[7] & 0xf0) << 4)); 1846 vbl = (buf[6] + ((buf[7] & 0x0f) << 8)); 1847 vso = ((buf[10] >> 4) + ((buf[11] & 0x0c) << 2)); 1848 vspw = ((buf[10] & 0x0f) + ((buf[11] & 0x03) << 4)); 1849 vborder = buf[16]; 1850 1851 /* Edid contains pixel clock in terms of 10KHz */ 1852 mode->clock = (buf[0] + (buf[1] << 8)) * 10; 1853 mode->hdisplay = ha; 1854 mode->hsync_start = ha + hso; 1855 mode->hsync_end = ha + hso + hspw; 1856 mode->htotal = ha + hbl; 1857 mode->vdisplay = va; 1858 mode->vsync_start = va + vso; 1859 mode->vsync_end = va + vso + vspw; 1860 mode->vtotal = va + vbl; 1861 1862 mode->flags = EDID_DETAILED_TIMING_FLAG_HSYNC_POLARITY(*t) ? 1863 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1864 mode->flags |= EDID_DETAILED_TIMING_FLAG_VSYNC_POLARITY(*t) ? 1865 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1866 1867 if (EDID_DETAILED_TIMING_FLAG_INTERLACED(*t)) 1868 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1869 1870 debug("Detailed mode clock %u kHz, %d mm x %d mm, flags[%x]\n" 1871 " %04d %04d %04d %04d hborder %d\n" 1872 " %04d %04d %04d %04d vborder %d\n", 1873 mode->clock, 1874 x_mm, y_mm, mode->flags, 1875 mode->hdisplay, mode->hsync_start, mode->hsync_end, 1876 mode->htotal, hborder, 1877 mode->vdisplay, mode->vsync_start, mode->vsync_end, 1878 mode->vtotal, vborder); 1879 } 1880 1881 /** 1882 * edid_vendor - match a string against EDID's obfuscated vendor field 1883 * @edid: EDID to match 1884 * @vendor: vendor string 1885 * 1886 * Returns true if @vendor is in @edid, false otherwise 1887 */ 1888 static bool edid_vendor(struct edid *edid, char *vendor) 1889 { 1890 char edid_vendor[3]; 1891 1892 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1893 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1894 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1895 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1896 1897 return !strncmp(edid_vendor, vendor, 3); 1898 } 1899 1900 /** 1901 * Check if HDMI vendor specific data block is present in CEA block 1902 * @param info CEA extension block 1903 * @return true if block is found 1904 */ 1905 static bool cea_is_hdmi_vsdb_present(struct edid_cea861_info *info) 1906 { 1907 u8 end, i = 0; 1908 1909 /* check for end of data block */ 1910 end = info->dtd_offset; 1911 if (end == 0) 1912 end = sizeof(info->data); 1913 if (end < 4 || end > sizeof(info->data)) 1914 return false; 1915 end -= 4; 1916 1917 while (i < end) { 1918 /* Look for vendor specific data block of appropriate size */ 1919 if ((EDID_CEA861_DB_TYPE(*info, i) == EDID_CEA861_DB_VENDOR) && 1920 (EDID_CEA861_DB_LEN(*info, i) >= 5)) { 1921 u8 *db = &info->data[i + 1]; 1922 u32 oui = db[0] | (db[1] << 8) | (db[2] << 16); 1923 1924 if (oui == HDMI_IEEE_OUI) 1925 return true; 1926 } 1927 i += EDID_CEA861_DB_LEN(*info, i) + 1; 1928 } 1929 1930 return false; 1931 } 1932 1933 static int drm_get_vrefresh(const struct drm_display_mode *mode) 1934 { 1935 int refresh = 0; 1936 unsigned int calc_val; 1937 1938 if (mode->vrefresh > 0) { 1939 refresh = mode->vrefresh; 1940 } else if (mode->htotal > 0 && mode->vtotal > 0) { 1941 int vtotal; 1942 1943 vtotal = mode->vtotal; 1944 /* work out vrefresh the value will be x1000 */ 1945 calc_val = (mode->clock * 1000); 1946 calc_val /= mode->htotal; 1947 refresh = (calc_val + vtotal / 2) / vtotal; 1948 1949 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1950 refresh *= 2; 1951 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 1952 refresh /= 2; 1953 if (mode->vscan > 1) 1954 refresh /= mode->vscan; 1955 } 1956 return refresh; 1957 } 1958 1959 int edid_get_drm_mode(u8 *buf, int buf_size, struct drm_display_mode *mode, 1960 int *panel_bits_per_colourp) 1961 { 1962 struct edid1_info *edid = (struct edid1_info *)buf; 1963 bool timing_done; 1964 int i; 1965 1966 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 1967 debug("%s: Invalid buffer\n", __func__); 1968 return -EINVAL; 1969 } 1970 1971 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 1972 debug("%s: No preferred timing\n", __func__); 1973 return -ENOENT; 1974 } 1975 1976 /* Look for detailed timing */ 1977 timing_done = false; 1978 for (i = 0; i < 4; i++) { 1979 struct edid_monitor_descriptor *desc; 1980 1981 desc = &edid->monitor_details.descriptor[i]; 1982 if (desc->zero_flag_1 != 0) { 1983 decode_mode((u8 *)desc, mode); 1984 timing_done = true; 1985 break; 1986 } 1987 } 1988 if (!timing_done) 1989 return -EINVAL; 1990 1991 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 1992 debug("%s: Not a digital display\n", __func__); 1993 return -ENOSYS; 1994 } 1995 if (edid->version != 1 || edid->revision < 4) { 1996 debug("%s: EDID version %d.%d does not have required info\n", 1997 __func__, edid->version, edid->revision); 1998 *panel_bits_per_colourp = -1; 1999 } else { 2000 *panel_bits_per_colourp = 2001 ((edid->video_input_definition & 0x70) >> 3) + 4; 2002 } 2003 2004 return 0; 2005 } 2006 2007 int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, 2008 int *panel_bits_per_colourp) 2009 { 2010 struct edid1_info *edid = (struct edid1_info *)buf; 2011 bool timing_done; 2012 int i; 2013 2014 if (buf_size < sizeof(*edid) || edid_check_info(edid)) { 2015 debug("%s: Invalid buffer\n", __func__); 2016 return -EINVAL; 2017 } 2018 2019 if (!EDID1_INFO_FEATURE_PREFERRED_TIMING_MODE(*edid)) { 2020 debug("%s: No preferred timing\n", __func__); 2021 return -ENOENT; 2022 } 2023 2024 /* Look for detailed timing */ 2025 timing_done = false; 2026 for (i = 0; i < 4; i++) { 2027 struct edid_monitor_descriptor *desc; 2028 2029 desc = &edid->monitor_details.descriptor[i]; 2030 if (desc->zero_flag_1 != 0) { 2031 decode_timing((u8 *)desc, timing); 2032 timing_done = true; 2033 break; 2034 } 2035 } 2036 if (!timing_done) 2037 return -EINVAL; 2038 2039 if (!EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid)) { 2040 debug("%s: Not a digital display\n", __func__); 2041 return -ENOSYS; 2042 } 2043 if (edid->version != 1 || edid->revision < 4) { 2044 debug("%s: EDID version %d.%d does not have required info\n", 2045 __func__, edid->version, edid->revision); 2046 *panel_bits_per_colourp = -1; 2047 } else { 2048 *panel_bits_per_colourp = 2049 ((edid->video_input_definition & 0x70) >> 3) + 4; 2050 } 2051 2052 timing->hdmi_monitor = false; 2053 if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) { 2054 struct edid_cea861_info *info = 2055 (struct edid_cea861_info *)(buf + sizeof(*edid)); 2056 2057 if (info->extension_tag == EDID_CEA861_EXTENSION_TAG) 2058 timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info); 2059 } 2060 2061 return 0; 2062 } 2063 2064 /** 2065 * Snip the tailing whitespace/return of a string. 2066 * 2067 * @param string The string to be snipped 2068 * @return the snipped string 2069 */ 2070 static char *snip(char *string) 2071 { 2072 char *s; 2073 2074 /* 2075 * This is always a 13 character buffer 2076 * and it's not always terminated. 2077 */ 2078 string[12] = '\0'; 2079 s = &string[strlen(string) - 1]; 2080 2081 while (s >= string && (isspace(*s) || *s == '\n' || *s == '\r' || 2082 *s == '\0')) 2083 *(s--) = '\0'; 2084 2085 return string; 2086 } 2087 2088 /** 2089 * Print an EDID monitor descriptor block 2090 * 2091 * @param monitor The EDID monitor descriptor block 2092 * @have_timing Modifies to 1 if the desciptor contains timing info 2093 */ 2094 static void edid_print_dtd(struct edid_monitor_descriptor *monitor, 2095 unsigned int *have_timing) 2096 { 2097 unsigned char *bytes = (unsigned char *)monitor; 2098 struct edid_detailed_timing *timing = 2099 (struct edid_detailed_timing *)monitor; 2100 2101 if (bytes[0] == 0 && bytes[1] == 0) { 2102 if (monitor->type == EDID_MONITOR_DESCRIPTOR_SERIAL) 2103 printf("Monitor serial number: %s\n", 2104 snip(monitor->data.string)); 2105 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_ASCII) 2106 printf("Monitor ID: %s\n", 2107 snip(monitor->data.string)); 2108 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_NAME) 2109 printf("Monitor name: %s\n", 2110 snip(monitor->data.string)); 2111 else if (monitor->type == EDID_MONITOR_DESCRIPTOR_RANGE) 2112 printf("Monitor range limits, horizontal sync: " 2113 "%d-%d kHz, vertical refresh: " 2114 "%d-%d Hz, max pixel clock: " 2115 "%d MHz\n", 2116 monitor->data.range_data.horizontal_min, 2117 monitor->data.range_data.horizontal_max, 2118 monitor->data.range_data.vertical_min, 2119 monitor->data.range_data.vertical_max, 2120 monitor->data.range_data.pixel_clock_max * 10); 2121 } else { 2122 u32 pixclock, h_active, h_blanking, v_active, v_blanking; 2123 u32 h_total, v_total, vfreq; 2124 2125 pixclock = EDID_DETAILED_TIMING_PIXEL_CLOCK(*timing); 2126 h_active = EDID_DETAILED_TIMING_HORIZONTAL_ACTIVE(*timing); 2127 h_blanking = EDID_DETAILED_TIMING_HORIZONTAL_BLANKING(*timing); 2128 v_active = EDID_DETAILED_TIMING_VERTICAL_ACTIVE(*timing); 2129 v_blanking = EDID_DETAILED_TIMING_VERTICAL_BLANKING(*timing); 2130 2131 h_total = h_active + h_blanking; 2132 v_total = v_active + v_blanking; 2133 if (v_total > 0 && h_total > 0) 2134 vfreq = pixclock / (v_total * h_total); 2135 else 2136 vfreq = 1; /* Error case */ 2137 printf("\t%dx%d\%c\t%d Hz (detailed)\n", h_active, 2138 v_active, h_active > 1000 ? ' ' : '\t', vfreq); 2139 *have_timing = 1; 2140 } 2141 } 2142 2143 /** 2144 * Get the manufacturer name from an EDID info. 2145 * 2146 * @param edid_info The EDID info to be printed 2147 * @param name Returns the string of the manufacturer name 2148 */ 2149 static void edid_get_manufacturer_name(struct edid1_info *edid, char *name) 2150 { 2151 name[0] = EDID1_INFO_MANUFACTURER_NAME_CHAR1(*edid) + 'A' - 1; 2152 name[1] = EDID1_INFO_MANUFACTURER_NAME_CHAR2(*edid) + 'A' - 1; 2153 name[2] = EDID1_INFO_MANUFACTURER_NAME_CHAR3(*edid) + 'A' - 1; 2154 name[3] = '\0'; 2155 } 2156 2157 void edid_print_info(struct edid1_info *edid_info) 2158 { 2159 int i; 2160 char manufacturer[4]; 2161 unsigned int have_timing = 0; 2162 u32 serial_number; 2163 2164 if (edid_check_info(edid_info)) { 2165 printf("Not a valid EDID\n"); 2166 return; 2167 } 2168 2169 printf("EDID version: %d.%d\n", 2170 edid_info->version, edid_info->revision); 2171 2172 printf("Product ID code: %04x\n", EDID1_INFO_PRODUCT_CODE(*edid_info)); 2173 2174 edid_get_manufacturer_name(edid_info, manufacturer); 2175 printf("Manufacturer: %s\n", manufacturer); 2176 2177 serial_number = EDID1_INFO_SERIAL_NUMBER(*edid_info); 2178 if (serial_number != 0xffffffff) { 2179 if (strcmp(manufacturer, "MAG") == 0) 2180 serial_number -= 0x7000000; 2181 if (strcmp(manufacturer, "OQI") == 0) 2182 serial_number -= 456150000; 2183 if (strcmp(manufacturer, "VSC") == 0) 2184 serial_number -= 640000000; 2185 } 2186 printf("Serial number: %08x\n", serial_number); 2187 printf("Manufactured in week: %d year: %d\n", 2188 edid_info->week, edid_info->year + 1990); 2189 2190 printf("Video input definition: %svoltage level %d%s%s%s%s%s\n", 2191 EDID1_INFO_VIDEO_INPUT_DIGITAL(*edid_info) ? 2192 "digital signal, " : "analog signal, ", 2193 EDID1_INFO_VIDEO_INPUT_VOLTAGE_LEVEL(*edid_info), 2194 EDID1_INFO_VIDEO_INPUT_BLANK_TO_BLACK(*edid_info) ? 2195 ", blank to black" : "", 2196 EDID1_INFO_VIDEO_INPUT_SEPARATE_SYNC(*edid_info) ? 2197 ", separate sync" : "", 2198 EDID1_INFO_VIDEO_INPUT_COMPOSITE_SYNC(*edid_info) ? 2199 ", composite sync" : "", 2200 EDID1_INFO_VIDEO_INPUT_SYNC_ON_GREEN(*edid_info) ? 2201 ", sync on green" : "", 2202 EDID1_INFO_VIDEO_INPUT_SERRATION_V(*edid_info) ? 2203 ", serration v" : ""); 2204 2205 printf("Monitor is %s\n", 2206 EDID1_INFO_FEATURE_RGB(*edid_info) ? "RGB" : "non-RGB"); 2207 2208 printf("Maximum visible display size: %d cm x %d cm\n", 2209 edid_info->max_size_horizontal, 2210 edid_info->max_size_vertical); 2211 2212 printf("Power management features: %s%s, %s%s, %s%s\n", 2213 EDID1_INFO_FEATURE_ACTIVE_OFF(*edid_info) ? 2214 "" : "no ", "active off", 2215 EDID1_INFO_FEATURE_SUSPEND(*edid_info) ? "" : "no ", "suspend", 2216 EDID1_INFO_FEATURE_STANDBY(*edid_info) ? "" : "no ", "standby"); 2217 2218 printf("Estabilished timings:\n"); 2219 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_70(*edid_info)) 2220 printf("\t720x400\t\t70 Hz (VGA 640x400, IBM)\n"); 2221 if (EDID1_INFO_ESTABLISHED_TIMING_720X400_88(*edid_info)) 2222 printf("\t720x400\t\t88 Hz (XGA2)\n"); 2223 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_60(*edid_info)) 2224 printf("\t640x480\t\t60 Hz (VGA)\n"); 2225 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_67(*edid_info)) 2226 printf("\t640x480\t\t67 Hz (Mac II, Apple)\n"); 2227 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_72(*edid_info)) 2228 printf("\t640x480\t\t72 Hz (VESA)\n"); 2229 if (EDID1_INFO_ESTABLISHED_TIMING_640X480_75(*edid_info)) 2230 printf("\t640x480\t\t75 Hz (VESA)\n"); 2231 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_56(*edid_info)) 2232 printf("\t800x600\t\t56 Hz (VESA)\n"); 2233 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_60(*edid_info)) 2234 printf("\t800x600\t\t60 Hz (VESA)\n"); 2235 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_72(*edid_info)) 2236 printf("\t800x600\t\t72 Hz (VESA)\n"); 2237 if (EDID1_INFO_ESTABLISHED_TIMING_800X600_75(*edid_info)) 2238 printf("\t800x600\t\t75 Hz (VESA)\n"); 2239 if (EDID1_INFO_ESTABLISHED_TIMING_832X624_75(*edid_info)) 2240 printf("\t832x624\t\t75 Hz (Mac II)\n"); 2241 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_87I(*edid_info)) 2242 printf("\t1024x768\t87 Hz Interlaced (8514A)\n"); 2243 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_60(*edid_info)) 2244 printf("\t1024x768\t60 Hz (VESA)\n"); 2245 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_70(*edid_info)) 2246 printf("\t1024x768\t70 Hz (VESA)\n"); 2247 if (EDID1_INFO_ESTABLISHED_TIMING_1024X768_75(*edid_info)) 2248 printf("\t1024x768\t75 Hz (VESA)\n"); 2249 if (EDID1_INFO_ESTABLISHED_TIMING_1280X1024_75(*edid_info)) 2250 printf("\t1280x1024\t75 (VESA)\n"); 2251 if (EDID1_INFO_ESTABLISHED_TIMING_1152X870_75(*edid_info)) 2252 printf("\t1152x870\t75 (Mac II)\n"); 2253 2254 /* Standard timings. */ 2255 printf("Standard timings:\n"); 2256 for (i = 0; i < ARRAY_SIZE(edid_info->standard_timings); i++) { 2257 unsigned int aspect = 10000; 2258 unsigned int x, y; 2259 unsigned char xres, vfreq; 2260 2261 xres = EDID1_INFO_STANDARD_TIMING_XRESOLUTION(*edid_info, i); 2262 vfreq = EDID1_INFO_STANDARD_TIMING_VFREQ(*edid_info, i); 2263 if ((xres != vfreq) || 2264 ((xres != 0) && (xres != 1)) || 2265 ((vfreq != 0) && (vfreq != 1))) { 2266 switch (EDID1_INFO_STANDARD_TIMING_ASPECT(*edid_info, 2267 i)) { 2268 case ASPECT_625: 2269 aspect = 6250; 2270 break; 2271 case ASPECT_75: 2272 aspect = 7500; 2273 break; 2274 case ASPECT_8: 2275 aspect = 8000; 2276 break; 2277 case ASPECT_5625: 2278 aspect = 5625; 2279 break; 2280 } 2281 x = (xres + 31) * 8; 2282 y = x * aspect / 10000; 2283 printf("\t%dx%d%c\t%d Hz\n", x, y, 2284 x > 1000 ? ' ' : '\t', (vfreq & 0x3f) + 60); 2285 have_timing = 1; 2286 } 2287 } 2288 2289 /* Detailed timing information. */ 2290 for (i = 0; i < ARRAY_SIZE(edid_info->monitor_details.descriptor); 2291 i++) { 2292 edid_print_dtd(&edid_info->monitor_details.descriptor[i], 2293 &have_timing); 2294 } 2295 2296 if (!have_timing) 2297 printf("\tNone\n"); 2298 } 2299 2300 /** 2301 * drm_cvt_mode -create a modeline based on the CVT algorithm 2302 * @hdisplay: hdisplay size 2303 * @vdisplay: vdisplay size 2304 * @vrefresh: vrefresh rate 2305 * @reduced: whether to use reduced blanking 2306 * @interlaced: whether to compute an interlaced mode 2307 * @margins: whether to add margins (borders) 2308 * 2309 * This function is called to generate the modeline based on CVT algorithm 2310 * according to the hdisplay, vdisplay, vrefresh. 2311 * It is based from the VESA(TM) Coordinated Video Timing Generator by 2312 * Graham Loveridge April 9, 2003 available at 2313 * http://www.elo.utfsm.cl/~elo212/docs/CVTd6r1.xls 2314 * 2315 * And it is copied from xf86CVTmode in xserver/hw/xfree86/modes/xf86cvt.c. 2316 * What I have done is to translate it by using integer calculation. 2317 * 2318 * Returns: 2319 * The modeline based on the CVT algorithm stored in a drm_display_mode object. 2320 * The display mode object is allocated with drm_mode_create(). Returns NULL 2321 * when no mode could be allocated. 2322 */ 2323 static 2324 struct drm_display_mode *drm_cvt_mode(int hdisplay, int vdisplay, int vrefresh, 2325 bool reduced, bool interlaced, 2326 bool margins) 2327 { 2328 #define HV_FACTOR 1000 2329 /* 1) top/bottom margin size (% of height) - default: 1.8, */ 2330 #define CVT_MARGIN_PERCENTAGE 18 2331 /* 2) character cell horizontal granularity (pixels) - default 8 */ 2332 #define CVT_H_GRANULARITY 8 2333 /* 3) Minimum vertical porch (lines) - default 3 */ 2334 #define CVT_MIN_V_PORCH 3 2335 /* 4) Minimum number of vertical back porch lines - default 6 */ 2336 #define CVT_MIN_V_BPORCH 6 2337 /* Pixel Clock step (kHz) */ 2338 #define CVT_CLOCK_STEP 250 2339 struct drm_display_mode *drm_mode; 2340 unsigned int vfieldrate, hperiod; 2341 int hdisplay_rnd, hmargin, vdisplay_rnd, vmargin, vsync; 2342 int interlace; 2343 2344 /* allocate the drm_display_mode structure. If failure, we will 2345 * return directly 2346 */ 2347 drm_mode = drm_mode_create(); 2348 if (!drm_mode) 2349 return NULL; 2350 2351 /* the CVT default refresh rate is 60Hz */ 2352 if (!vrefresh) 2353 vrefresh = 60; 2354 2355 /* the required field fresh rate */ 2356 if (interlaced) 2357 vfieldrate = vrefresh * 2; 2358 else 2359 vfieldrate = vrefresh; 2360 2361 /* horizontal pixels */ 2362 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); 2363 2364 /* determine the left&right borders */ 2365 hmargin = 0; 2366 if (margins) { 2367 hmargin = hdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2368 hmargin -= hmargin % CVT_H_GRANULARITY; 2369 } 2370 /* find the total active pixels */ 2371 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; 2372 2373 /* find the number of lines per field */ 2374 if (interlaced) 2375 vdisplay_rnd = vdisplay / 2; 2376 else 2377 vdisplay_rnd = vdisplay; 2378 2379 /* find the top & bottom borders */ 2380 vmargin = 0; 2381 if (margins) 2382 vmargin = vdisplay_rnd * CVT_MARGIN_PERCENTAGE / 1000; 2383 2384 drm_mode->vdisplay = vdisplay + 2 * vmargin; 2385 2386 /* Interlaced */ 2387 if (interlaced) 2388 interlace = 1; 2389 else 2390 interlace = 0; 2391 2392 /* Determine VSync Width from aspect ratio */ 2393 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) 2394 vsync = 4; 2395 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) 2396 vsync = 5; 2397 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) 2398 vsync = 6; 2399 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) 2400 vsync = 7; 2401 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) 2402 vsync = 7; 2403 else /* custom */ 2404 vsync = 10; 2405 2406 if (!reduced) { 2407 /* simplify the GTF calculation */ 2408 /* 4) Minimum time of vertical sync + back porch interval 2409 * default 550.0 2410 */ 2411 int tmp1, tmp2; 2412 #define CVT_MIN_VSYNC_BP 550 2413 /* 3) Nominal HSync width (% of line period) - default 8 */ 2414 #define CVT_HSYNC_PERCENTAGE 8 2415 unsigned int hblank_percentage; 2416 int vsyncandback_porch, hblank; 2417 2418 /* estimated the horizontal period */ 2419 tmp1 = HV_FACTOR * 1000000 - 2420 CVT_MIN_VSYNC_BP * HV_FACTOR * vfieldrate; 2421 tmp2 = (vdisplay_rnd + 2 * vmargin + CVT_MIN_V_PORCH) * 2 + 2422 interlace; 2423 hperiod = tmp1 * 2 / (tmp2 * vfieldrate); 2424 2425 tmp1 = CVT_MIN_VSYNC_BP * HV_FACTOR / hperiod + 1; 2426 /* 9. Find number of lines in sync + backporch */ 2427 if (tmp1 < (vsync + CVT_MIN_V_PORCH)) 2428 vsyncandback_porch = vsync + CVT_MIN_V_PORCH; 2429 else 2430 vsyncandback_porch = tmp1; 2431 /* 10. Find number of lines in back porch 2432 * vback_porch = vsyncandback_porch - vsync; 2433 */ 2434 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + 2435 vsyncandback_porch + CVT_MIN_V_PORCH; 2436 /* 5) Definition of Horizontal blanking time limitation */ 2437 /* Gradient (%/kHz) - default 600 */ 2438 #define CVT_M_FACTOR 600 2439 /* Offset (%) - default 40 */ 2440 #define CVT_C_FACTOR 40 2441 /* Blanking time scaling factor - default 128 */ 2442 #define CVT_K_FACTOR 128 2443 /* Scaling factor weighting - default 20 */ 2444 #define CVT_J_FACTOR 20 2445 #define CVT_M_PRIME (CVT_M_FACTOR * CVT_K_FACTOR / 256) 2446 #define CVT_C_PRIME ((CVT_C_FACTOR - CVT_J_FACTOR) * CVT_K_FACTOR / 256 + \ 2447 CVT_J_FACTOR) 2448 /* 12. Find ideal blanking duty cycle from formula */ 2449 hblank_percentage = CVT_C_PRIME * HV_FACTOR - CVT_M_PRIME * 2450 hperiod / 1000; 2451 /* 13. Blanking time */ 2452 if (hblank_percentage < 20 * HV_FACTOR) 2453 hblank_percentage = 20 * HV_FACTOR; 2454 hblank = drm_mode->hdisplay * hblank_percentage / 2455 (100 * HV_FACTOR - hblank_percentage); 2456 hblank -= hblank % (2 * CVT_H_GRANULARITY); 2457 /* 14. find the total pixels per line */ 2458 drm_mode->htotal = drm_mode->hdisplay + hblank; 2459 drm_mode->hsync_end = drm_mode->hdisplay + hblank / 2; 2460 drm_mode->hsync_start = drm_mode->hsync_end - 2461 (drm_mode->htotal * CVT_HSYNC_PERCENTAGE) / 100; 2462 drm_mode->hsync_start += CVT_H_GRANULARITY - 2463 drm_mode->hsync_start % CVT_H_GRANULARITY; 2464 /* fill the Vsync values */ 2465 drm_mode->vsync_start = drm_mode->vdisplay + CVT_MIN_V_PORCH; 2466 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2467 } else { 2468 /* Reduced blanking */ 2469 /* Minimum vertical blanking interval time - default 460 */ 2470 #define CVT_RB_MIN_VBLANK 460 2471 /* Fixed number of clocks for horizontal sync */ 2472 #define CVT_RB_H_SYNC 32 2473 /* Fixed number of clocks for horizontal blanking */ 2474 #define CVT_RB_H_BLANK 160 2475 /* Fixed number of lines for vertical front porch - default 3*/ 2476 #define CVT_RB_VFPORCH 3 2477 int vbilines; 2478 int tmp1, tmp2; 2479 /* 8. Estimate Horizontal period. */ 2480 tmp1 = HV_FACTOR * 1000000 - 2481 CVT_RB_MIN_VBLANK * HV_FACTOR * vfieldrate; 2482 tmp2 = vdisplay_rnd + 2 * vmargin; 2483 hperiod = tmp1 / (tmp2 * vfieldrate); 2484 /* 9. Find number of lines in vertical blanking */ 2485 vbilines = CVT_RB_MIN_VBLANK * HV_FACTOR / hperiod + 1; 2486 /* 10. Check if vertical blanking is sufficient */ 2487 if (vbilines < (CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH)) 2488 vbilines = CVT_RB_VFPORCH + vsync + CVT_MIN_V_BPORCH; 2489 /* 11. Find total number of lines in vertical field */ 2490 drm_mode->vtotal = vdisplay_rnd + 2 * vmargin + vbilines; 2491 /* 12. Find total number of pixels in a line */ 2492 drm_mode->htotal = drm_mode->hdisplay + CVT_RB_H_BLANK; 2493 /* Fill in HSync values */ 2494 drm_mode->hsync_end = drm_mode->hdisplay + CVT_RB_H_BLANK / 2; 2495 drm_mode->hsync_start = drm_mode->hsync_end - CVT_RB_H_SYNC; 2496 /* Fill in VSync values */ 2497 drm_mode->vsync_start = drm_mode->vdisplay + CVT_RB_VFPORCH; 2498 drm_mode->vsync_end = drm_mode->vsync_start + vsync; 2499 } 2500 /* 15/13. Find pixel clock frequency (kHz for xf86) */ 2501 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod; 2502 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP; 2503 /* 18/16. Find actual vertical frame frequency */ 2504 /* ignore - just set the mode flag for interlaced */ 2505 if (interlaced) { 2506 drm_mode->vtotal *= 2; 2507 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 2508 } 2509 2510 if (reduced) 2511 drm_mode->flags |= (DRM_MODE_FLAG_PHSYNC | 2512 DRM_MODE_FLAG_NVSYNC); 2513 else 2514 drm_mode->flags |= (DRM_MODE_FLAG_PVSYNC | 2515 DRM_MODE_FLAG_NHSYNC); 2516 2517 return drm_mode; 2518 } 2519 2520 static int 2521 cea_db_payload_len(const u8 *db) 2522 { 2523 return db[0] & 0x1f; 2524 } 2525 2526 static int 2527 cea_db_extended_tag(const u8 *db) 2528 { 2529 return db[1]; 2530 } 2531 2532 static int 2533 cea_db_tag(const u8 *db) 2534 { 2535 return db[0] >> 5; 2536 } 2537 2538 #define for_each_cea_db(cea, i, start, end) \ 2539 for ((i) = (start); (i) < (end) && (i) + \ 2540 cea_db_payload_len(&(cea)[(i)]) < \ 2541 (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2542 2543 static int 2544 cea_revision(const u8 *cea) 2545 { 2546 return cea[1]; 2547 } 2548 2549 static int 2550 cea_db_offsets(const u8 *cea, int *start, int *end) 2551 { 2552 /* Data block offset in CEA extension block */ 2553 *start = 4; 2554 *end = cea[2]; 2555 if (*end == 0) 2556 *end = 127; 2557 if (*end < 4 || *end > 127) 2558 return -ERANGE; 2559 2560 /* 2561 * XXX: cea[2] is equal to the real value minus one in some sink edid. 2562 */ 2563 if (*end != 4) { 2564 int i; 2565 2566 i = *start; 2567 while (i < (*end) && 2568 i + cea_db_payload_len(&(cea)[i]) < (*end)) 2569 i += cea_db_payload_len(&(cea)[i]) + 1; 2570 2571 if (cea_db_payload_len(&(cea)[i]) && 2572 i + cea_db_payload_len(&(cea)[i]) == (*end)) 2573 (*end)++; 2574 } 2575 2576 return 0; 2577 } 2578 2579 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2580 { 2581 int hdmi_id; 2582 2583 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2584 return false; 2585 2586 if (cea_db_payload_len(db) < 5) 2587 return false; 2588 2589 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2590 2591 return hdmi_id == HDMI_IEEE_OUI; 2592 } 2593 2594 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 2595 { 2596 unsigned int oui; 2597 2598 if (cea_db_tag(db) != EDID_CEA861_DB_VENDOR) 2599 return false; 2600 2601 if (cea_db_payload_len(db) < 7) 2602 return false; 2603 2604 oui = db[3] << 16 | db[2] << 8 | db[1]; 2605 2606 return oui == HDMI_FORUM_IEEE_OUI; 2607 } 2608 2609 static bool cea_db_is_y420cmdb(const u8 *db) 2610 { 2611 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2612 return false; 2613 2614 if (!cea_db_payload_len(db)) 2615 return false; 2616 2617 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 2618 return false; 2619 2620 return true; 2621 } 2622 2623 static bool cea_db_is_y420vdb(const u8 *db) 2624 { 2625 if (cea_db_tag(db) != EDID_CEA861_DB_USE_EXTENDED) 2626 return false; 2627 2628 if (!cea_db_payload_len(db)) 2629 return false; 2630 2631 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 2632 return false; 2633 2634 return true; 2635 } 2636 2637 static bool drm_valid_hdmi_vic(u8 vic) 2638 { 2639 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 2640 } 2641 2642 static void drm_add_hdmi_modes(struct hdmi_edid_data *data, 2643 const struct drm_display_mode *mode) 2644 { 2645 struct drm_display_mode *mode_buf = data->mode_buf; 2646 2647 if (data->modes >= MODE_LEN) 2648 return; 2649 mode_buf[(data->modes)++] = *mode; 2650 } 2651 2652 static bool drm_valid_cea_vic(u8 vic) 2653 { 2654 return cea_mode_for_vic(vic) ? true : false; 2655 } 2656 2657 static u8 svd_to_vic(u8 svd) 2658 { 2659 /* 0-6 bit vic, 7th bit native mode indicator */ 2660 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 2661 return svd & 127; 2662 2663 return svd; 2664 } 2665 2666 static struct drm_display_mode * 2667 drm_display_mode_from_vic_index(const u8 *video_db, u8 video_len, 2668 u8 video_index) 2669 { 2670 struct drm_display_mode *newmode; 2671 u8 vic; 2672 2673 if (!video_db || video_index >= video_len) 2674 return NULL; 2675 2676 /* CEA modes are numbered 1..127 */ 2677 vic = svd_to_vic(video_db[video_index]); 2678 if (!drm_valid_cea_vic(vic)) 2679 return NULL; 2680 2681 newmode = drm_mode_create(); 2682 if (!newmode) 2683 return NULL; 2684 2685 *newmode = *cea_mode_for_vic(vic); 2686 newmode->vrefresh = 0; 2687 2688 return newmode; 2689 } 2690 2691 static void bitmap_set(unsigned long *map, unsigned int start, int len) 2692 { 2693 unsigned long *p = map + BIT_WORD(start); 2694 const unsigned int size = start + len; 2695 int bits_to_set = BITS_PER_LONG - (start % BITS_PER_LONG); 2696 unsigned long mask_to_set = BITMAP_FIRST_WORD_MASK(start); 2697 2698 while (len - bits_to_set >= 0) { 2699 *p |= mask_to_set; 2700 len -= bits_to_set; 2701 bits_to_set = BITS_PER_LONG; 2702 mask_to_set = ~0UL; 2703 p++; 2704 } 2705 if (len) { 2706 mask_to_set &= BITMAP_LAST_WORD_MASK(size); 2707 *p |= mask_to_set; 2708 } 2709 } 2710 2711 static void 2712 drm_add_cmdb_modes(u8 svd, struct drm_hdmi_info *hdmi) 2713 { 2714 u8 vic = svd_to_vic(svd); 2715 2716 if (!drm_valid_cea_vic(vic)) 2717 return; 2718 2719 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 2720 } 2721 2722 int do_cea_modes(struct hdmi_edid_data *data, const u8 *db, u8 len) 2723 { 2724 int i, modes = 0; 2725 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2726 2727 for (i = 0; i < len; i++) { 2728 struct drm_display_mode *mode; 2729 2730 mode = drm_display_mode_from_vic_index(db, len, i); 2731 if (mode) { 2732 /* 2733 * YCBCR420 capability block contains a bitmap which 2734 * gives the index of CEA modes from CEA VDB, which 2735 * can support YCBCR 420 sampling output also (apart 2736 * from RGB/YCBCR444 etc). 2737 * For example, if the bit 0 in bitmap is set, 2738 * first mode in VDB can support YCBCR420 output too. 2739 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 2740 */ 2741 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 2742 drm_add_cmdb_modes(db[i], hdmi); 2743 drm_add_hdmi_modes(data, mode); 2744 drm_mode_destroy(mode); 2745 modes++; 2746 } 2747 } 2748 2749 return modes; 2750 } 2751 2752 /* 2753 * do_y420vdb_modes - Parse YCBCR 420 only modes 2754 * @data: the structure that save parsed hdmi edid data 2755 * @svds: start of the data block of CEA YCBCR 420 VDB 2756 * @svds_len: length of the CEA YCBCR 420 VDB 2757 * @hdmi: runtime information about the connected HDMI sink 2758 * 2759 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 2760 * which contains modes which can be supported in YCBCR 420 2761 * output format only. 2762 */ 2763 static int 2764 do_y420vdb_modes(struct hdmi_edid_data *data, const u8 *svds, u8 svds_len) 2765 { 2766 int modes = 0, i; 2767 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 2768 2769 for (i = 0; i < svds_len; i++) { 2770 u8 vic = svd_to_vic(svds[i]); 2771 2772 if (!drm_valid_cea_vic(vic)) 2773 continue; 2774 2775 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 2776 drm_add_hdmi_modes(data, cea_mode_for_vic(vic)); 2777 modes++; 2778 } 2779 2780 return modes; 2781 } 2782 2783 struct stereo_mandatory_mode { 2784 int width, height, vrefresh; 2785 unsigned int flags; 2786 }; 2787 2788 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2789 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2790 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2791 { 1920, 1080, 50, 2792 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2793 { 1920, 1080, 60, 2794 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2795 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2796 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2797 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2798 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2799 }; 2800 2801 static bool 2802 stereo_match_mandatory(const struct drm_display_mode *mode, 2803 const struct stereo_mandatory_mode *stereo_mode) 2804 { 2805 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2806 2807 return mode->hdisplay == stereo_mode->width && 2808 mode->vdisplay == stereo_mode->height && 2809 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2810 drm_get_vrefresh(mode) == stereo_mode->vrefresh; 2811 } 2812 2813 static int add_hdmi_mandatory_stereo_modes(struct hdmi_edid_data *data) 2814 { 2815 const struct drm_display_mode *mode; 2816 int num = data->modes, modes = 0, i, k; 2817 2818 for (k = 0; k < num; k++) { 2819 mode = &data->mode_buf[k]; 2820 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2821 const struct stereo_mandatory_mode *mandatory; 2822 struct drm_display_mode *new_mode; 2823 2824 if (!stereo_match_mandatory(mode, 2825 &stereo_mandatory_modes[i])) 2826 continue; 2827 2828 mandatory = &stereo_mandatory_modes[i]; 2829 new_mode = drm_mode_create(); 2830 if (!new_mode) 2831 continue; 2832 2833 *new_mode = *mode; 2834 new_mode->flags |= mandatory->flags; 2835 drm_add_hdmi_modes(data, new_mode); 2836 drm_mode_destroy(new_mode); 2837 modes++; 2838 } 2839 } 2840 2841 return modes; 2842 } 2843 2844 static int add_3d_struct_modes(struct hdmi_edid_data *data, u16 structure, 2845 const u8 *video_db, u8 video_len, u8 video_index) 2846 { 2847 struct drm_display_mode *newmode; 2848 int modes = 0; 2849 2850 if (structure & (1 << 0)) { 2851 newmode = drm_display_mode_from_vic_index(video_db, 2852 video_len, 2853 video_index); 2854 if (newmode) { 2855 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2856 drm_add_hdmi_modes(data, newmode); 2857 modes++; 2858 drm_mode_destroy(newmode); 2859 } 2860 } 2861 if (structure & (1 << 6)) { 2862 newmode = drm_display_mode_from_vic_index(video_db, 2863 video_len, 2864 video_index); 2865 if (newmode) { 2866 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2867 drm_add_hdmi_modes(data, newmode); 2868 modes++; 2869 drm_mode_destroy(newmode); 2870 } 2871 } 2872 if (structure & (1 << 8)) { 2873 newmode = drm_display_mode_from_vic_index(video_db, 2874 video_len, 2875 video_index); 2876 if (newmode) { 2877 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2878 drm_add_hdmi_modes(data, newmode); 2879 modes++; 2880 drm_mode_destroy(newmode); 2881 } 2882 } 2883 2884 return modes; 2885 } 2886 2887 static int add_hdmi_mode(struct hdmi_edid_data *data, u8 vic) 2888 { 2889 if (!drm_valid_hdmi_vic(vic)) { 2890 debug("Unknown HDMI VIC: %d\n", vic); 2891 return 0; 2892 } 2893 2894 drm_add_hdmi_modes(data, &edid_4k_modes[vic]); 2895 2896 return 1; 2897 } 2898 2899 /* 2900 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2901 * @db: start of the CEA vendor specific block 2902 * @len: length of the CEA block payload, ie. one can access up to db[len] 2903 * 2904 * Parses the HDMI VSDB looking for modes to add to @data. This function 2905 * also adds the stereo 3d modes when applicable. 2906 */ 2907 static int 2908 do_hdmi_vsdb_modes(const u8 *db, u8 len, const u8 *video_db, u8 video_len, 2909 struct hdmi_edid_data *data) 2910 { 2911 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2912 u8 vic_len, hdmi_3d_len = 0; 2913 u16 mask; 2914 u16 structure_all; 2915 2916 if (len < 8) 2917 goto out; 2918 2919 /* no HDMI_Video_Present */ 2920 if (!(db[8] & (1 << 5))) 2921 goto out; 2922 2923 /* Latency_Fields_Present */ 2924 if (db[8] & (1 << 7)) 2925 offset += 2; 2926 2927 /* I_Latency_Fields_Present */ 2928 if (db[8] & (1 << 6)) 2929 offset += 2; 2930 2931 /* the declared length is not long enough for the 2 first bytes 2932 * of additional video format capabilities 2933 */ 2934 if (len < (8 + offset + 2)) 2935 goto out; 2936 2937 /* 3D_Present */ 2938 offset++; 2939 if (db[8 + offset] & (1 << 7)) { 2940 modes += add_hdmi_mandatory_stereo_modes(data); 2941 2942 /* 3D_Multi_present */ 2943 multi_present = (db[8 + offset] & 0x60) >> 5; 2944 } 2945 2946 offset++; 2947 vic_len = db[8 + offset] >> 5; 2948 hdmi_3d_len = db[8 + offset] & 0x1f; 2949 2950 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2951 u8 vic; 2952 2953 vic = db[9 + offset + i]; 2954 modes += add_hdmi_mode(data, vic); 2955 } 2956 2957 offset += 1 + vic_len; 2958 2959 if (multi_present == 1) 2960 multi_len = 2; 2961 else if (multi_present == 2) 2962 multi_len = 4; 2963 else 2964 multi_len = 0; 2965 2966 if (len < (8 + offset + hdmi_3d_len - 1)) 2967 goto out; 2968 2969 if (hdmi_3d_len < multi_len) 2970 goto out; 2971 2972 if (multi_present == 1 || multi_present == 2) { 2973 /* 3D_Structure_ALL */ 2974 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2975 2976 /* check if 3D_MASK is present */ 2977 if (multi_present == 2) 2978 mask = (db[10 + offset] << 8) | db[11 + offset]; 2979 else 2980 mask = 0xffff; 2981 2982 for (i = 0; i < 16; i++) { 2983 if (mask & (1 << i)) 2984 modes += add_3d_struct_modes(data, 2985 structure_all, 2986 video_db, 2987 video_len, i); 2988 } 2989 } 2990 2991 offset += multi_len; 2992 2993 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2994 int vic_index; 2995 struct drm_display_mode *newmode = NULL; 2996 unsigned int newflag = 0; 2997 bool detail_present; 2998 2999 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3000 3001 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3002 break; 3003 3004 /* 2D_VIC_order_X */ 3005 vic_index = db[8 + offset + i] >> 4; 3006 3007 /* 3D_Structure_X */ 3008 switch (db[8 + offset + i] & 0x0f) { 3009 case 0: 3010 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3011 break; 3012 case 6: 3013 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3014 break; 3015 case 8: 3016 /* 3D_Detail_X */ 3017 if ((db[9 + offset + i] >> 4) == 1) 3018 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3019 break; 3020 } 3021 3022 if (newflag != 0) { 3023 newmode = drm_display_mode_from_vic_index( 3024 video_db, 3025 video_len, 3026 vic_index); 3027 3028 if (newmode) { 3029 newmode->flags |= newflag; 3030 drm_add_hdmi_modes(data, newmode); 3031 modes++; 3032 drm_mode_destroy(newmode); 3033 } 3034 } 3035 3036 if (detail_present) 3037 i++; 3038 } 3039 3040 out: 3041 return modes; 3042 } 3043 3044 /** 3045 * edid_get_quirks - return quirk flags for a given EDID 3046 * @edid: EDID to process 3047 * 3048 * This tells subsequent routines what fixes they need to apply. 3049 */ 3050 static u32 edid_get_quirks(struct edid *edid) 3051 { 3052 struct edid_quirk *quirk; 3053 int i; 3054 3055 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 3056 quirk = &edid_quirk_list[i]; 3057 3058 if (edid_vendor(edid, quirk->vendor) && 3059 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 3060 return quirk->quirks; 3061 } 3062 3063 return 0; 3064 } 3065 3066 static void drm_parse_y420cmdb_bitmap(struct hdmi_edid_data *data, 3067 const u8 *db) 3068 { 3069 struct drm_display_info *info = &data->display_info; 3070 struct drm_hdmi_info *hdmi = &info->hdmi; 3071 u8 map_len = cea_db_payload_len(db) - 1; 3072 u8 count; 3073 u64 map = 0; 3074 3075 if (map_len == 0) { 3076 /* All CEA modes support ycbcr420 sampling also.*/ 3077 hdmi->y420_cmdb_map = U64_MAX; 3078 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3079 return; 3080 } 3081 3082 /* 3083 * This map indicates which of the existing CEA block modes 3084 * from VDB can support YCBCR420 output too. So if bit=0 is 3085 * set, first mode from VDB can support YCBCR420 output too. 3086 * We will parse and keep this map, before parsing VDB itself 3087 * to avoid going through the same block again and again. 3088 * 3089 * Spec is not clear about max possible size of this block. 3090 * Clamping max bitmap block size at 8 bytes. Every byte can 3091 * address 8 CEA modes, in this way this map can address 3092 * 8*8 = first 64 SVDs. 3093 */ 3094 if (map_len > 8) 3095 map_len = 8; 3096 3097 for (count = 0; count < map_len; count++) 3098 map |= (u64)db[2 + count] << (8 * count); 3099 3100 if (map) 3101 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3102 3103 hdmi->y420_cmdb_map = map; 3104 } 3105 3106 static 3107 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 3108 { 3109 switch (max_frl_rate) { 3110 case 1: 3111 *max_lanes = 3; 3112 *max_rate_per_lane = 3; 3113 break; 3114 case 2: 3115 *max_lanes = 3; 3116 *max_rate_per_lane = 6; 3117 break; 3118 case 3: 3119 *max_lanes = 4; 3120 *max_rate_per_lane = 6; 3121 break; 3122 case 4: 3123 *max_lanes = 4; 3124 *max_rate_per_lane = 8; 3125 break; 3126 case 5: 3127 *max_lanes = 4; 3128 *max_rate_per_lane = 10; 3129 break; 3130 case 6: 3131 *max_lanes = 4; 3132 *max_rate_per_lane = 12; 3133 break; 3134 case 0: 3135 default: 3136 *max_lanes = 0; 3137 *max_rate_per_lane = 0; 3138 } 3139 } 3140 3141 static void drm_parse_ycbcr420_deep_color_info(struct hdmi_edid_data *data, 3142 const u8 *db) 3143 { 3144 u8 dc_mask; 3145 struct drm_hdmi_info *hdmi = &data->display_info.hdmi; 3146 3147 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 3148 hdmi->y420_dc_modes |= dc_mask; 3149 } 3150 3151 static void drm_parse_hdmi_forum_vsdb(struct hdmi_edid_data *data, 3152 const u8 *hf_vsdb) 3153 { 3154 struct drm_display_info *display = &data->display_info; 3155 struct drm_hdmi_info *hdmi = &display->hdmi; 3156 3157 if (hf_vsdb[6] & 0x80) { 3158 hdmi->scdc.supported = true; 3159 if (hf_vsdb[6] & 0x40) 3160 hdmi->scdc.read_request = true; 3161 } 3162 3163 /* 3164 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 3165 * And as per the spec, three factors confirm this: 3166 * * Availability of a HF-VSDB block in EDID (check) 3167 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 3168 * * SCDC support available (let's check) 3169 * Lets check it out. 3170 */ 3171 3172 if (hf_vsdb[5]) { 3173 /* max clock is 5000 KHz times block value */ 3174 u32 max_tmds_clock = hf_vsdb[5] * 5000; 3175 struct drm_scdc *scdc = &hdmi->scdc; 3176 3177 if (max_tmds_clock > 340000) { 3178 display->max_tmds_clock = max_tmds_clock; 3179 debug("HF-VSDB: max TMDS clock %d kHz\n", 3180 display->max_tmds_clock); 3181 } 3182 3183 if (scdc->supported) { 3184 scdc->scrambling.supported = true; 3185 3186 /* Few sinks support scrambling for cloks < 340M */ 3187 if ((hf_vsdb[6] & 0x8)) 3188 scdc->scrambling.low_rates = true; 3189 } 3190 } 3191 3192 if (hf_vsdb[7]) { 3193 u8 max_frl_rate; 3194 u8 dsc_max_frl_rate; 3195 u8 dsc_max_slices; 3196 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 3197 3198 debug("hdmi_21 sink detected. parsing edid\n"); 3199 max_frl_rate = (hf_vsdb[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 3200 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 3201 &hdmi->max_frl_rate_per_lane); 3202 hdmi_dsc->v_1p2 = hf_vsdb[11] & DRM_EDID_DSC_1P2; 3203 3204 if (hdmi_dsc->v_1p2) { 3205 hdmi_dsc->native_420 = hf_vsdb[11] & DRM_EDID_DSC_NATIVE_420; 3206 hdmi_dsc->all_bpp = hf_vsdb[11] & DRM_EDID_DSC_ALL_BPP; 3207 3208 if (hf_vsdb[11] & DRM_EDID_DSC_16BPC) 3209 hdmi_dsc->bpc_supported = 16; 3210 else if (hf_vsdb[11] & DRM_EDID_DSC_12BPC) 3211 hdmi_dsc->bpc_supported = 12; 3212 else if (hf_vsdb[11] & DRM_EDID_DSC_10BPC) 3213 hdmi_dsc->bpc_supported = 10; 3214 else 3215 hdmi_dsc->bpc_supported = 0; 3216 3217 dsc_max_frl_rate = (hf_vsdb[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 3218 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 3219 &hdmi_dsc->max_frl_rate_per_lane); 3220 hdmi_dsc->total_chunk_kbytes = 3221 hf_vsdb[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 3222 3223 dsc_max_slices = hf_vsdb[12] & DRM_EDID_DSC_MAX_SLICES; 3224 switch (dsc_max_slices) { 3225 case 1: 3226 hdmi_dsc->max_slices = 1; 3227 hdmi_dsc->clk_per_slice = 340; 3228 break; 3229 case 2: 3230 hdmi_dsc->max_slices = 2; 3231 hdmi_dsc->clk_per_slice = 340; 3232 break; 3233 case 3: 3234 hdmi_dsc->max_slices = 4; 3235 hdmi_dsc->clk_per_slice = 340; 3236 break; 3237 case 4: 3238 hdmi_dsc->max_slices = 8; 3239 hdmi_dsc->clk_per_slice = 340; 3240 break; 3241 case 5: 3242 hdmi_dsc->max_slices = 8; 3243 hdmi_dsc->clk_per_slice = 400; 3244 break; 3245 case 6: 3246 hdmi_dsc->max_slices = 12; 3247 hdmi_dsc->clk_per_slice = 400; 3248 break; 3249 case 7: 3250 hdmi_dsc->max_slices = 16; 3251 hdmi_dsc->clk_per_slice = 400; 3252 break; 3253 case 0: 3254 default: 3255 hdmi_dsc->max_slices = 0; 3256 hdmi_dsc->clk_per_slice = 0; 3257 } 3258 } 3259 } 3260 3261 drm_parse_ycbcr420_deep_color_info(data, hf_vsdb); 3262 } 3263 3264 /** 3265 * drm_default_rgb_quant_range - default RGB quantization range 3266 * @mode: display mode 3267 * 3268 * Determine the default RGB quantization range for the mode, 3269 * as specified in CEA-861. 3270 * 3271 * Return: The default RGB quantization range for the mode 3272 */ 3273 enum hdmi_quantization_range 3274 drm_default_rgb_quant_range(struct drm_display_mode *mode) 3275 { 3276 /* All CEA modes other than VIC 1 use limited quantization range. */ 3277 return drm_match_cea_mode(mode) > 1 ? 3278 HDMI_QUANTIZATION_RANGE_LIMITED : 3279 HDMI_QUANTIZATION_RANGE_FULL; 3280 } 3281 3282 static void drm_parse_hdmi_deep_color_info(struct hdmi_edid_data *data, 3283 const u8 *hdmi) 3284 { 3285 struct drm_display_info *info = &data->display_info; 3286 unsigned int dc_bpc = 0; 3287 3288 /* HDMI supports at least 8 bpc */ 3289 info->bpc = 8; 3290 3291 if (cea_db_payload_len(hdmi) < 6) 3292 return; 3293 3294 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3295 dc_bpc = 10; 3296 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3297 debug("HDMI sink does deep color 30.\n"); 3298 } 3299 3300 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3301 dc_bpc = 12; 3302 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3303 debug("HDMI sink does deep color 36.\n"); 3304 } 3305 3306 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3307 dc_bpc = 16; 3308 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3309 debug("HDMI sink does deep color 48.\n"); 3310 } 3311 3312 if (dc_bpc == 0) { 3313 debug("No deep color support on this HDMI sink.\n"); 3314 return; 3315 } 3316 3317 debug("Assigning HDMI sink color depth as %d bpc.\n", dc_bpc); 3318 info->bpc = dc_bpc; 3319 3320 /* YCRCB444 is optional according to spec. */ 3321 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3322 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_Y444; 3323 debug("HDMI sink does YCRCB444 in deep color.\n"); 3324 } 3325 3326 /* 3327 * Spec says that if any deep color mode is supported at all, 3328 * then deep color 36 bit must be supported. 3329 */ 3330 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) 3331 debug("HDMI sink should do DC_36, but does not!\n"); 3332 } 3333 3334 /* 3335 * Search EDID for CEA extension block. 3336 */ 3337 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 3338 { 3339 u8 *edid_ext = NULL; 3340 int i; 3341 3342 /* No EDID or EDID extensions */ 3343 if (!edid || !edid->extensions) 3344 return NULL; 3345 3346 /* Find CEA extension */ 3347 for (i = 0; i < edid->extensions; i++) { 3348 edid_ext = (u8 *)edid + EDID_SIZE * (i + 1); 3349 if (edid_ext[0] == ext_id) 3350 break; 3351 } 3352 3353 if (i == edid->extensions) 3354 return NULL; 3355 3356 return edid_ext; 3357 } 3358 3359 static u8 *drm_find_cea_extension(struct edid *edid) 3360 { 3361 return drm_find_edid_extension(edid, 0x02); 3362 } 3363 3364 #define AUDIO_BLOCK 0x01 3365 #define VIDEO_BLOCK 0x02 3366 #define VENDOR_BLOCK 0x03 3367 #define SPEAKER_BLOCK 0x04 3368 #define EDID_BASIC_AUDIO BIT(6) 3369 3370 /** 3371 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3372 * @edid: monitor EDID information 3373 * 3374 * Parse the CEA extension according to CEA-861-B. 3375 * 3376 * Return: True if the monitor is HDMI, false if not or unknown. 3377 */ 3378 bool drm_detect_hdmi_monitor(struct edid *edid) 3379 { 3380 u8 *edid_ext; 3381 int i; 3382 int start_offset, end_offset; 3383 3384 edid_ext = drm_find_cea_extension(edid); 3385 if (!edid_ext) 3386 return false; 3387 3388 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3389 return false; 3390 3391 /* 3392 * Because HDMI identifier is in Vendor Specific Block, 3393 * search it from all data blocks of CEA extension. 3394 */ 3395 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3396 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3397 return true; 3398 } 3399 3400 return false; 3401 } 3402 3403 /** 3404 * drm_detect_monitor_audio - check monitor audio capability 3405 * @edid: EDID block to scan 3406 * 3407 * Monitor should have CEA extension block. 3408 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3409 * audio' only. If there is any audio extension block and supported 3410 * audio format, assume at least 'basic audio' support, even if 'basic 3411 * audio' is not defined in EDID. 3412 * 3413 * Return: True if the monitor supports audio, false otherwise. 3414 */ 3415 bool drm_detect_monitor_audio(struct edid *edid) 3416 { 3417 u8 *edid_ext; 3418 int i, j; 3419 bool has_audio = false; 3420 int start_offset, end_offset; 3421 3422 edid_ext = drm_find_cea_extension(edid); 3423 if (!edid_ext) 3424 goto end; 3425 3426 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3427 3428 if (has_audio) { 3429 printf("Monitor has basic audio support\n"); 3430 goto end; 3431 } 3432 3433 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3434 goto end; 3435 3436 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3437 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3438 has_audio = true; 3439 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; 3440 j += 3) 3441 debug("CEA audio format %d\n", 3442 (edid_ext[i + j] >> 3) & 0xf); 3443 goto end; 3444 } 3445 } 3446 end: 3447 return has_audio; 3448 } 3449 3450 static void 3451 drm_parse_hdmi_vsdb_video(struct hdmi_edid_data *data, const u8 *db) 3452 { 3453 struct drm_display_info *info = &data->display_info; 3454 u8 len = cea_db_payload_len(db); 3455 3456 if (len >= 6) 3457 info->dvi_dual = db[6] & 1; 3458 if (len >= 7) 3459 info->max_tmds_clock = db[7] * 5000; 3460 3461 drm_parse_hdmi_deep_color_info(data, db); 3462 } 3463 3464 static void drm_parse_cea_ext(struct hdmi_edid_data *data, 3465 struct edid *edid) 3466 { 3467 struct drm_display_info *info = &data->display_info; 3468 const u8 *edid_ext; 3469 int i, start, end; 3470 3471 edid_ext = drm_find_cea_extension(edid); 3472 if (!edid_ext) 3473 return; 3474 3475 info->cea_rev = edid_ext[1]; 3476 3477 /* The existence of a CEA block should imply RGB support */ 3478 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3479 if (edid_ext[3] & EDID_CEA_YCRCB444) 3480 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3481 if (edid_ext[3] & EDID_CEA_YCRCB422) 3482 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3483 3484 if (cea_db_offsets(edid_ext, &start, &end)) 3485 return; 3486 3487 for_each_cea_db(edid_ext, i, start, end) { 3488 const u8 *db = &edid_ext[i]; 3489 3490 if (cea_db_is_hdmi_vsdb(db)) 3491 drm_parse_hdmi_vsdb_video(data, db); 3492 if (cea_db_is_hdmi_forum_vsdb(db)) 3493 drm_parse_hdmi_forum_vsdb(data, db); 3494 if (cea_db_is_y420cmdb(db)) 3495 drm_parse_y420cmdb_bitmap(data, db); 3496 } 3497 } 3498 3499 static void drm_add_display_info(struct hdmi_edid_data *data, struct edid *edid) 3500 { 3501 struct drm_display_info *info = &data->display_info; 3502 3503 info->width_mm = edid->width_cm * 10; 3504 info->height_mm = edid->height_cm * 10; 3505 3506 /* driver figures it out in this case */ 3507 info->bpc = 0; 3508 info->color_formats = 0; 3509 info->cea_rev = 0; 3510 info->max_tmds_clock = 0; 3511 info->dvi_dual = false; 3512 info->edid_hdmi_dc_modes = 0; 3513 3514 memset(&info->hdmi, 0, sizeof(info->hdmi)); 3515 3516 if (edid->revision < 3) 3517 return; 3518 3519 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3520 return; 3521 3522 drm_parse_cea_ext(data, edid); 3523 3524 /* 3525 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 3526 * 3527 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 3528 * tells us to assume 8 bpc color depth if the EDID doesn't have 3529 * extensions which tell otherwise. 3530 */ 3531 if ((info->bpc == 0) && (edid->revision < 4) && 3532 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) { 3533 info->bpc = 8; 3534 debug("Assigning DFP sink color depth as %d bpc.\n", info->bpc); 3535 } 3536 3537 /* Only defined for 1.4 with digital displays */ 3538 if (edid->revision < 4) 3539 return; 3540 3541 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3542 case DRM_EDID_DIGITAL_DEPTH_6: 3543 info->bpc = 6; 3544 break; 3545 case DRM_EDID_DIGITAL_DEPTH_8: 3546 info->bpc = 8; 3547 break; 3548 case DRM_EDID_DIGITAL_DEPTH_10: 3549 info->bpc = 10; 3550 break; 3551 case DRM_EDID_DIGITAL_DEPTH_12: 3552 info->bpc = 12; 3553 break; 3554 case DRM_EDID_DIGITAL_DEPTH_14: 3555 info->bpc = 14; 3556 break; 3557 case DRM_EDID_DIGITAL_DEPTH_16: 3558 info->bpc = 16; 3559 break; 3560 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3561 default: 3562 info->bpc = 0; 3563 break; 3564 } 3565 3566 debug("Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3567 info->bpc); 3568 3569 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3570 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3571 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3572 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3573 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3574 } 3575 3576 static 3577 int add_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 3578 { 3579 const u8 *cea = drm_find_cea_extension(edid); 3580 const u8 *db, *hdmi = NULL, *video = NULL; 3581 u8 dbl, hdmi_len, video_len = 0; 3582 int modes = 0; 3583 3584 if (cea && cea_revision(cea) >= 3) { 3585 int i, start, end; 3586 3587 if (cea_db_offsets(cea, &start, &end)) 3588 return 0; 3589 3590 for_each_cea_db(cea, i, start, end) { 3591 db = &cea[i]; 3592 dbl = cea_db_payload_len(db); 3593 3594 if (cea_db_tag(db) == EDID_CEA861_DB_VIDEO) { 3595 video = db + 1; 3596 video_len = dbl; 3597 modes += do_cea_modes(data, video, dbl); 3598 } else if (cea_db_is_hdmi_vsdb(db)) { 3599 hdmi = db; 3600 hdmi_len = dbl; 3601 } else if (cea_db_is_y420vdb(db)) { 3602 const u8 *vdb420 = &db[2]; 3603 3604 /* Add 4:2:0(only) modes present in EDID */ 3605 modes += do_y420vdb_modes(data, vdb420, 3606 dbl - 1); 3607 } 3608 } 3609 } 3610 3611 /* 3612 * We parse the HDMI VSDB after having added the cea modes as we will 3613 * be patching their flags when the sink supports stereo 3D. 3614 */ 3615 if (hdmi) 3616 modes += do_hdmi_vsdb_modes(hdmi, hdmi_len, video, 3617 video_len, data); 3618 3619 return modes; 3620 } 3621 3622 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 3623 3624 static void 3625 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3626 { 3627 int i, n = 0; 3628 u8 d = ext[0x02]; 3629 u8 *det_base = ext + d; 3630 3631 if (d < 4 || d > 127) 3632 return; 3633 3634 n = (127 - d) / 18; 3635 for (i = 0; i < n; i++) 3636 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3637 } 3638 3639 static void 3640 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 3641 { 3642 unsigned int i, n = min((int)ext[0x02], 6); 3643 u8 *det_base = ext + 5; 3644 3645 if (ext[0x01] != 1) 3646 return; /* unknown version */ 3647 3648 for (i = 0; i < n; i++) 3649 cb((struct detailed_timing *)(det_base + 18 * i), closure); 3650 } 3651 3652 static void 3653 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 3654 { 3655 int i; 3656 struct edid *edid = (struct edid *)raw_edid; 3657 3658 if (!edid) 3659 return; 3660 3661 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3662 cb(&edid->detailed_timings[i], closure); 3663 3664 for (i = 1; i <= raw_edid[0x7e]; i++) { 3665 u8 *ext = raw_edid + (i * EDID_SIZE); 3666 3667 switch (*ext) { 3668 case CEA_EXT: 3669 cea_for_each_detailed_block(ext, cb, closure); 3670 break; 3671 case VTB_EXT: 3672 vtb_for_each_detailed_block(ext, cb, closure); 3673 break; 3674 default: 3675 break; 3676 } 3677 } 3678 } 3679 3680 /* 3681 * EDID is delightfully ambiguous about how interlaced modes are to be 3682 * encoded. Our internal representation is of frame height, but some 3683 * HDTV detailed timings are encoded as field height. 3684 * 3685 * The format list here is from CEA, in frame size. Technically we 3686 * should be checking refresh rate too. Whatever. 3687 */ 3688 static void 3689 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3690 struct detailed_pixel_timing *pt) 3691 { 3692 int i; 3693 3694 static const struct { 3695 int w, h; 3696 } cea_interlaced[] = { 3697 { 1920, 1080 }, 3698 { 720, 480 }, 3699 { 1440, 480 }, 3700 { 2880, 480 }, 3701 { 720, 576 }, 3702 { 1440, 576 }, 3703 { 2880, 576 }, 3704 }; 3705 3706 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3707 return; 3708 3709 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3710 if ((mode->hdisplay == cea_interlaced[i].w) && 3711 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3712 mode->vdisplay *= 2; 3713 mode->vsync_start *= 2; 3714 mode->vsync_end *= 2; 3715 mode->vtotal *= 2; 3716 mode->vtotal |= 1; 3717 } 3718 } 3719 3720 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3721 } 3722 3723 /** 3724 * drm_mode_detailed - create a new mode from an EDID detailed timing section 3725 * @edid: EDID block 3726 * @timing: EDID detailed timing info 3727 * @quirks: quirks to apply 3728 * 3729 * An EDID detailed timing block contains enough info for us to create and 3730 * return a new struct drm_display_mode. 3731 */ 3732 static 3733 struct drm_display_mode *drm_mode_detailed(struct edid *edid, 3734 struct detailed_timing *timing, 3735 u32 quirks) 3736 { 3737 struct drm_display_mode *mode; 3738 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3739 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3740 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3741 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3742 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3743 unsigned hsync_offset = 3744 (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | 3745 pt->hsync_offset_lo; 3746 unsigned hsync_pulse_width = 3747 (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | 3748 pt->hsync_pulse_width_lo; 3749 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 3750 2 | pt->vsync_offset_pulse_width_lo >> 4; 3751 unsigned vsync_pulse_width = 3752 (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | 3753 (pt->vsync_offset_pulse_width_lo & 0xf); 3754 3755 /* ignore tiny modes */ 3756 if (hactive < 64 || vactive < 64) 3757 return NULL; 3758 3759 if (pt->misc & DRM_EDID_PT_STEREO) { 3760 debug("stereo mode not supported\n"); 3761 return NULL; 3762 } 3763 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) 3764 debug("composite sync not supported\n"); 3765 3766 /* it is incorrect if hsync/vsync width is zero */ 3767 if (!hsync_pulse_width || !vsync_pulse_width) { 3768 debug("Incorrect Detailed timing. "); 3769 debug("Wrong Hsync/Vsync pulse width\n"); 3770 return NULL; 3771 } 3772 3773 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3774 mode = drm_cvt_mode(hactive, vactive, 60, true, false, false); 3775 if (!mode) 3776 return NULL; 3777 3778 goto set_refresh; 3779 } 3780 3781 mode = drm_mode_create(); 3782 if (!mode) 3783 return NULL; 3784 3785 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3786 timing->pixel_clock = cpu_to_le16(1088); 3787 3788 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3789 3790 mode->hdisplay = hactive; 3791 mode->hsync_start = mode->hdisplay + hsync_offset; 3792 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3793 mode->htotal = mode->hdisplay + hblank; 3794 3795 mode->vdisplay = vactive; 3796 mode->vsync_start = mode->vdisplay + vsync_offset; 3797 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3798 mode->vtotal = mode->vdisplay + vblank; 3799 3800 /* Some EDIDs have bogus h/vtotal values */ 3801 if (mode->hsync_end > mode->htotal) 3802 mode->htotal = mode->hsync_end + 1; 3803 if (mode->vsync_end > mode->vtotal) 3804 mode->vtotal = mode->vsync_end + 1; 3805 3806 drm_mode_do_interlace_quirk(mode, pt); 3807 3808 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) 3809 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | 3810 DRM_EDID_PT_VSYNC_POSITIVE; 3811 3812 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3813 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3814 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3815 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3816 3817 set_refresh: 3818 3819 mode->type = DRM_MODE_TYPE_DRIVER; 3820 mode->vrefresh = drm_get_vrefresh(mode); 3821 3822 return mode; 3823 } 3824 3825 /* 3826 * Calculate the alternate clock for the CEA mode 3827 * (60Hz vs. 59.94Hz etc.) 3828 */ 3829 static unsigned int 3830 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3831 { 3832 unsigned int clock = cea_mode->clock; 3833 3834 if (cea_mode->vrefresh % 6 != 0) 3835 return clock; 3836 3837 /* 3838 * edid_cea_modes contains the 59.94Hz 3839 * variant for 240 and 480 line modes, 3840 * and the 60Hz variant otherwise. 3841 */ 3842 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3843 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3844 else 3845 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3846 3847 return clock; 3848 } 3849 3850 /** 3851 * drm_mode_equal_no_clocks_no_stereo - test modes for equality 3852 * @mode1: first mode 3853 * @mode2: second mode 3854 * 3855 * Check to see if @mode1 and @mode2 are equivalent, but 3856 * don't check the pixel clocks nor the stereo layout. 3857 * 3858 * Returns: 3859 * True if the modes are equal, false otherwise. 3860 */ 3861 3862 static 3863 bool drm_mode_equal_no_clocks_no_stereo(const struct drm_display_mode *mode1, 3864 const struct drm_display_mode *mode2) 3865 { 3866 unsigned int flags_mask = 3867 ~(DRM_MODE_FLAG_3D_MASK | DRM_MODE_FLAG_420_MASK); 3868 3869 if (mode1->hdisplay == mode2->hdisplay && 3870 mode1->hsync_start == mode2->hsync_start && 3871 mode1->hsync_end == mode2->hsync_end && 3872 mode1->htotal == mode2->htotal && 3873 mode1->vdisplay == mode2->vdisplay && 3874 mode1->vsync_start == mode2->vsync_start && 3875 mode1->vsync_end == mode2->vsync_end && 3876 mode1->vtotal == mode2->vtotal && 3877 mode1->vscan == mode2->vscan && 3878 (mode1->flags & flags_mask) == (mode2->flags & flags_mask)) 3879 return true; 3880 3881 return false; 3882 } 3883 3884 /** 3885 * drm_mode_equal_no_clocks - test modes for equality 3886 * @mode1: first mode 3887 * @mode2: second mode 3888 * 3889 * Check to see if @mode1 and @mode2 are equivalent, but 3890 * don't check the pixel clocks. 3891 * 3892 * Returns: 3893 * True if the modes are equal, false otherwise. 3894 */ 3895 static bool drm_mode_equal_no_clocks(const struct drm_display_mode *mode1, 3896 const struct drm_display_mode *mode2) 3897 { 3898 if ((mode1->flags & DRM_MODE_FLAG_3D_MASK) != 3899 (mode2->flags & DRM_MODE_FLAG_3D_MASK)) 3900 return false; 3901 3902 return drm_mode_equal_no_clocks_no_stereo(mode1, mode2); 3903 } 3904 3905 static 3906 u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3907 unsigned int clock_tolerance) 3908 { 3909 u8 vic; 3910 3911 if (!to_match->clock) 3912 return 0; 3913 3914 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3915 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 3916 unsigned int clock1, clock2; 3917 3918 /* Check both 60Hz and 59.94Hz */ 3919 clock1 = cea_mode->clock; 3920 clock2 = cea_mode_alternate_clock(cea_mode); 3921 3922 if (abs(to_match->clock - clock1) > clock_tolerance && 3923 abs(to_match->clock - clock2) > clock_tolerance) 3924 continue; 3925 3926 if (drm_mode_equal_no_clocks(to_match, cea_mode)) 3927 return vic; 3928 } 3929 3930 return 0; 3931 } 3932 3933 static unsigned int 3934 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3935 { 3936 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 3937 return hdmi_mode->clock; 3938 3939 return cea_mode_alternate_clock(hdmi_mode); 3940 } 3941 3942 static 3943 u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3944 unsigned int clock_tolerance) 3945 { 3946 u8 vic; 3947 3948 if (!to_match->clock) 3949 return 0; 3950 3951 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3952 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3953 unsigned int clock1, clock2; 3954 3955 /* Make sure to also match alternate clocks */ 3956 clock1 = hdmi_mode->clock; 3957 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3958 3959 if (abs(to_match->clock - clock1) > clock_tolerance && 3960 abs(to_match->clock - clock2) > clock_tolerance) 3961 continue; 3962 3963 if (drm_mode_equal_no_clocks(to_match, hdmi_mode)) 3964 return vic; 3965 } 3966 3967 return 0; 3968 } 3969 3970 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3971 { 3972 const struct drm_display_mode *cea_mode; 3973 int clock1, clock2, clock; 3974 u8 vic; 3975 const char *type; 3976 3977 /* 3978 * allow 5kHz clock difference either way to account for 3979 * the 10kHz clock resolution limit of detailed timings. 3980 */ 3981 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 3982 if (drm_valid_cea_vic(vic)) { 3983 type = "CEA"; 3984 cea_mode = cea_mode_for_vic(vic); 3985 clock1 = cea_mode->clock; 3986 clock2 = cea_mode_alternate_clock(cea_mode); 3987 } else { 3988 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 3989 if (drm_valid_hdmi_vic(vic)) { 3990 type = "HDMI"; 3991 cea_mode = &edid_4k_modes[vic]; 3992 clock1 = cea_mode->clock; 3993 clock2 = hdmi_mode_alternate_clock(cea_mode); 3994 } else { 3995 return; 3996 } 3997 } 3998 3999 /* pick whichever is closest */ 4000 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4001 clock = clock1; 4002 else 4003 clock = clock2; 4004 4005 if (mode->clock == clock) 4006 return; 4007 4008 debug("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4009 type, vic, mode->clock, clock); 4010 mode->clock = clock; 4011 } 4012 4013 static void 4014 do_detailed_mode(struct detailed_timing *timing, void *c) 4015 { 4016 struct detailed_mode_closure *closure = c; 4017 struct drm_display_mode *newmode; 4018 4019 if (timing->pixel_clock) { 4020 newmode = drm_mode_detailed( 4021 closure->edid, timing, 4022 closure->quirks); 4023 if (!newmode) 4024 return; 4025 4026 if (closure->preferred) 4027 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4028 4029 /* 4030 * Detailed modes are limited to 10kHz pixel clock resolution, 4031 * so fix up anything that looks like CEA/HDMI mode, 4032 * but the clock is just slightly off. 4033 */ 4034 fixup_detailed_cea_mode_clock(newmode); 4035 drm_add_hdmi_modes(closure->data, newmode); 4036 drm_mode_destroy(newmode); 4037 closure->modes++; 4038 closure->preferred = 0; 4039 } 4040 } 4041 4042 /* 4043 * add_detailed_modes - Add modes from detailed timings 4044 * @data: attached data 4045 * @edid: EDID block to scan 4046 * @quirks: quirks to apply 4047 */ 4048 static int 4049 add_detailed_modes(struct hdmi_edid_data *data, struct edid *edid, 4050 u32 quirks) 4051 { 4052 struct detailed_mode_closure closure = { 4053 .data = data, 4054 .edid = edid, 4055 .preferred = 1, 4056 .quirks = quirks, 4057 }; 4058 4059 if (closure.preferred && !version_greater(edid, 1, 3)) 4060 closure.preferred = 4061 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 4062 4063 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 4064 4065 return closure.modes; 4066 } 4067 4068 static int drm_cvt_modes(struct hdmi_edid_data *data, 4069 struct detailed_timing *timing) 4070 { 4071 int i, j, modes = 0; 4072 struct drm_display_mode *newmode; 4073 struct cvt_timing *cvt; 4074 const int rates[] = { 60, 85, 75, 60, 50 }; 4075 const u8 empty[3] = { 0, 0, 0 }; 4076 4077 for (i = 0; i < 4; i++) { 4078 int uninitialized_var(width), height; 4079 4080 cvt = &timing->data.other_data.data.cvt[i]; 4081 4082 if (!memcmp(cvt->code, empty, 3)) 4083 continue; 4084 4085 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4086 switch (cvt->code[1] & 0x0c) { 4087 case 0x00: 4088 width = height * 4 / 3; 4089 break; 4090 case 0x04: 4091 width = height * 16 / 9; 4092 break; 4093 case 0x08: 4094 width = height * 16 / 10; 4095 break; 4096 case 0x0c: 4097 width = height * 15 / 9; 4098 break; 4099 } 4100 4101 for (j = 1; j < 5; j++) { 4102 if (cvt->code[2] & (1 << j)) { 4103 newmode = drm_cvt_mode(width, height, 4104 rates[j], j == 0, 4105 false, false); 4106 if (newmode) { 4107 drm_add_hdmi_modes(data, newmode); 4108 modes++; 4109 drm_mode_destroy(newmode); 4110 } 4111 } 4112 } 4113 } 4114 4115 return modes; 4116 } 4117 4118 static void 4119 do_cvt_mode(struct detailed_timing *timing, void *c) 4120 { 4121 struct detailed_mode_closure *closure = c; 4122 struct detailed_non_pixel *data = &timing->data.other_data; 4123 4124 if (data->type == EDID_DETAIL_CVT_3BYTE) 4125 closure->modes += drm_cvt_modes(closure->data, timing); 4126 } 4127 4128 static int 4129 add_cvt_modes(struct hdmi_edid_data *data, struct edid *edid) 4130 { 4131 struct detailed_mode_closure closure = { 4132 .data = data, 4133 .edid = edid, 4134 }; 4135 4136 if (version_greater(edid, 1, 2)) 4137 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 4138 4139 /* XXX should also look for CVT codes in VTB blocks */ 4140 4141 return closure.modes; 4142 } 4143 4144 static void 4145 find_gtf2(struct detailed_timing *t, void *data) 4146 { 4147 u8 *r = (u8 *)t; 4148 4149 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 4150 *(u8 **)data = r; 4151 } 4152 4153 /* Secondary GTF curve kicks in above some break frequency */ 4154 static int 4155 drm_gtf2_hbreak(struct edid *edid) 4156 { 4157 u8 *r = NULL; 4158 4159 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4160 return r ? (r[12] * 2) : 0; 4161 } 4162 4163 static int 4164 drm_gtf2_2c(struct edid *edid) 4165 { 4166 u8 *r = NULL; 4167 4168 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4169 return r ? r[13] : 0; 4170 } 4171 4172 static int 4173 drm_gtf2_m(struct edid *edid) 4174 { 4175 u8 *r = NULL; 4176 4177 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4178 return r ? (r[15] << 8) + r[14] : 0; 4179 } 4180 4181 static int 4182 drm_gtf2_k(struct edid *edid) 4183 { 4184 u8 *r = NULL; 4185 4186 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4187 return r ? r[16] : 0; 4188 } 4189 4190 static int 4191 drm_gtf2_2j(struct edid *edid) 4192 { 4193 u8 *r = NULL; 4194 4195 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 4196 return r ? r[17] : 0; 4197 } 4198 4199 /** 4200 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 4201 * @edid: EDID block to scan 4202 */ 4203 static int standard_timing_level(struct edid *edid) 4204 { 4205 if (edid->revision >= 2) { 4206 if (edid->revision >= 4 && 4207 (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 4208 return LEVEL_CVT; 4209 if (drm_gtf2_hbreak(edid)) 4210 return LEVEL_GTF2; 4211 return LEVEL_GTF; 4212 } 4213 return LEVEL_DMT; 4214 } 4215 4216 /* 4217 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 4218 * monitors fill with ascii space (0x20) instead. 4219 */ 4220 static int 4221 bad_std_timing(u8 a, u8 b) 4222 { 4223 return (a == 0x00 && b == 0x00) || 4224 (a == 0x01 && b == 0x01) || 4225 (a == 0x20 && b == 0x20); 4226 } 4227 4228 static void 4229 is_rb(struct detailed_timing *t, void *data) 4230 { 4231 u8 *r = (u8 *)t; 4232 4233 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 4234 if (r[15] & 0x10) 4235 *(bool *)data = true; 4236 } 4237 4238 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 4239 static bool 4240 drm_monitor_supports_rb(struct edid *edid) 4241 { 4242 if (edid->revision >= 4) { 4243 bool ret = false; 4244 4245 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 4246 return ret; 4247 } 4248 4249 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 4250 } 4251 4252 static bool 4253 mode_is_rb(const struct drm_display_mode *mode) 4254 { 4255 return (mode->htotal - mode->hdisplay == 160) && 4256 (mode->hsync_end - mode->hdisplay == 80) && 4257 (mode->hsync_end - mode->hsync_start == 32) && 4258 (mode->vsync_start - mode->vdisplay == 3); 4259 } 4260 4261 /* 4262 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 4263 * @hsize: Mode width 4264 * @vsize: Mode height 4265 * @fresh: Mode refresh rate 4266 * @rb: Mode reduced-blanking-ness 4267 * 4268 * Walk the DMT mode list looking for a match for the given parameters. 4269 * 4270 * Return: A newly allocated copy of the mode, or NULL if not found. 4271 */ 4272 static struct drm_display_mode *drm_mode_find_dmt( 4273 int hsize, int vsize, int fresh, 4274 bool rb) 4275 { 4276 int i; 4277 struct drm_display_mode *newmode; 4278 4279 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 4280 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 4281 4282 if (hsize != ptr->hdisplay) 4283 continue; 4284 if (vsize != ptr->vdisplay) 4285 continue; 4286 if (fresh != drm_get_vrefresh(ptr)) 4287 continue; 4288 if (rb != mode_is_rb(ptr)) 4289 continue; 4290 4291 newmode = drm_mode_create(); 4292 *newmode = *ptr; 4293 return newmode; 4294 } 4295 4296 return NULL; 4297 } 4298 4299 static struct drm_display_mode * 4300 drm_gtf_mode_complex(int hdisplay, int vdisplay, 4301 int vrefresh, bool interlaced, int margins, 4302 int GTF_M, int GTF_2C, int GTF_K, int GTF_2J) 4303 { /* 1) top/bottom margin size (% of height) - default: 1.8, */ 4304 #define GTF_MARGIN_PERCENTAGE 18 4305 /* 2) character cell horizontal granularity (pixels) - default 8 */ 4306 #define GTF_CELL_GRAN 8 4307 /* 3) Minimum vertical porch (lines) - default 3 */ 4308 #define GTF_MIN_V_PORCH 1 4309 /* width of vsync in lines */ 4310 #define V_SYNC_RQD 3 4311 /* width of hsync as % of total line */ 4312 #define H_SYNC_PERCENT 8 4313 /* min time of vsync + back porch (microsec) */ 4314 #define MIN_VSYNC_PLUS_BP 550 4315 /* C' and M' are part of the Blanking Duty Cycle computation */ 4316 #define GTF_C_PRIME ((((GTF_2C - GTF_2J) * GTF_K / 256) + GTF_2J) / 2) 4317 #define GTF_M_PRIME (GTF_K * GTF_M / 256) 4318 struct drm_display_mode *drm_mode; 4319 unsigned int hdisplay_rnd, vdisplay_rnd, vfieldrate_rqd; 4320 int top_margin, bottom_margin; 4321 int interlace; 4322 unsigned int hfreq_est; 4323 int vsync_plus_bp; 4324 unsigned int vtotal_lines; 4325 int left_margin, right_margin; 4326 unsigned int total_active_pixels, ideal_duty_cycle; 4327 unsigned int hblank, total_pixels, pixel_freq; 4328 int hsync, hfront_porch, vodd_front_porch_lines; 4329 unsigned int tmp1, tmp2; 4330 4331 drm_mode = drm_mode_create(); 4332 if (!drm_mode) 4333 return NULL; 4334 4335 /* 1. In order to give correct results, the number of horizontal 4336 * pixels requested is first processed to ensure that it is divisible 4337 * by the character size, by rounding it to the nearest character 4338 * cell boundary: 4339 */ 4340 hdisplay_rnd = (hdisplay + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4341 hdisplay_rnd = hdisplay_rnd * GTF_CELL_GRAN; 4342 4343 /* 2. If interlace is requested, the number of vertical lines assumed 4344 * by the calculation must be halved, as the computation calculates 4345 * the number of vertical lines per field. 4346 */ 4347 if (interlaced) 4348 vdisplay_rnd = vdisplay / 2; 4349 else 4350 vdisplay_rnd = vdisplay; 4351 4352 /* 3. Find the frame rate required: */ 4353 if (interlaced) 4354 vfieldrate_rqd = vrefresh * 2; 4355 else 4356 vfieldrate_rqd = vrefresh; 4357 4358 /* 4. Find number of lines in Top margin: */ 4359 top_margin = 0; 4360 if (margins) 4361 top_margin = (vdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4362 1000; 4363 /* 5. Find number of lines in bottom margin: */ 4364 bottom_margin = top_margin; 4365 4366 /* 6. If interlace is required, then set variable interlace: */ 4367 if (interlaced) 4368 interlace = 1; 4369 else 4370 interlace = 0; 4371 4372 /* 7. Estimate the Horizontal frequency */ 4373 { 4374 tmp1 = (1000000 - MIN_VSYNC_PLUS_BP * vfieldrate_rqd) / 500; 4375 tmp2 = (vdisplay_rnd + 2 * top_margin + GTF_MIN_V_PORCH) * 4376 2 + interlace; 4377 hfreq_est = (tmp2 * 1000 * vfieldrate_rqd) / tmp1; 4378 } 4379 4380 /* 8. Find the number of lines in V sync + back porch */ 4381 /* [V SYNC+BP] = RINT(([MIN VSYNC+BP] * hfreq_est / 1000000)) */ 4382 vsync_plus_bp = MIN_VSYNC_PLUS_BP * hfreq_est / 1000; 4383 vsync_plus_bp = (vsync_plus_bp + 500) / 1000; 4384 /* 9. Find the number of lines in V back porch alone: 4385 * vback_porch = vsync_plus_bp - V_SYNC_RQD; 4386 */ 4387 /* 10. Find the total number of lines in Vertical field period: */ 4388 vtotal_lines = vdisplay_rnd + top_margin + bottom_margin + 4389 vsync_plus_bp + GTF_MIN_V_PORCH; 4390 /* 11. Estimate the Vertical field frequency: 4391 * vfieldrate_est = hfreq_est / vtotal_lines; 4392 */ 4393 4394 /* 12. Find the actual horizontal period: 4395 * hperiod = 1000000 / (vfieldrate_rqd * vtotal_lines); 4396 */ 4397 /* 13. Find the actual Vertical field frequency: 4398 * vfield_rate = hfreq_est / vtotal_lines; 4399 */ 4400 /* 14. Find the Vertical frame frequency: 4401 * if (interlaced) 4402 * vframe_rate = vfield_rate / 2; 4403 * else 4404 * vframe_rate = vfield_rate; 4405 */ 4406 /* 15. Find number of pixels in left margin: */ 4407 if (margins) 4408 left_margin = (hdisplay_rnd * GTF_MARGIN_PERCENTAGE + 500) / 4409 1000; 4410 else 4411 left_margin = 0; 4412 4413 /* 16.Find number of pixels in right margin: */ 4414 right_margin = left_margin; 4415 /* 17.Find total number of active pixels in image and left and right */ 4416 total_active_pixels = hdisplay_rnd + left_margin + right_margin; 4417 /* 18.Find the ideal blanking duty cycle from blanking duty cycle */ 4418 ideal_duty_cycle = GTF_C_PRIME * 1000 - 4419 (GTF_M_PRIME * 1000000 / hfreq_est); 4420 /* 19.Find the number of pixels in the blanking time to the nearest 4421 * double character cell: 4422 */ 4423 hblank = total_active_pixels * ideal_duty_cycle / 4424 (100000 - ideal_duty_cycle); 4425 hblank = (hblank + GTF_CELL_GRAN) / (2 * GTF_CELL_GRAN); 4426 hblank = hblank * 2 * GTF_CELL_GRAN; 4427 /* 20.Find total number of pixels: */ 4428 total_pixels = total_active_pixels + hblank; 4429 /* 21.Find pixel clock frequency: */ 4430 pixel_freq = total_pixels * hfreq_est / 1000; 4431 /* Stage 1 computations are now complete; I should really pass 4432 * the results to another function and do the Stage 2 computations, 4433 * but I only need a few more values so I'll just append the 4434 * computations here for now 4435 */ 4436 4437 /* 17. Find the number of pixels in the horizontal sync period: */ 4438 hsync = H_SYNC_PERCENT * total_pixels / 100; 4439 hsync = (hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN; 4440 hsync = hsync * GTF_CELL_GRAN; 4441 /* 18. Find the number of pixels in horizontal front porch period */ 4442 hfront_porch = hblank / 2 - hsync; 4443 /* 36. Find the number of lines in the odd front porch period: */ 4444 vodd_front_porch_lines = GTF_MIN_V_PORCH; 4445 4446 /* finally, pack the results in the mode struct */ 4447 drm_mode->hdisplay = hdisplay_rnd; 4448 drm_mode->hsync_start = hdisplay_rnd + hfront_porch; 4449 drm_mode->hsync_end = drm_mode->hsync_start + hsync; 4450 drm_mode->htotal = total_pixels; 4451 drm_mode->vdisplay = vdisplay_rnd; 4452 drm_mode->vsync_start = vdisplay_rnd + vodd_front_porch_lines; 4453 drm_mode->vsync_end = drm_mode->vsync_start + V_SYNC_RQD; 4454 drm_mode->vtotal = vtotal_lines; 4455 4456 drm_mode->clock = pixel_freq; 4457 4458 if (interlaced) { 4459 drm_mode->vtotal *= 2; 4460 drm_mode->flags |= DRM_MODE_FLAG_INTERLACE; 4461 } 4462 4463 if (GTF_M == 600 && GTF_2C == 80 && GTF_K == 128 && GTF_2J == 40) 4464 drm_mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC; 4465 else 4466 drm_mode->flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC; 4467 4468 return drm_mode; 4469 } 4470 4471 /** 4472 * drm_gtf_mode - create the mode based on the GTF algorithm 4473 * @hdisplay: hdisplay size 4474 * @vdisplay: vdisplay size 4475 * @vrefresh: vrefresh rate. 4476 * @interlaced: whether to compute an interlaced mode 4477 * @margins: desired margin (borders) size 4478 * 4479 * return the mode based on GTF algorithm 4480 * 4481 * This function is to create the mode based on the GTF algorithm. 4482 * Generalized Timing Formula is derived from: 4483 * GTF Spreadsheet by Andy Morrish (1/5/97) 4484 * available at http://www.vesa.org 4485 * 4486 * And it is copied from the file of xserver/hw/xfree86/modes/xf86gtf.c. 4487 * What I have done is to translate it by using integer calculation. 4488 * I also refer to the function of fb_get_mode in the file of 4489 * drivers/video/fbmon.c 4490 * 4491 * Standard GTF parameters: 4492 * M = 600 4493 * C = 40 4494 * K = 128 4495 * J = 20 4496 * 4497 * Returns: 4498 * The modeline based on the GTF algorithm stored in a drm_display_mode object. 4499 * The display mode object is allocated with drm_mode_create(). Returns NULL 4500 * when no mode could be allocated. 4501 */ 4502 static struct drm_display_mode * 4503 drm_gtf_mode(int hdisplay, int vdisplay, int vrefresh, 4504 bool interlaced, int margins) 4505 { 4506 return drm_gtf_mode_complex(hdisplay, vdisplay, vrefresh, 4507 interlaced, margins, 4508 600, 40 * 2, 128, 20 * 2); 4509 } 4510 4511 /** drm_mode_hsync - get the hsync of a mode 4512 * @mode: mode 4513 * 4514 * Returns: 4515 * @modes's hsync rate in kHz, rounded to the nearest integer. Calculates the 4516 * value first if it is not yet set. 4517 */ 4518 static int drm_mode_hsync(const struct drm_display_mode *mode) 4519 { 4520 unsigned int calc_val; 4521 4522 if (mode->htotal < 0) 4523 return 0; 4524 4525 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */ 4526 calc_val += 500; /* round to 1000Hz */ 4527 calc_val /= 1000; /* truncate to kHz */ 4528 4529 return calc_val; 4530 } 4531 4532 /** 4533 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 4534 * @data: the structure that save parsed hdmi edid data 4535 * @edid: EDID block to scan 4536 * @t: standard timing params 4537 * 4538 * Take the standard timing params (in this case width, aspect, and refresh) 4539 * and convert them into a real mode using CVT/GTF/DMT. 4540 */ 4541 static struct drm_display_mode * 4542 drm_mode_std(struct hdmi_edid_data *data, struct edid *edid, 4543 struct std_timing *t) 4544 { 4545 struct drm_display_mode *mode = NULL; 4546 int i, hsize, vsize; 4547 int vrefresh_rate; 4548 int num = data->modes; 4549 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 4550 >> EDID_TIMING_ASPECT_SHIFT; 4551 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 4552 >> EDID_TIMING_VFREQ_SHIFT; 4553 int timing_level = standard_timing_level(edid); 4554 4555 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 4556 return NULL; 4557 4558 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 4559 hsize = t->hsize * 8 + 248; 4560 /* vrefresh_rate = vfreq + 60 */ 4561 vrefresh_rate = vfreq + 60; 4562 /* the vdisplay is calculated based on the aspect ratio */ 4563 if (aspect_ratio == 0) { 4564 if (edid->revision < 3) 4565 vsize = hsize; 4566 else 4567 vsize = (hsize * 10) / 16; 4568 } else if (aspect_ratio == 1) { 4569 vsize = (hsize * 3) / 4; 4570 } else if (aspect_ratio == 2) { 4571 vsize = (hsize * 4) / 5; 4572 } else { 4573 vsize = (hsize * 9) / 16; 4574 } 4575 4576 /* HDTV hack, part 1 */ 4577 if (vrefresh_rate == 60 && 4578 ((hsize == 1360 && vsize == 765) || 4579 (hsize == 1368 && vsize == 769))) { 4580 hsize = 1366; 4581 vsize = 768; 4582 } 4583 4584 /* 4585 * If we already has a mode for this size and refresh 4586 * rate (because it came from detailed or CVT info), use that 4587 * instead. This way we don't have to guess at interlace or 4588 * reduced blanking. 4589 */ 4590 for (i = 0; i < num; i++) 4591 if (data->mode_buf[i].hdisplay == hsize && 4592 data->mode_buf[i].vdisplay == vsize && 4593 drm_get_vrefresh(&data->mode_buf[i]) == vrefresh_rate) 4594 return NULL; 4595 4596 /* HDTV hack, part 2 */ 4597 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 4598 mode = drm_cvt_mode(1366, 768, vrefresh_rate, 0, 0, 4599 false); 4600 mode->hdisplay = 1366; 4601 mode->hsync_start = mode->hsync_start - 1; 4602 mode->hsync_end = mode->hsync_end - 1; 4603 return mode; 4604 } 4605 4606 /* check whether it can be found in default mode table */ 4607 if (drm_monitor_supports_rb(edid)) { 4608 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, 4609 true); 4610 if (mode) 4611 return mode; 4612 } 4613 4614 mode = drm_mode_find_dmt(hsize, vsize, vrefresh_rate, false); 4615 if (mode) 4616 return mode; 4617 4618 /* okay, generate it */ 4619 switch (timing_level) { 4620 case LEVEL_DMT: 4621 break; 4622 case LEVEL_GTF: 4623 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4624 break; 4625 case LEVEL_GTF2: 4626 /* 4627 * This is potentially wrong if there's ever a monitor with 4628 * more than one ranges section, each claiming a different 4629 * secondary GTF curve. Please don't do that. 4630 */ 4631 mode = drm_gtf_mode(hsize, vsize, vrefresh_rate, 0, 0); 4632 if (!mode) 4633 return NULL; 4634 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 4635 drm_mode_destroy(mode); 4636 mode = drm_gtf_mode_complex(hsize, vsize, 4637 vrefresh_rate, 0, 0, 4638 drm_gtf2_m(edid), 4639 drm_gtf2_2c(edid), 4640 drm_gtf2_k(edid), 4641 drm_gtf2_2j(edid)); 4642 } 4643 break; 4644 case LEVEL_CVT: 4645 mode = drm_cvt_mode(hsize, vsize, vrefresh_rate, 0, 0, 4646 false); 4647 break; 4648 } 4649 4650 return mode; 4651 } 4652 4653 static void 4654 do_standard_modes(struct detailed_timing *timing, void *c) 4655 { 4656 struct detailed_mode_closure *closure = c; 4657 struct detailed_non_pixel *data = &timing->data.other_data; 4658 struct edid *edid = closure->edid; 4659 4660 if (data->type == EDID_DETAIL_STD_MODES) { 4661 int i; 4662 4663 for (i = 0; i < 6; i++) { 4664 struct std_timing *std; 4665 struct drm_display_mode *newmode; 4666 4667 std = &data->data.timings[i]; 4668 newmode = drm_mode_std(closure->data, edid, std); 4669 if (newmode) { 4670 drm_add_hdmi_modes(closure->data, newmode); 4671 closure->modes++; 4672 drm_mode_destroy(newmode); 4673 } 4674 } 4675 } 4676 } 4677 4678 /** 4679 * add_standard_modes - get std. modes from EDID and add them 4680 * @data: data to add mode(s) to 4681 * @edid: EDID block to scan 4682 * 4683 * Standard modes can be calculated using the appropriate standard (DMT, 4684 * GTF or CVT. Grab them from @edid and add them to the list. 4685 */ 4686 static int 4687 add_standard_modes(struct hdmi_edid_data *data, struct edid *edid) 4688 { 4689 int i, modes = 0; 4690 struct detailed_mode_closure closure = { 4691 .data = data, 4692 .edid = edid, 4693 }; 4694 4695 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4696 struct drm_display_mode *newmode; 4697 4698 newmode = drm_mode_std(data, edid, 4699 &edid->standard_timings[i]); 4700 if (newmode) { 4701 drm_add_hdmi_modes(data, newmode); 4702 modes++; 4703 drm_mode_destroy(newmode); 4704 } 4705 } 4706 4707 if (version_greater(edid, 1, 0)) 4708 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 4709 &closure); 4710 4711 /* XXX should also look for standard codes in VTB blocks */ 4712 4713 return modes + closure.modes; 4714 } 4715 4716 static int 4717 drm_est3_modes(struct hdmi_edid_data *data, struct detailed_timing *timing) 4718 { 4719 int i, j, m, modes = 0; 4720 struct drm_display_mode *mode; 4721 u8 *est = ((u8 *)timing) + 6; 4722 4723 for (i = 0; i < 6; i++) { 4724 for (j = 7; j >= 0; j--) { 4725 m = (i * 8) + (7 - j); 4726 if (m >= ARRAY_SIZE(est3_modes)) 4727 break; 4728 if (est[i] & (1 << j)) { 4729 mode = drm_mode_find_dmt( 4730 est3_modes[m].w, 4731 est3_modes[m].h, 4732 est3_modes[m].r, 4733 est3_modes[m].rb); 4734 if (mode) { 4735 drm_add_hdmi_modes(data, mode); 4736 modes++; 4737 drm_mode_destroy(mode); 4738 } 4739 } 4740 } 4741 } 4742 4743 return modes; 4744 } 4745 4746 static void 4747 do_established_modes(struct detailed_timing *timing, void *c) 4748 { 4749 struct detailed_mode_closure *closure = c; 4750 struct detailed_non_pixel *data = &timing->data.other_data; 4751 4752 if (data->type == EDID_DETAIL_EST_TIMINGS) 4753 closure->modes += drm_est3_modes(closure->data, timing); 4754 } 4755 4756 /** 4757 * add_established_modes - get est. modes from EDID and add them 4758 * @data: data to add mode(s) to 4759 * @edid: EDID block to scan 4760 * 4761 * Each EDID block contains a bitmap of the supported "established modes" list 4762 * (defined above). Tease them out and add them to the modes list. 4763 */ 4764 static int 4765 add_established_modes(struct hdmi_edid_data *data, struct edid *edid) 4766 { 4767 unsigned long est_bits = edid->established_timings.t1 | 4768 (edid->established_timings.t2 << 8) | 4769 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 4770 int i, modes = 0; 4771 struct detailed_mode_closure closure = { 4772 .data = data, 4773 .edid = edid, 4774 }; 4775 4776 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 4777 if (est_bits & (1 << i)) { 4778 struct drm_display_mode *newmode = drm_mode_create(); 4779 *newmode = edid_est_modes[i]; 4780 if (newmode) { 4781 drm_add_hdmi_modes(data, newmode); 4782 modes++; 4783 drm_mode_destroy(newmode); 4784 } 4785 } 4786 } 4787 4788 if (version_greater(edid, 1, 0)) 4789 drm_for_each_detailed_block((u8 *)edid, 4790 do_established_modes, &closure); 4791 4792 return modes + closure.modes; 4793 } 4794 4795 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4796 { 4797 u8 vic; 4798 4799 if (!to_match->clock) 4800 return 0; 4801 4802 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4803 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4804 unsigned int clock1, clock2; 4805 4806 /* Make sure to also match alternate clocks */ 4807 clock1 = hdmi_mode->clock; 4808 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4809 4810 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4811 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4812 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 4813 return vic; 4814 } 4815 return 0; 4816 } 4817 4818 static int 4819 add_alternate_cea_modes(struct hdmi_edid_data *data, struct edid *edid) 4820 { 4821 struct drm_display_mode *mode; 4822 int i, num, modes = 0; 4823 4824 /* Don't add CEA modes if the CEA extension block is missing */ 4825 if (!drm_find_cea_extension(edid)) 4826 return 0; 4827 4828 /* 4829 * Go through all probed modes and create a new mode 4830 * with the alternate clock for certain CEA modes. 4831 */ 4832 num = data->modes; 4833 4834 for (i = 0; i < num; i++) { 4835 const struct drm_display_mode *cea_mode = NULL; 4836 struct drm_display_mode *newmode; 4837 u8 vic; 4838 unsigned int clock1, clock2; 4839 4840 mode = &data->mode_buf[i]; 4841 vic = drm_match_cea_mode(mode); 4842 4843 if (drm_valid_cea_vic(vic)) { 4844 cea_mode = cea_mode_for_vic(vic); 4845 clock2 = cea_mode_alternate_clock(cea_mode); 4846 } else { 4847 vic = drm_match_hdmi_mode(mode); 4848 if (drm_valid_hdmi_vic(vic)) { 4849 cea_mode = &edid_4k_modes[vic]; 4850 clock2 = hdmi_mode_alternate_clock(cea_mode); 4851 } 4852 } 4853 4854 if (!cea_mode) 4855 continue; 4856 4857 clock1 = cea_mode->clock; 4858 4859 if (clock1 == clock2) 4860 continue; 4861 4862 if (mode->clock != clock1 && mode->clock != clock2) 4863 continue; 4864 4865 newmode = drm_mode_create(); 4866 *newmode = *cea_mode; 4867 if (!newmode) 4868 continue; 4869 4870 /* Carry over the stereo flags */ 4871 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4872 4873 /* 4874 * The current mode could be either variant. Make 4875 * sure to pick the "other" clock for the new mode. 4876 */ 4877 if (mode->clock != clock1) 4878 newmode->clock = clock1; 4879 else 4880 newmode->clock = clock2; 4881 4882 drm_add_hdmi_modes(data, newmode); 4883 modes++; 4884 drm_mode_destroy(newmode); 4885 } 4886 4887 return modes; 4888 } 4889 4890 static u8 *drm_find_displayid_extension(struct edid *edid) 4891 { 4892 return drm_find_edid_extension(edid, DISPLAYID_EXT); 4893 } 4894 4895 static int validate_displayid(u8 *displayid, int length, int idx) 4896 { 4897 int i; 4898 u8 csum = 0; 4899 struct displayid_hdr *base; 4900 4901 base = (struct displayid_hdr *)&displayid[idx]; 4902 4903 debug("base revision 0x%x, length %d, %d %d\n", 4904 base->rev, base->bytes, base->prod_id, base->ext_count); 4905 4906 if (base->bytes + 5 > length - idx) 4907 return -EINVAL; 4908 for (i = idx; i <= base->bytes + 5; i++) 4909 csum += displayid[i]; 4910 if (csum) { 4911 debug("DisplayID checksum invalid, remainder is %d\n", csum); 4912 return -EINVAL; 4913 } 4914 return 0; 4915 } 4916 4917 static struct 4918 drm_display_mode *drm_displayid_detailed(struct displayid_detailed_timings_1 4919 *timings) 4920 { 4921 struct drm_display_mode *mode; 4922 unsigned pixel_clock = (timings->pixel_clock[0] | 4923 (timings->pixel_clock[1] << 8) | 4924 (timings->pixel_clock[2] << 16)); 4925 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 4926 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 4927 unsigned hsync = (timings->hsync[0] | 4928 (timings->hsync[1] & 0x7f) << 8) + 1; 4929 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 4930 unsigned vactive = (timings->vactive[0] | 4931 timings->vactive[1] << 8) + 1; 4932 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 4933 unsigned vsync = (timings->vsync[0] | 4934 (timings->vsync[1] & 0x7f) << 8) + 1; 4935 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 4936 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 4937 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 4938 4939 mode = drm_mode_create(); 4940 if (!mode) 4941 return NULL; 4942 4943 mode->clock = pixel_clock * 10; 4944 mode->hdisplay = hactive; 4945 mode->hsync_start = mode->hdisplay + hsync; 4946 mode->hsync_end = mode->hsync_start + hsync_width; 4947 mode->htotal = mode->hdisplay + hblank; 4948 4949 mode->vdisplay = vactive; 4950 mode->vsync_start = mode->vdisplay + vsync; 4951 mode->vsync_end = mode->vsync_start + vsync_width; 4952 mode->vtotal = mode->vdisplay + vblank; 4953 4954 mode->flags = 0; 4955 mode->flags |= 4956 hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 4957 mode->flags |= 4958 vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 4959 mode->type = DRM_MODE_TYPE_DRIVER; 4960 4961 if (timings->flags & 0x80) 4962 mode->type |= DRM_MODE_TYPE_PREFERRED; 4963 mode->vrefresh = drm_get_vrefresh(mode); 4964 4965 return mode; 4966 } 4967 4968 static int add_displayid_detailed_1_modes(struct hdmi_edid_data *data, 4969 struct displayid_block *block) 4970 { 4971 struct displayid_detailed_timing_block *det; 4972 int i; 4973 int num_timings; 4974 struct drm_display_mode *newmode; 4975 int num_modes = 0; 4976 4977 det = (struct displayid_detailed_timing_block *)block; 4978 /* blocks must be multiple of 20 bytes length */ 4979 if (block->num_bytes % 20) 4980 return 0; 4981 4982 num_timings = block->num_bytes / 20; 4983 for (i = 0; i < num_timings; i++) { 4984 struct displayid_detailed_timings_1 *timings = 4985 &det->timings[i]; 4986 4987 newmode = drm_displayid_detailed(timings); 4988 if (!newmode) 4989 continue; 4990 4991 drm_add_hdmi_modes(data, newmode); 4992 num_modes++; 4993 drm_mode_destroy(newmode); 4994 } 4995 return num_modes; 4996 } 4997 4998 static int add_displayid_detailed_modes(struct hdmi_edid_data *data, 4999 struct edid *edid) 5000 { 5001 u8 *displayid; 5002 int ret; 5003 int idx = 1; 5004 int length = EDID_SIZE; 5005 struct displayid_block *block; 5006 int num_modes = 0; 5007 5008 displayid = drm_find_displayid_extension(edid); 5009 if (!displayid) 5010 return 0; 5011 5012 ret = validate_displayid(displayid, length, idx); 5013 if (ret) 5014 return 0; 5015 5016 idx += sizeof(struct displayid_hdr); 5017 while (block = (struct displayid_block *)&displayid[idx], 5018 idx + sizeof(struct displayid_block) <= length && 5019 idx + sizeof(struct displayid_block) + block->num_bytes <= 5020 length && block->num_bytes > 0) { 5021 idx += block->num_bytes + sizeof(struct displayid_block); 5022 switch (block->tag) { 5023 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5024 num_modes += 5025 add_displayid_detailed_1_modes(data, block); 5026 break; 5027 } 5028 } 5029 return num_modes; 5030 } 5031 5032 static bool 5033 mode_in_hsync_range(const struct drm_display_mode *mode, 5034 struct edid *edid, u8 *t) 5035 { 5036 int hsync, hmin, hmax; 5037 5038 hmin = t[7]; 5039 if (edid->revision >= 4) 5040 hmin += ((t[4] & 0x04) ? 255 : 0); 5041 hmax = t[8]; 5042 if (edid->revision >= 4) 5043 hmax += ((t[4] & 0x08) ? 255 : 0); 5044 hsync = drm_mode_hsync(mode); 5045 5046 return (hsync <= hmax && hsync >= hmin); 5047 } 5048 5049 static bool 5050 mode_in_vsync_range(const struct drm_display_mode *mode, 5051 struct edid *edid, u8 *t) 5052 { 5053 int vsync, vmin, vmax; 5054 5055 vmin = t[5]; 5056 if (edid->revision >= 4) 5057 vmin += ((t[4] & 0x01) ? 255 : 0); 5058 vmax = t[6]; 5059 if (edid->revision >= 4) 5060 vmax += ((t[4] & 0x02) ? 255 : 0); 5061 vsync = drm_get_vrefresh(mode); 5062 5063 return (vsync <= vmax && vsync >= vmin); 5064 } 5065 5066 static u32 5067 range_pixel_clock(struct edid *edid, u8 *t) 5068 { 5069 /* unspecified */ 5070 if (t[9] == 0 || t[9] == 255) 5071 return 0; 5072 5073 /* 1.4 with CVT support gives us real precision, yay */ 5074 if (edid->revision >= 4 && t[10] == 0x04) 5075 return (t[9] * 10000) - ((t[12] >> 2) * 250); 5076 5077 /* 1.3 is pathetic, so fuzz up a bit */ 5078 return t[9] * 10000 + 5001; 5079 } 5080 5081 static bool 5082 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 5083 struct detailed_timing *timing) 5084 { 5085 u32 max_clock; 5086 u8 *t = (u8 *)timing; 5087 5088 if (!mode_in_hsync_range(mode, edid, t)) 5089 return false; 5090 5091 if (!mode_in_vsync_range(mode, edid, t)) 5092 return false; 5093 5094 max_clock = range_pixel_clock(edid, t); 5095 if (max_clock) 5096 if (mode->clock > max_clock) 5097 return false; 5098 5099 /* 1.4 max horizontal check */ 5100 if (edid->revision >= 4 && t[10] == 0x04) 5101 if (t[13] && mode->hdisplay > 8 * 5102 (t[13] + (256 * (t[12] & 0x3)))) 5103 return false; 5104 5105 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 5106 return false; 5107 5108 return true; 5109 } 5110 5111 static bool valid_inferred_mode(struct hdmi_edid_data *data, 5112 const struct drm_display_mode *mode) 5113 { 5114 const struct drm_display_mode *m; 5115 bool ok = false; 5116 int i; 5117 5118 for (i = 0; i < data->modes; i++) { 5119 m = &data->mode_buf[i]; 5120 if (mode->hdisplay == m->hdisplay && 5121 mode->vdisplay == m->vdisplay && 5122 drm_get_vrefresh(mode) == drm_get_vrefresh(m)) 5123 return false; /* duplicated */ 5124 if (mode->hdisplay <= m->hdisplay && 5125 mode->vdisplay <= m->vdisplay) 5126 ok = true; 5127 } 5128 return ok; 5129 } 5130 5131 static int 5132 drm_dmt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5133 struct detailed_timing *timing) 5134 { 5135 int i, modes = 0; 5136 5137 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 5138 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 5139 valid_inferred_mode(data, drm_dmt_modes + i)) { 5140 drm_add_hdmi_modes(data, &drm_dmt_modes[i]); 5141 modes++; 5142 } 5143 } 5144 5145 return modes; 5146 } 5147 5148 /* fix up 1366x768 mode from 1368x768; 5149 * GFT/CVT can't express 1366 width which isn't dividable by 8 5150 */ 5151 static void fixup_mode_1366x768(struct drm_display_mode *mode) 5152 { 5153 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 5154 mode->hdisplay = 1366; 5155 mode->hsync_start--; 5156 mode->hsync_end--; 5157 } 5158 } 5159 5160 static int 5161 drm_gtf_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5162 struct detailed_timing *timing) 5163 { 5164 int i, modes = 0; 5165 struct drm_display_mode *newmode; 5166 5167 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5168 const struct minimode *m = &extra_modes[i]; 5169 5170 newmode = drm_gtf_mode(m->w, m->h, m->r, 0, 0); 5171 if (!newmode) 5172 return modes; 5173 5174 fixup_mode_1366x768(newmode); 5175 if (!mode_in_range(newmode, edid, timing) || 5176 !valid_inferred_mode(data, newmode)) { 5177 drm_mode_destroy(newmode); 5178 continue; 5179 } 5180 5181 drm_add_hdmi_modes(data, newmode); 5182 modes++; 5183 drm_mode_destroy(newmode); 5184 } 5185 5186 return modes; 5187 } 5188 5189 static int 5190 drm_cvt_modes_for_range(struct hdmi_edid_data *data, struct edid *edid, 5191 struct detailed_timing *timing) 5192 { 5193 int i, modes = 0; 5194 struct drm_display_mode *newmode; 5195 bool rb = drm_monitor_supports_rb(edid); 5196 5197 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 5198 const struct minimode *m = &extra_modes[i]; 5199 5200 newmode = drm_cvt_mode(m->w, m->h, m->r, rb, 0, 0); 5201 if (!newmode) 5202 return modes; 5203 5204 fixup_mode_1366x768(newmode); 5205 if (!mode_in_range(newmode, edid, timing) || 5206 !valid_inferred_mode(data, newmode)) { 5207 drm_mode_destroy(newmode); 5208 continue; 5209 } 5210 5211 drm_add_hdmi_modes(data, newmode); 5212 modes++; 5213 drm_mode_destroy(newmode); 5214 } 5215 5216 return modes; 5217 } 5218 5219 static void 5220 do_inferred_modes(struct detailed_timing *timing, void *c) 5221 { 5222 struct detailed_mode_closure *closure = c; 5223 struct detailed_non_pixel *data = &timing->data.other_data; 5224 struct detailed_data_monitor_range *range = &data->data.range; 5225 5226 if (data->type != EDID_DETAIL_MONITOR_RANGE) 5227 return; 5228 5229 closure->modes += drm_dmt_modes_for_range(closure->data, 5230 closure->edid, 5231 timing); 5232 5233 if (!version_greater(closure->edid, 1, 1)) 5234 return; /* GTF not defined yet */ 5235 5236 switch (range->flags) { 5237 case 0x02: /* secondary gtf, XXX could do more */ 5238 case 0x00: /* default gtf */ 5239 closure->modes += drm_gtf_modes_for_range(closure->data, 5240 closure->edid, 5241 timing); 5242 break; 5243 case 0x04: /* cvt, only in 1.4+ */ 5244 if (!version_greater(closure->edid, 1, 3)) 5245 break; 5246 5247 closure->modes += drm_cvt_modes_for_range(closure->data, 5248 closure->edid, 5249 timing); 5250 break; 5251 case 0x01: /* just the ranges, no formula */ 5252 default: 5253 break; 5254 } 5255 } 5256 5257 static int 5258 add_inferred_modes(struct hdmi_edid_data *data, struct edid *edid) 5259 { 5260 struct detailed_mode_closure closure = { 5261 .data = data, 5262 .edid = edid, 5263 }; 5264 5265 if (version_greater(edid, 1, 0)) 5266 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 5267 &closure); 5268 5269 return closure.modes; 5270 } 5271 5272 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 5273 #define MODE_REFRESH_DIFF(c, t) (abs((c) - (t))) 5274 5275 /** 5276 * edid_fixup_preferred - set preferred modes based on quirk list 5277 * @data: the structure that save parsed hdmi edid data 5278 * @quirks: quirks list 5279 * 5280 * Walk the mode list, clearing the preferred status 5281 * on existing modes and setting it anew for the right mode ala @quirks. 5282 */ 5283 static void edid_fixup_preferred(struct hdmi_edid_data *data, 5284 u32 quirks) 5285 { 5286 struct drm_display_mode *cur_mode, *preferred_mode; 5287 int i, target_refresh = 0; 5288 int num = data->modes; 5289 int cur_vrefresh, preferred_vrefresh; 5290 5291 if (!num) 5292 return; 5293 5294 preferred_mode = data->preferred_mode; 5295 5296 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 5297 target_refresh = 60; 5298 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 5299 target_refresh = 75; 5300 5301 for (i = 0; i < num; i++) { 5302 cur_mode = &data->mode_buf[i]; 5303 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 5304 5305 if (cur_mode == preferred_mode) 5306 continue; 5307 5308 /* Largest mode is preferred */ 5309 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 5310 preferred_mode = cur_mode; 5311 5312 cur_vrefresh = cur_mode->vrefresh ? 5313 cur_mode->vrefresh : drm_get_vrefresh(cur_mode); 5314 preferred_vrefresh = preferred_mode->vrefresh ? 5315 preferred_mode->vrefresh : drm_get_vrefresh(preferred_mode); 5316 /* At a given size, try to get closest to target refresh */ 5317 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 5318 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 5319 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 5320 preferred_mode = cur_mode; 5321 } 5322 } 5323 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 5324 data->preferred_mode = preferred_mode; 5325 } 5326 5327 static const u8 edid_header[] = { 5328 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 5329 }; 5330 5331 /** 5332 * drm_edid_header_is_valid - sanity check the header of the base EDID block 5333 * @raw_edid: pointer to raw base EDID block 5334 * 5335 * Sanity check the header of the base EDID block. 5336 * 5337 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 5338 */ 5339 static int drm_edid_header_is_valid(const u8 *raw_edid) 5340 { 5341 int i, score = 0; 5342 5343 for (i = 0; i < sizeof(edid_header); i++) 5344 if (raw_edid[i] == edid_header[i]) 5345 score++; 5346 5347 return score; 5348 } 5349 5350 static int drm_edid_block_checksum(const u8 *raw_edid) 5351 { 5352 int i; 5353 u8 csum = 0; 5354 5355 for (i = 0; i < EDID_SIZE; i++) 5356 csum += raw_edid[i]; 5357 5358 return csum; 5359 } 5360 5361 static bool drm_edid_is_zero(const u8 *in_edid, int length) 5362 { 5363 if (memchr_inv(in_edid, 0, length)) 5364 return false; 5365 5366 return true; 5367 } 5368 5369 /** 5370 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 5371 * @raw_edid: pointer to raw EDID block 5372 * @block: type of block to validate (0 for base, extension otherwise) 5373 * @print_bad_edid: if true, dump bad EDID blocks to the console 5374 * @edid_corrupt: if true, the header or checksum is invalid 5375 * 5376 * Validate a base or extension EDID block and optionally dump bad blocks to 5377 * the console. 5378 * 5379 * Return: True if the block is valid, false otherwise. 5380 */ 5381 static 5382 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 5383 bool *edid_corrupt) 5384 { 5385 u8 csum; 5386 int edid_fixup = 6; 5387 struct edid *edid = (struct edid *)raw_edid; 5388 5389 if ((!raw_edid)) 5390 return false; 5391 5392 if (block == 0) { 5393 int score = drm_edid_header_is_valid(raw_edid); 5394 5395 if (score == 8) { 5396 if (edid_corrupt) 5397 *edid_corrupt = false; 5398 } else if (score >= edid_fixup) { 5399 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 5400 * The corrupt flag needs to be set here otherwise, the 5401 * fix-up code here will correct the problem, the 5402 * checksum is correct and the test fails 5403 */ 5404 if (edid_corrupt) 5405 *edid_corrupt = true; 5406 debug("Fixing header, your hardware may be failing\n"); 5407 memcpy(raw_edid, edid_header, sizeof(edid_header)); 5408 } else { 5409 if (edid_corrupt) 5410 *edid_corrupt = true; 5411 goto bad; 5412 } 5413 } 5414 5415 csum = drm_edid_block_checksum(raw_edid); 5416 if (csum) { 5417 if (print_bad_edid) { 5418 debug("EDID checksum is invalid, remainder is %d\n", 5419 csum); 5420 } 5421 5422 if (edid_corrupt) 5423 *edid_corrupt = true; 5424 5425 /* allow CEA to slide through, switches mangle this */ 5426 if (raw_edid[0] != 0x02) 5427 goto bad; 5428 } 5429 5430 /* per-block-type checks */ 5431 switch (raw_edid[0]) { 5432 case 0: /* base */ 5433 if (edid->version != 1) { 5434 debug("EDID has major version %d, instead of 1\n", 5435 edid->version); 5436 goto bad; 5437 } 5438 5439 if (edid->revision > 4) 5440 debug("minor > 4, assuming backward compatibility\n"); 5441 break; 5442 5443 default: 5444 break; 5445 } 5446 5447 return true; 5448 5449 bad: 5450 if (print_bad_edid) { 5451 if (drm_edid_is_zero(raw_edid, EDID_SIZE)) { 5452 debug("EDID block is all zeroes\n"); 5453 } else { 5454 debug("Raw EDID:\n"); 5455 print_hex_dump("", DUMP_PREFIX_NONE, 16, 1, 5456 raw_edid, EDID_SIZE, false); 5457 } 5458 } 5459 return false; 5460 } 5461 5462 /** 5463 * drm_edid_is_valid - sanity check EDID data 5464 * @edid: EDID data 5465 * 5466 * Sanity-check an entire EDID record (including extensions) 5467 * 5468 * Return: True if the EDID data is valid, false otherwise. 5469 */ 5470 static bool drm_edid_is_valid(struct edid *edid) 5471 { 5472 int i; 5473 u8 *raw = (u8 *)edid; 5474 5475 if (!edid) 5476 return false; 5477 5478 for (i = 0; i <= edid->extensions; i++) 5479 if (!drm_edid_block_valid(raw + i * EDID_SIZE, i, true, NULL)) 5480 return false; 5481 5482 return true; 5483 } 5484 5485 /** 5486 * drm_add_edid_modes - add modes from EDID data, if available 5487 * @data: data we're probing 5488 * @edid: EDID data 5489 * 5490 * Add the specified modes to the data's mode list. 5491 * 5492 * Return: The number of modes added or 0 if we couldn't find any. 5493 */ 5494 int drm_add_edid_modes(struct hdmi_edid_data *data, u8 *raw_edid) 5495 { 5496 int num_modes = 0; 5497 u32 quirks; 5498 struct edid *edid = (struct edid *)raw_edid; 5499 5500 if (!edid) { 5501 debug("no edid\n"); 5502 return 0; 5503 } 5504 5505 if (!drm_edid_is_valid(edid)) { 5506 debug("EDID invalid\n"); 5507 return 0; 5508 } 5509 5510 if (!data->mode_buf) { 5511 debug("mode buff is null\n"); 5512 return 0; 5513 } 5514 5515 quirks = edid_get_quirks(edid); 5516 /* 5517 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5518 * To avoid multiple parsing of same block, lets parse that map 5519 * from sink info, before parsing CEA modes. 5520 */ 5521 drm_add_display_info(data, edid); 5522 5523 /* 5524 * EDID spec says modes should be preferred in this order: 5525 * - preferred detailed mode 5526 * - other detailed modes from base block 5527 * - detailed modes from extension blocks 5528 * - CVT 3-byte code modes 5529 * - standard timing codes 5530 * - established timing codes 5531 * - modes inferred from GTF or CVT range information 5532 * 5533 * We get this pretty much right. 5534 * 5535 * XXX order for additional mode types in extension blocks? 5536 */ 5537 num_modes += add_detailed_modes(data, edid, quirks); 5538 num_modes += add_cvt_modes(data, edid); 5539 num_modes += add_standard_modes(data, edid); 5540 num_modes += add_established_modes(data, edid); 5541 num_modes += add_cea_modes(data, edid); 5542 num_modes += add_alternate_cea_modes(data, edid); 5543 num_modes += add_displayid_detailed_modes(data, edid); 5544 5545 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5546 num_modes += add_inferred_modes(data, edid); 5547 5548 if (num_modes > 0) 5549 data->preferred_mode = &data->mode_buf[0]; 5550 5551 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5552 edid_fixup_preferred(data, quirks); 5553 5554 if (quirks & EDID_QUIRK_FORCE_6BPC) 5555 data->display_info.bpc = 6; 5556 5557 if (quirks & EDID_QUIRK_FORCE_8BPC) 5558 data->display_info.bpc = 8; 5559 5560 if (quirks & EDID_QUIRK_FORCE_10BPC) 5561 data->display_info.bpc = 10; 5562 5563 if (quirks & EDID_QUIRK_FORCE_12BPC) 5564 data->display_info.bpc = 12; 5565 5566 return num_modes; 5567 } 5568 5569 u8 drm_match_cea_mode(struct drm_display_mode *to_match) 5570 { 5571 u8 vic; 5572 5573 if (!to_match->clock) { 5574 printf("can't find to match\n"); 5575 return 0; 5576 } 5577 5578 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 5579 const struct drm_display_mode *cea_mode = cea_mode_for_vic(vic); 5580 unsigned int clock1, clock2; 5581 5582 /* Check both 60Hz and 59.94Hz */ 5583 clock1 = cea_mode->clock; 5584 clock2 = cea_mode_alternate_clock(cea_mode); 5585 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 5586 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 5587 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 5588 return vic; 5589 } 5590 5591 return 0; 5592 } 5593 5594 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 5595 { 5596 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 5597 5598 if (mode) 5599 return mode->picture_aspect_ratio; 5600 5601 return HDMI_PICTURE_ASPECT_NONE; 5602 } 5603 5604 int 5605 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5606 struct drm_display_mode *mode, 5607 bool is_hdmi2_sink) 5608 { 5609 int err; 5610 5611 if (!frame || !mode) 5612 return -EINVAL; 5613 5614 err = hdmi_avi_infoframe_init(frame); 5615 if (err < 0) 5616 return err; 5617 5618 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5619 frame->pixel_repeat = 1; 5620 5621 frame->video_code = drm_match_cea_mode(mode); 5622 5623 /* 5624 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5625 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5626 * have to make sure we dont break HDMI 1.4 sinks. 5627 */ 5628 if (!is_hdmi2_sink && frame->video_code > 64) 5629 frame->video_code = 0; 5630 5631 /* 5632 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5633 * we should send its VIC in vendor infoframes, else send the 5634 * VIC in AVI infoframes. Lets check if this mode is present in 5635 * HDMI 1.4b 4K modes 5636 */ 5637 if (frame->video_code) { 5638 u8 vendor_if_vic = drm_match_hdmi_mode(mode); 5639 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK; 5640 5641 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d) 5642 frame->video_code = 0; 5643 } 5644 5645 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5646 5647 /* 5648 * Populate picture aspect ratio from either 5649 * user input (if specified) or from the CEA mode list. 5650 */ 5651 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 5652 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 5653 frame->picture_aspect = mode->picture_aspect_ratio; 5654 else if (frame->video_code > 0) 5655 frame->picture_aspect = drm_get_cea_aspect_ratio( 5656 frame->video_code); 5657 5658 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5659 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5660 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5661 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5662 5663 return 0; 5664 } 5665 5666 /** 5667 * hdmi_vendor_infoframe_init() - initialize an HDMI vendor infoframe 5668 * @frame: HDMI vendor infoframe 5669 * 5670 * Returns 0 on success or a negative error code on failure. 5671 */ 5672 int hdmi_vendor_infoframe_init(struct hdmi_vendor_infoframe *frame) 5673 { 5674 memset(frame, 0, sizeof(*frame)); 5675 5676 frame->type = HDMI_INFOFRAME_TYPE_VENDOR; 5677 frame->version = 1; 5678 5679 frame->oui = HDMI_IEEE_OUI; 5680 5681 /* 5682 * 0 is a valid value for s3d_struct, so we use a special "not set" 5683 * value 5684 */ 5685 frame->s3d_struct = HDMI_3D_STRUCTURE_INVALID; 5686 5687 return 0; 5688 } 5689 5690 /** 5691 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5692 * quantization range information 5693 * @frame: HDMI AVI infoframe 5694 * @rgb_quant_range: RGB quantization range (Q) 5695 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS) 5696 */ 5697 void 5698 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5699 struct drm_display_mode *mode, 5700 enum hdmi_quantization_range rgb_quant_range, 5701 bool rgb_quant_range_selectable) 5702 { 5703 /* 5704 * CEA-861: 5705 * "A Source shall not send a non-zero Q value that does not correspond 5706 * to the default RGB Quantization Range for the transmitted Picture 5707 * unless the Sink indicates support for the Q bit in a Video 5708 * Capabilities Data Block." 5709 * 5710 * HDMI 2.0 recommends sending non-zero Q when it does match the 5711 * default RGB quantization range for the mode, even when QS=0. 5712 */ 5713 if (rgb_quant_range_selectable || 5714 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5715 frame->quantization_range = rgb_quant_range; 5716 else 5717 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5718 5719 /* 5720 * CEA-861-F: 5721 * "When transmitting any RGB colorimetry, the Source should set the 5722 * YQ-field to match the RGB Quantization Range being transmitted 5723 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5724 * set YQ=1) and the Sink shall ignore the YQ-field." 5725 */ 5726 if (rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5727 frame->ycc_quantization_range = 5728 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5729 else 5730 frame->ycc_quantization_range = 5731 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5732 } 5733 5734 static enum hdmi_3d_structure 5735 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5736 { 5737 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5738 5739 switch (layout) { 5740 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5741 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5742 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5743 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5744 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5745 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5746 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5747 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5748 case DRM_MODE_FLAG_3D_L_DEPTH: 5749 return HDMI_3D_STRUCTURE_L_DEPTH; 5750 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5751 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5752 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5753 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5754 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5755 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5756 default: 5757 return HDMI_3D_STRUCTURE_INVALID; 5758 } 5759 } 5760 5761 int 5762 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5763 struct drm_display_mode *mode) 5764 { 5765 int err; 5766 u32 s3d_flags; 5767 u8 vic; 5768 5769 if (!frame || !mode) 5770 return -EINVAL; 5771 5772 vic = drm_match_hdmi_mode(mode); 5773 5774 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 5775 5776 if (!vic && !s3d_flags) 5777 return -EINVAL; 5778 5779 if (vic && s3d_flags) 5780 return -EINVAL; 5781 5782 err = hdmi_vendor_infoframe_init(frame); 5783 if (err < 0) 5784 return err; 5785 5786 if (vic) 5787 frame->vic = vic; 5788 else 5789 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5790 5791 return 0; 5792 } 5793 5794 static u8 hdmi_infoframe_checksum(u8 *ptr, size_t size) 5795 { 5796 u8 csum = 0; 5797 size_t i; 5798 5799 /* compute checksum */ 5800 for (i = 0; i < size; i++) 5801 csum += ptr[i]; 5802 5803 return 256 - csum; 5804 } 5805 5806 static void hdmi_infoframe_set_checksum(void *buffer, size_t size) 5807 { 5808 u8 *ptr = buffer; 5809 5810 ptr[3] = hdmi_infoframe_checksum(buffer, size); 5811 } 5812 5813 /** 5814 * hdmi_avi_infoframe_init() - initialize an HDMI AVI infoframe 5815 * @frame: HDMI AVI infoframe 5816 * 5817 * Returns 0 on success or a negative error code on failure. 5818 */ 5819 int hdmi_avi_infoframe_init(struct hdmi_avi_infoframe *frame) 5820 { 5821 memset(frame, 0, sizeof(*frame)); 5822 5823 frame->type = HDMI_INFOFRAME_TYPE_AVI; 5824 frame->version = 2; 5825 frame->length = HDMI_AVI_INFOFRAME_SIZE; 5826 5827 return 0; 5828 } 5829 EXPORT_SYMBOL(hdmi_avi_infoframe_init); 5830 5831 /** 5832 * hdmi_avi_infoframe_pack() - write HDMI AVI infoframe to binary buffer 5833 * @frame: HDMI AVI infoframe 5834 * @buffer: destination buffer 5835 * @size: size of buffer 5836 * 5837 * Packs the information contained in the @frame structure into a binary 5838 * representation that can be written into the corresponding controller 5839 * registers. Also computes the checksum as required by section 5.3.5 of 5840 * the HDMI 1.4 specification. 5841 * 5842 * Returns the number of bytes packed into the binary buffer or a negative 5843 * error code on failure. 5844 */ 5845 ssize_t hdmi_avi_infoframe_pack(struct hdmi_avi_infoframe *frame, void *buffer, 5846 size_t size) 5847 { 5848 u8 *ptr = buffer; 5849 size_t length; 5850 5851 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5852 5853 if (size < length) 5854 return -ENOSPC; 5855 5856 memset(buffer, 0, size); 5857 5858 ptr[0] = frame->type; 5859 ptr[1] = frame->version; 5860 ptr[2] = frame->length; 5861 ptr[3] = 0; /* checksum */ 5862 5863 /* start infoframe payload */ 5864 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5865 5866 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5867 5868 /* 5869 * Data byte 1, bit 4 has to be set if we provide the active format 5870 * aspect ratio 5871 */ 5872 if (frame->active_aspect & 0xf) 5873 ptr[0] |= BIT(4); 5874 5875 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5876 if (frame->top_bar || frame->bottom_bar) 5877 ptr[0] |= BIT(3); 5878 5879 if (frame->left_bar || frame->right_bar) 5880 ptr[0] |= BIT(2); 5881 5882 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5883 ((frame->picture_aspect & 0x3) << 4) | 5884 (frame->active_aspect & 0xf); 5885 5886 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 5887 ((frame->quantization_range & 0x3) << 2) | 5888 (frame->nups & 0x3); 5889 5890 if (frame->itc) 5891 ptr[2] |= BIT(7); 5892 5893 ptr[3] = frame->video_code & 0x7f; 5894 5895 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 5896 ((frame->content_type & 0x3) << 4) | 5897 (frame->pixel_repeat & 0xf); 5898 5899 ptr[5] = frame->top_bar & 0xff; 5900 ptr[6] = (frame->top_bar >> 8) & 0xff; 5901 ptr[7] = frame->bottom_bar & 0xff; 5902 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 5903 ptr[9] = frame->left_bar & 0xff; 5904 ptr[10] = (frame->left_bar >> 8) & 0xff; 5905 ptr[11] = frame->right_bar & 0xff; 5906 ptr[12] = (frame->right_bar >> 8) & 0xff; 5907 5908 hdmi_infoframe_set_checksum(buffer, length); 5909 5910 return length; 5911 } 5912 EXPORT_SYMBOL(hdmi_avi_infoframe_pack); 5913 5914 static int hdmi_avi_infoframe_check_only(const struct hdmi_avi_infoframe *frame) 5915 { 5916 if (frame->type != HDMI_INFOFRAME_TYPE_AVI || 5917 frame->version != 2 || 5918 frame->length != HDMI_AVI_INFOFRAME_SIZE) 5919 return -EINVAL; 5920 5921 if (frame->picture_aspect > HDMI_PICTURE_ASPECT_16_9) 5922 return -EINVAL; 5923 5924 return 0; 5925 } 5926 5927 /** 5928 * hdmi_avi_infoframe_check() - check a HDMI AVI infoframe 5929 * @frame: HDMI AVI infoframe 5930 * 5931 * Validates that the infoframe is consistent and updates derived fields 5932 * (eg. length) based on other fields. 5933 * 5934 * Returns 0 on success or a negative error code on failure. 5935 */ 5936 int hdmi_avi_infoframe_check(struct hdmi_avi_infoframe *frame) 5937 { 5938 return hdmi_avi_infoframe_check_only(frame); 5939 } 5940 EXPORT_SYMBOL(hdmi_avi_infoframe_check); 5941 5942 /** 5943 * hdmi_avi_infoframe_pack_only() - write HDMI AVI infoframe to binary buffer 5944 * @frame: HDMI AVI infoframe 5945 * @buffer: destination buffer 5946 * @size: size of buffer 5947 * 5948 * Packs the information contained in the @frame structure into a binary 5949 * representation that can be written into the corresponding controller 5950 * registers. Also computes the checksum as required by section 5.3.5 of 5951 * the HDMI 1.4 specification. 5952 * 5953 * Returns the number of bytes packed into the binary buffer or a negative 5954 * error code on failure. 5955 */ 5956 ssize_t hdmi_avi_infoframe_pack_only(const struct hdmi_avi_infoframe *frame, 5957 void *buffer, size_t size) 5958 { 5959 u8 *ptr = buffer; 5960 size_t length; 5961 int ret; 5962 5963 ret = hdmi_avi_infoframe_check_only(frame); 5964 if (ret) 5965 return ret; 5966 5967 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 5968 5969 if (size < length) 5970 return -ENOSPC; 5971 5972 memset(buffer, 0, size); 5973 5974 ptr[0] = frame->type; 5975 ptr[1] = frame->version; 5976 ptr[2] = frame->length; 5977 ptr[3] = 0; /* checksum */ 5978 5979 /* start infoframe payload */ 5980 ptr += HDMI_INFOFRAME_HEADER_SIZE; 5981 5982 ptr[0] = ((frame->colorspace & 0x3) << 5) | (frame->scan_mode & 0x3); 5983 5984 /* 5985 * Data byte 1, bit 4 has to be set if we provide the active format 5986 * aspect ratio 5987 */ 5988 if (frame->active_aspect & 0xf) 5989 ptr[0] |= BIT(4); 5990 5991 /* Bit 3 and 2 indicate if we transmit horizontal/vertical bar data */ 5992 if (frame->top_bar || frame->bottom_bar) 5993 ptr[0] |= BIT(3); 5994 5995 if (frame->left_bar || frame->right_bar) 5996 ptr[0] |= BIT(2); 5997 5998 ptr[1] = ((frame->colorimetry & 0x3) << 6) | 5999 ((frame->picture_aspect & 0x3) << 4) | 6000 (frame->active_aspect & 0xf); 6001 6002 ptr[2] = ((frame->extended_colorimetry & 0x7) << 4) | 6003 ((frame->quantization_range & 0x3) << 2) | 6004 (frame->nups & 0x3); 6005 6006 if (frame->itc) 6007 ptr[2] |= BIT(7); 6008 6009 ptr[3] = frame->video_code & 0xff; 6010 6011 ptr[4] = ((frame->ycc_quantization_range & 0x3) << 6) | 6012 ((frame->content_type & 0x3) << 4) | 6013 (frame->pixel_repeat & 0xf); 6014 6015 ptr[5] = frame->top_bar & 0xff; 6016 ptr[6] = (frame->top_bar >> 8) & 0xff; 6017 ptr[7] = frame->bottom_bar & 0xff; 6018 ptr[8] = (frame->bottom_bar >> 8) & 0xff; 6019 ptr[9] = frame->left_bar & 0xff; 6020 ptr[10] = (frame->left_bar >> 8) & 0xff; 6021 ptr[11] = frame->right_bar & 0xff; 6022 ptr[12] = (frame->right_bar >> 8) & 0xff; 6023 6024 hdmi_infoframe_set_checksum(buffer, length); 6025 6026 return length; 6027 } 6028 EXPORT_SYMBOL(hdmi_avi_infoframe_pack_only); 6029 6030 /** 6031 * hdmi_spd_infoframe_init() - initialize an HDMI SPD infoframe 6032 * @frame: HDMI SPD infoframe 6033 * @vendor: vendor string 6034 * @product: product string 6035 * 6036 * Returns 0 on success or a negative error code on failure. 6037 */ 6038 int hdmi_spd_infoframe_init(struct hdmi_spd_infoframe *frame, 6039 const char *vendor, const char *product) 6040 { 6041 memset(frame, 0, sizeof(*frame)); 6042 6043 frame->type = HDMI_INFOFRAME_TYPE_SPD; 6044 frame->version = 1; 6045 frame->length = HDMI_SPD_INFOFRAME_SIZE; 6046 6047 strncpy(frame->vendor, vendor, sizeof(frame->vendor)); 6048 strncpy(frame->product, product, sizeof(frame->product)); 6049 6050 return 0; 6051 } 6052 EXPORT_SYMBOL(hdmi_spd_infoframe_init); 6053 6054 /** 6055 * hdmi_spd_infoframe_pack() - write HDMI SPD infoframe to binary buffer 6056 * @frame: HDMI SPD infoframe 6057 * @buffer: destination buffer 6058 * @size: size of buffer 6059 * 6060 * Packs the information contained in the @frame structure into a binary 6061 * representation that can be written into the corresponding controller 6062 * registers. Also computes the checksum as required by section 5.3.5 of 6063 * the HDMI 1.4 specification. 6064 * 6065 * Returns the number of bytes packed into the binary buffer or a negative 6066 * error code on failure. 6067 */ 6068 ssize_t hdmi_spd_infoframe_pack(struct hdmi_spd_infoframe *frame, void *buffer, 6069 size_t size) 6070 { 6071 u8 *ptr = buffer; 6072 size_t length; 6073 6074 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6075 6076 if (size < length) 6077 return -ENOSPC; 6078 6079 memset(buffer, 0, size); 6080 6081 ptr[0] = frame->type; 6082 ptr[1] = frame->version; 6083 ptr[2] = frame->length; 6084 ptr[3] = 0; /* checksum */ 6085 6086 /* start infoframe payload */ 6087 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6088 6089 memcpy(ptr, frame->vendor, sizeof(frame->vendor)); 6090 memcpy(ptr + 8, frame->product, sizeof(frame->product)); 6091 6092 ptr[24] = frame->sdi; 6093 6094 hdmi_infoframe_set_checksum(buffer, length); 6095 6096 return length; 6097 } 6098 EXPORT_SYMBOL(hdmi_spd_infoframe_pack); 6099 6100 /** 6101 * hdmi_audio_infoframe_init() - initialize an HDMI audio infoframe 6102 * @frame: HDMI audio infoframe 6103 * 6104 * Returns 0 on success or a negative error code on failure. 6105 */ 6106 int hdmi_audio_infoframe_init(struct hdmi_audio_infoframe *frame) 6107 { 6108 memset(frame, 0, sizeof(*frame)); 6109 6110 frame->type = HDMI_INFOFRAME_TYPE_AUDIO; 6111 frame->version = 1; 6112 frame->length = HDMI_AUDIO_INFOFRAME_SIZE; 6113 6114 return 0; 6115 } 6116 6117 /** 6118 * hdmi_audio_infoframe_pack() - write HDMI audio infoframe to binary buffer 6119 * @frame: HDMI audio infoframe 6120 * @buffer: destination buffer 6121 * @size: size of buffer 6122 * 6123 * Packs the information contained in the @frame structure into a binary 6124 * representation that can be written into the corresponding controller 6125 * registers. Also computes the checksum as required by section 5.3.5 of 6126 * the HDMI 1.4 specification. 6127 * 6128 * Returns the number of bytes packed into the binary buffer or a negative 6129 * error code on failure. 6130 */ 6131 ssize_t hdmi_audio_infoframe_pack(struct hdmi_audio_infoframe *frame, 6132 void *buffer, size_t size) 6133 { 6134 unsigned char channels; 6135 char *ptr = buffer; 6136 size_t length; 6137 6138 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6139 6140 if (size < length) 6141 return -ENOSPC; 6142 6143 memset(buffer, 0, size); 6144 6145 if (frame->channels >= 2) 6146 channels = frame->channels - 1; 6147 else 6148 channels = 0; 6149 6150 ptr[0] = frame->type; 6151 ptr[1] = frame->version; 6152 ptr[2] = frame->length; 6153 ptr[3] = 0; /* checksum */ 6154 6155 /* start infoframe payload */ 6156 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6157 6158 ptr[0] = ((frame->coding_type & 0xf) << 4) | (channels & 0x7); 6159 ptr[1] = ((frame->sample_frequency & 0x7) << 2) | 6160 (frame->sample_size & 0x3); 6161 ptr[2] = frame->coding_type_ext & 0x1f; 6162 ptr[3] = frame->channel_allocation; 6163 ptr[4] = (frame->level_shift_value & 0xf) << 3; 6164 6165 if (frame->downmix_inhibit) 6166 ptr[4] |= BIT(7); 6167 6168 hdmi_infoframe_set_checksum(buffer, length); 6169 6170 return length; 6171 } 6172 6173 /** 6174 * hdmi_vendor_infoframe_pack() - write a HDMI vendor infoframe to binary buffer 6175 * @frame: HDMI infoframe 6176 * @buffer: destination buffer 6177 * @size: size of buffer 6178 * 6179 * Packs the information contained in the @frame structure into a binary 6180 * representation that can be written into the corresponding controller 6181 * registers. Also computes the checksum as required by section 5.3.5 of 6182 * the HDMI 1.4 specification. 6183 * 6184 * Returns the number of bytes packed into the binary buffer or a negative 6185 * error code on failure. 6186 */ 6187 ssize_t hdmi_vendor_infoframe_pack(struct hdmi_vendor_infoframe *frame, 6188 void *buffer, size_t size) 6189 { 6190 char *ptr = buffer; 6191 size_t length; 6192 6193 /* empty info frame */ 6194 if (frame->vic == 0 && frame->s3d_struct == HDMI_3D_STRUCTURE_INVALID) 6195 return -EINVAL; 6196 6197 /* only one of those can be supplied */ 6198 if (frame->vic != 0 && frame->s3d_struct != HDMI_3D_STRUCTURE_INVALID) 6199 return -EINVAL; 6200 6201 /* for side by side (half) we also need to provide 3D_Ext_Data */ 6202 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6203 frame->length = 6; 6204 else 6205 frame->length = 5; 6206 6207 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6208 6209 if (size < length) 6210 return -ENOSPC; 6211 6212 memset(buffer, 0, size); 6213 6214 ptr[0] = frame->type; 6215 ptr[1] = frame->version; 6216 ptr[2] = frame->length; 6217 ptr[3] = 0; /* checksum */ 6218 6219 /* HDMI OUI */ 6220 ptr[4] = 0x03; 6221 ptr[5] = 0x0c; 6222 ptr[6] = 0x00; 6223 6224 if (frame->vic) { 6225 ptr[7] = 0x1 << 5; /* video format */ 6226 ptr[8] = frame->vic; 6227 } else { 6228 ptr[7] = 0x2 << 5; /* video format */ 6229 ptr[8] = (frame->s3d_struct & 0xf) << 4; 6230 if (frame->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 6231 ptr[9] = (frame->s3d_ext_data & 0xf) << 4; 6232 } 6233 6234 hdmi_infoframe_set_checksum(buffer, length); 6235 6236 return length; 6237 } 6238 6239 /** 6240 * hdmi_drm_infoframe_init() - initialize an HDMI Dynaminc Range and 6241 * mastering infoframe 6242 * @frame: HDMI DRM infoframe 6243 * 6244 * Returns 0 on success or a negative error code on failure. 6245 */ 6246 int hdmi_drm_infoframe_init(struct hdmi_drm_infoframe *frame) 6247 { 6248 memset(frame, 0, sizeof(*frame)); 6249 6250 frame->type = HDMI_INFOFRAME_TYPE_DRM; 6251 frame->version = 1; 6252 6253 return 0; 6254 } 6255 6256 /** 6257 * hdmi_drm_infoframe_pack() - write HDMI DRM infoframe to binary buffer 6258 * @frame: HDMI DRM infoframe 6259 * @buffer: destination buffer 6260 * @size: size of buffer 6261 * 6262 * Packs the information contained in the @frame structure into a binary 6263 * representation that can be written into the corresponding controller 6264 * registers. Also computes the checksum as required by section 5.3.5 of 6265 * the HDMI 1.4 specification. 6266 * 6267 * Returns the number of bytes packed into the binary buffer or a negative 6268 * error code on failure. 6269 */ 6270 ssize_t hdmi_drm_infoframe_pack(struct hdmi_drm_infoframe *frame, void *buffer, 6271 size_t size) 6272 { 6273 u8 *ptr = buffer; 6274 size_t length; 6275 6276 length = HDMI_INFOFRAME_HEADER_SIZE + frame->length; 6277 6278 if (size < length) 6279 return -ENOSPC; 6280 6281 memset(buffer, 0, size); 6282 6283 ptr[0] = frame->type; 6284 ptr[1] = frame->version; 6285 ptr[2] = frame->length; 6286 ptr[3] = 0; /* checksum */ 6287 6288 /* start infoframe payload */ 6289 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6290 6291 ptr[0] = frame->eotf; 6292 ptr[1] = frame->metadata_type; 6293 6294 ptr[2] = frame->display_primaries_x[0] & 0xff; 6295 ptr[3] = frame->display_primaries_x[0] >> 8; 6296 6297 ptr[4] = frame->display_primaries_x[1] & 0xff; 6298 ptr[5] = frame->display_primaries_x[1] >> 8; 6299 6300 ptr[6] = frame->display_primaries_x[2] & 0xff; 6301 ptr[7] = frame->display_primaries_x[2] >> 8; 6302 6303 ptr[9] = frame->display_primaries_y[0] & 0xff; 6304 ptr[10] = frame->display_primaries_y[0] >> 8; 6305 6306 ptr[11] = frame->display_primaries_y[1] & 0xff; 6307 ptr[12] = frame->display_primaries_y[1] >> 8; 6308 6309 ptr[13] = frame->display_primaries_y[2] & 0xff; 6310 ptr[14] = frame->display_primaries_y[2] >> 8; 6311 6312 ptr[15] = frame->white_point_x & 0xff; 6313 ptr[16] = frame->white_point_x >> 8; 6314 6315 ptr[17] = frame->white_point_y & 0xff; 6316 ptr[18] = frame->white_point_y >> 8; 6317 6318 ptr[19] = frame->max_mastering_display_luminance & 0xff; 6319 ptr[20] = frame->max_mastering_display_luminance >> 8; 6320 6321 ptr[21] = frame->min_mastering_display_luminance & 0xff; 6322 ptr[22] = frame->min_mastering_display_luminance >> 8; 6323 6324 ptr[23] = frame->max_cll & 0xff; 6325 ptr[24] = frame->max_cll >> 8; 6326 6327 ptr[25] = frame->max_fall & 0xff; 6328 ptr[26] = frame->max_fall >> 8; 6329 6330 hdmi_infoframe_set_checksum(buffer, length); 6331 6332 return length; 6333 } 6334 6335 /* 6336 * hdmi_vendor_any_infoframe_pack() - write a vendor infoframe to binary buffer 6337 */ 6338 static ssize_t 6339 hdmi_vendor_any_infoframe_pack(union hdmi_vendor_any_infoframe *frame, 6340 void *buffer, size_t size) 6341 { 6342 /* we only know about HDMI vendor infoframes */ 6343 if (frame->any.oui != HDMI_IEEE_OUI) 6344 return -EINVAL; 6345 6346 return hdmi_vendor_infoframe_pack(&frame->hdmi, buffer, size); 6347 } 6348 6349 /** 6350 * hdmi_infoframe_pack() - write a HDMI infoframe to binary buffer 6351 * @frame: HDMI infoframe 6352 * @buffer: destination buffer 6353 * @size: size of buffer 6354 * 6355 * Packs the information contained in the @frame structure into a binary 6356 * representation that can be written into the corresponding controller 6357 * registers. Also computes the checksum as required by section 5.3.5 of 6358 * the HDMI 1.4 specification. 6359 * 6360 * Returns the number of bytes packed into the binary buffer or a negative 6361 * error code on failure. 6362 */ 6363 ssize_t 6364 hdmi_infoframe_pack(union hdmi_infoframe *frame, void *buffer, size_t size) 6365 { 6366 ssize_t length; 6367 6368 switch (frame->any.type) { 6369 case HDMI_INFOFRAME_TYPE_AVI: 6370 length = hdmi_avi_infoframe_pack(&frame->avi, buffer, size); 6371 break; 6372 case HDMI_INFOFRAME_TYPE_DRM: 6373 length = hdmi_drm_infoframe_pack(&frame->drm, buffer, size); 6374 break; 6375 case HDMI_INFOFRAME_TYPE_SPD: 6376 length = hdmi_spd_infoframe_pack(&frame->spd, buffer, size); 6377 break; 6378 case HDMI_INFOFRAME_TYPE_AUDIO: 6379 length = hdmi_audio_infoframe_pack(&frame->audio, buffer, size); 6380 break; 6381 case HDMI_INFOFRAME_TYPE_VENDOR: 6382 length = hdmi_vendor_any_infoframe_pack(&frame->vendor, 6383 buffer, size); 6384 break; 6385 default: 6386 printf("Bad infoframe type %d\n", frame->any.type); 6387 length = -EINVAL; 6388 } 6389 6390 return length; 6391 } 6392 6393 /** 6394 * hdmi_avi_infoframe_unpack() - unpack binary buffer to a HDMI AVI infoframe 6395 * @buffer: source buffer 6396 * @frame: HDMI AVI infoframe 6397 * 6398 * Unpacks the information contained in binary @buffer into a structured 6399 * @frame of the HDMI Auxiliary Video (AVI) information frame. 6400 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6401 * specification. 6402 * 6403 * Returns 0 on success or a negative error code on failure. 6404 */ 6405 static int hdmi_avi_infoframe_unpack(struct hdmi_avi_infoframe *frame, 6406 void *buffer) 6407 { 6408 u8 *ptr = buffer; 6409 int ret; 6410 6411 if (ptr[0] != HDMI_INFOFRAME_TYPE_AVI || 6412 ptr[1] != 2 || 6413 ptr[2] != HDMI_AVI_INFOFRAME_SIZE) 6414 return -EINVAL; 6415 6416 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AVI)) != 0) 6417 return -EINVAL; 6418 6419 ret = hdmi_avi_infoframe_init(frame); 6420 if (ret) 6421 return ret; 6422 6423 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6424 6425 frame->colorspace = (ptr[0] >> 5) & 0x3; 6426 if (ptr[0] & 0x10) 6427 frame->active_aspect = ptr[1] & 0xf; 6428 if (ptr[0] & 0x8) { 6429 frame->top_bar = (ptr[5] << 8) + ptr[6]; 6430 frame->bottom_bar = (ptr[7] << 8) + ptr[8]; 6431 } 6432 if (ptr[0] & 0x4) { 6433 frame->left_bar = (ptr[9] << 8) + ptr[10]; 6434 frame->right_bar = (ptr[11] << 8) + ptr[12]; 6435 } 6436 frame->scan_mode = ptr[0] & 0x3; 6437 6438 frame->colorimetry = (ptr[1] >> 6) & 0x3; 6439 frame->picture_aspect = (ptr[1] >> 4) & 0x3; 6440 frame->active_aspect = ptr[1] & 0xf; 6441 6442 frame->itc = ptr[2] & 0x80 ? true : false; 6443 frame->extended_colorimetry = (ptr[2] >> 4) & 0x7; 6444 frame->quantization_range = (ptr[2] >> 2) & 0x3; 6445 frame->nups = ptr[2] & 0x3; 6446 6447 frame->video_code = ptr[3] & 0x7f; 6448 frame->ycc_quantization_range = (ptr[4] >> 6) & 0x3; 6449 frame->content_type = (ptr[4] >> 4) & 0x3; 6450 6451 frame->pixel_repeat = ptr[4] & 0xf; 6452 6453 return 0; 6454 } 6455 6456 /** 6457 * hdmi_spd_infoframe_unpack() - unpack binary buffer to a HDMI SPD infoframe 6458 * @buffer: source buffer 6459 * @frame: HDMI SPD infoframe 6460 * 6461 * Unpacks the information contained in binary @buffer into a structured 6462 * @frame of the HDMI Source Product Description (SPD) information frame. 6463 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6464 * specification. 6465 * 6466 * Returns 0 on success or a negative error code on failure. 6467 */ 6468 static int hdmi_spd_infoframe_unpack(struct hdmi_spd_infoframe *frame, 6469 void *buffer) 6470 { 6471 char *ptr = buffer; 6472 int ret; 6473 6474 if (ptr[0] != HDMI_INFOFRAME_TYPE_SPD || 6475 ptr[1] != 1 || 6476 ptr[2] != HDMI_SPD_INFOFRAME_SIZE) { 6477 return -EINVAL; 6478 } 6479 6480 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(SPD)) != 0) 6481 return -EINVAL; 6482 6483 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6484 6485 ret = hdmi_spd_infoframe_init(frame, ptr, ptr + 8); 6486 if (ret) 6487 return ret; 6488 6489 frame->sdi = ptr[24]; 6490 6491 return 0; 6492 } 6493 6494 /** 6495 * hdmi_audio_infoframe_unpack() - unpack binary buffer to a HDMI AUDIO infoframe 6496 * @buffer: source buffer 6497 * @frame: HDMI Audio infoframe 6498 * 6499 * Unpacks the information contained in binary @buffer into a structured 6500 * @frame of the HDMI Audio information frame. 6501 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6502 * specification. 6503 * 6504 * Returns 0 on success or a negative error code on failure. 6505 */ 6506 static int hdmi_audio_infoframe_unpack(struct hdmi_audio_infoframe *frame, 6507 void *buffer) 6508 { 6509 u8 *ptr = buffer; 6510 int ret; 6511 6512 if (ptr[0] != HDMI_INFOFRAME_TYPE_AUDIO || 6513 ptr[1] != 1 || 6514 ptr[2] != HDMI_AUDIO_INFOFRAME_SIZE) { 6515 return -EINVAL; 6516 } 6517 6518 if (hdmi_infoframe_checksum(buffer, HDMI_INFOFRAME_SIZE(AUDIO)) != 0) 6519 return -EINVAL; 6520 6521 ret = hdmi_audio_infoframe_init(frame); 6522 if (ret) 6523 return ret; 6524 6525 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6526 6527 frame->channels = ptr[0] & 0x7; 6528 frame->coding_type = (ptr[0] >> 4) & 0xf; 6529 frame->sample_size = ptr[1] & 0x3; 6530 frame->sample_frequency = (ptr[1] >> 2) & 0x7; 6531 frame->coding_type_ext = ptr[2] & 0x1f; 6532 frame->channel_allocation = ptr[3]; 6533 frame->level_shift_value = (ptr[4] >> 3) & 0xf; 6534 frame->downmix_inhibit = ptr[4] & 0x80 ? true : false; 6535 6536 return 0; 6537 } 6538 6539 /** 6540 * hdmi_vendor_infoframe_unpack() - unpack binary buffer to a HDMI vendor infoframe 6541 * @buffer: source buffer 6542 * @frame: HDMI Vendor infoframe 6543 * 6544 * Unpacks the information contained in binary @buffer into a structured 6545 * @frame of the HDMI Vendor information frame. 6546 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6547 * specification. 6548 * 6549 * Returns 0 on success or a negative error code on failure. 6550 */ 6551 static int 6552 hdmi_vendor_any_infoframe_unpack(union hdmi_vendor_any_infoframe *frame, 6553 void *buffer) 6554 { 6555 u8 *ptr = buffer; 6556 size_t length; 6557 int ret; 6558 u8 hdmi_video_format; 6559 struct hdmi_vendor_infoframe *hvf = &frame->hdmi; 6560 6561 if (ptr[0] != HDMI_INFOFRAME_TYPE_VENDOR || 6562 ptr[1] != 1 || 6563 (ptr[2] != 4 && ptr[2] != 5 && ptr[2] != 6)) 6564 return -EINVAL; 6565 6566 length = ptr[2]; 6567 6568 if (hdmi_infoframe_checksum(buffer, 6569 HDMI_INFOFRAME_HEADER_SIZE + length) != 0) 6570 return -EINVAL; 6571 6572 ptr += HDMI_INFOFRAME_HEADER_SIZE; 6573 6574 /* HDMI OUI */ 6575 if (ptr[0] != 0x03 || 6576 ptr[1] != 0x0c || 6577 ptr[2] != 0x00) 6578 return -EINVAL; 6579 6580 hdmi_video_format = ptr[3] >> 5; 6581 6582 if (hdmi_video_format > 0x2) 6583 return -EINVAL; 6584 6585 ret = hdmi_vendor_infoframe_init(hvf); 6586 if (ret) 6587 return ret; 6588 6589 hvf->length = length; 6590 6591 if (hdmi_video_format == 0x2) { 6592 if (length != 5 && length != 6) 6593 return -EINVAL; 6594 hvf->s3d_struct = ptr[4] >> 4; 6595 if (hvf->s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) { 6596 if (length != 6) 6597 return -EINVAL; 6598 hvf->s3d_ext_data = ptr[5] >> 4; 6599 } 6600 } else if (hdmi_video_format == 0x1) { 6601 if (length != 5) 6602 return -EINVAL; 6603 hvf->vic = ptr[4]; 6604 } else { 6605 if (length != 4) 6606 return -EINVAL; 6607 } 6608 6609 return 0; 6610 } 6611 6612 /** 6613 * hdmi_infoframe_unpack() - unpack binary buffer to a HDMI infoframe 6614 * @buffer: source buffer 6615 * @frame: HDMI infoframe 6616 * 6617 * Unpacks the information contained in binary buffer @buffer into a structured 6618 * @frame of a HDMI infoframe. 6619 * Also verifies the checksum as required by section 5.3.5 of the HDMI 1.4 6620 * specification. 6621 * 6622 * Returns 0 on success or a negative error code on failure. 6623 */ 6624 int hdmi_infoframe_unpack(union hdmi_infoframe *frame, void *buffer) 6625 { 6626 int ret; 6627 u8 *ptr = buffer; 6628 6629 switch (ptr[0]) { 6630 case HDMI_INFOFRAME_TYPE_AVI: 6631 ret = hdmi_avi_infoframe_unpack(&frame->avi, buffer); 6632 break; 6633 case HDMI_INFOFRAME_TYPE_SPD: 6634 ret = hdmi_spd_infoframe_unpack(&frame->spd, buffer); 6635 break; 6636 case HDMI_INFOFRAME_TYPE_AUDIO: 6637 ret = hdmi_audio_infoframe_unpack(&frame->audio, buffer); 6638 break; 6639 case HDMI_INFOFRAME_TYPE_VENDOR: 6640 ret = hdmi_vendor_any_infoframe_unpack(&frame->vendor, buffer); 6641 break; 6642 default: 6643 ret = -EINVAL; 6644 break; 6645 } 6646 6647 return ret; 6648 } 6649 6650 /** 6651 * drm_mode_sort - sort mode list 6652 * @edid_data: modes structures to sort 6653 * 6654 * Sort @edid_data by favorability, moving good modes to the head of the list. 6655 */ 6656 void drm_mode_sort(struct hdmi_edid_data *edid_data) 6657 { 6658 struct drm_display_mode *a, *b; 6659 struct drm_display_mode c; 6660 int diff, i, j; 6661 6662 for (i = 0; i < (edid_data->modes - 1); i++) { 6663 a = &edid_data->mode_buf[i]; 6664 for (j = i + 1; j < edid_data->modes; j++) { 6665 b = &edid_data->mode_buf[j]; 6666 diff = ((b->type & DRM_MODE_TYPE_PREFERRED) != 0) - 6667 ((a->type & DRM_MODE_TYPE_PREFERRED) != 0); 6668 if (diff) { 6669 if (diff > 0) { 6670 c = *a; 6671 *a = *b; 6672 *b = c; 6673 } 6674 continue; 6675 } 6676 6677 diff = b->hdisplay * b->vdisplay 6678 - a->hdisplay * a->vdisplay; 6679 if (diff) { 6680 if (diff > 0) { 6681 c = *a; 6682 *a = *b; 6683 *b = c; 6684 } 6685 continue; 6686 } 6687 6688 diff = b->vrefresh - a->vrefresh; 6689 if (diff) { 6690 if (diff > 0) { 6691 c = *a; 6692 *a = *b; 6693 *b = c; 6694 } 6695 continue; 6696 } 6697 6698 diff = b->clock - a->clock; 6699 if (diff > 0) { 6700 c = *a; 6701 *a = *b; 6702 *b = c; 6703 } 6704 } 6705 } 6706 edid_data->preferred_mode = &edid_data->mode_buf[0]; 6707 } 6708 6709 /** 6710 * drm_mode_prune_invalid - remove invalid modes from mode list 6711 * @edid_data: structure store mode list 6712 * Returns: 6713 * Number of valid modes. 6714 */ 6715 int drm_mode_prune_invalid(struct hdmi_edid_data *edid_data) 6716 { 6717 int i, j; 6718 int num = edid_data->modes; 6719 int len = sizeof(struct drm_display_mode); 6720 struct drm_display_mode *mode_buf = edid_data->mode_buf; 6721 6722 for (i = 0; i < num; i++) { 6723 if (mode_buf[i].invalid) { 6724 /* If mode is invalid, delete it. */ 6725 for (j = i; j < num - 1; j++) 6726 memcpy(&mode_buf[j], &mode_buf[j + 1], len); 6727 6728 num--; 6729 i--; 6730 } 6731 } 6732 /* Clear redundant modes of mode_buf. */ 6733 memset(&mode_buf[num], 0, len * (edid_data->modes - num)); 6734 6735 edid_data->modes = num; 6736 return num; 6737 } 6738 6739 /** 6740 * drm_rk_filter_whitelist - mark modes out of white list from mode list 6741 * @edid_data: structure store mode list 6742 */ 6743 void drm_rk_filter_whitelist(struct hdmi_edid_data *edid_data) 6744 { 6745 int i, j, white_len; 6746 6747 if (sizeof(resolution_white)) { 6748 white_len = sizeof(resolution_white) / 6749 sizeof(resolution_white[0]); 6750 for (i = 0; i < edid_data->modes; i++) { 6751 for (j = 0; j < white_len; j++) { 6752 if (drm_mode_match(&resolution_white[j], 6753 &edid_data->mode_buf[i], 6754 DRM_MODE_MATCH_TIMINGS | 6755 DRM_MODE_MATCH_CLOCK | 6756 DRM_MODE_MATCH_FLAGS)) 6757 break; 6758 } 6759 6760 if (j == white_len) 6761 edid_data->mode_buf[i].invalid = true; 6762 } 6763 } 6764 } 6765 6766 static void drm_display_mode_convert(struct drm_display_mode *mode, 6767 struct base_drm_display_mode *base_mode) 6768 { 6769 mode->clock = base_mode->clock; 6770 mode->hdisplay = base_mode->hdisplay; 6771 mode->hsync_start = base_mode->hsync_start; 6772 mode->hsync_end = base_mode->hsync_end; 6773 mode->htotal = base_mode->htotal; 6774 mode->vdisplay = base_mode->vdisplay; 6775 mode->vsync_start = base_mode->vsync_start; 6776 mode->vsync_end = base_mode->vsync_end; 6777 mode->vtotal = base_mode->vtotal; 6778 mode->vrefresh = base_mode->vrefresh; 6779 mode->vscan = base_mode->vscan; 6780 mode->flags = base_mode->flags; 6781 mode->picture_aspect_ratio = base_mode->picture_aspect_ratio; 6782 } 6783 6784 void drm_rk_select_mode(struct hdmi_edid_data *edid_data, 6785 struct base_screen_info *screen_info) 6786 { 6787 int i; 6788 struct drm_display_mode mode; 6789 6790 if (!screen_info) { 6791 /* define init resolution here */ 6792 } else { 6793 memset(&mode, 0, sizeof(struct drm_display_mode)); 6794 6795 drm_display_mode_convert(&mode, &screen_info->mode); 6796 for (i = 0; i < edid_data->modes; i++) { 6797 if (drm_mode_match(&mode, 6798 &edid_data->mode_buf[i], 6799 DRM_MODE_MATCH_TIMINGS | 6800 DRM_MODE_MATCH_CLOCK | 6801 DRM_MODE_MATCH_FLAGS)) { 6802 edid_data->preferred_mode = 6803 &edid_data->mode_buf[i]; 6804 6805 if (edid_data->mode_buf[i].picture_aspect_ratio) 6806 break; 6807 } 6808 } 6809 } 6810 } 6811 6812 /** 6813 * drm_do_probe_ddc_edid() - get EDID information via I2C 6814 * @adap: ddc adapter 6815 * @buf: EDID data buffer to be filled 6816 * @block: 128 byte EDID block to start fetching from 6817 * @len: EDID data buffer length to fetch 6818 * 6819 * Try to fetch EDID information by calling I2C driver functions. 6820 * 6821 * Return: 0 on success or -1 on failure. 6822 */ 6823 static int 6824 drm_do_probe_ddc_edid(struct ddc_adapter *adap, u8 *buf, unsigned int block, 6825 size_t len) 6826 { 6827 unsigned char start = block * HDMI_EDID_BLOCK_SIZE; 6828 unsigned char segment = block >> 1; 6829 unsigned char xfers = segment ? 3 : 2; 6830 int ret, retries = 5; 6831 6832 do { 6833 struct i2c_msg msgs[] = { 6834 { 6835 .addr = DDC_SEGMENT_ADDR, 6836 .flags = 0, 6837 .len = 1, 6838 .buf = &segment, 6839 }, { 6840 .addr = DDC_ADDR, 6841 .flags = 0, 6842 .len = 1, 6843 .buf = &start, 6844 }, { 6845 .addr = DDC_ADDR, 6846 .flags = I2C_M_RD, 6847 .len = len, 6848 .buf = buf, 6849 } 6850 }; 6851 6852 if (adap->ops) { 6853 ret = adap->ops->xfer(adap->i2c_bus, &msgs[3 - xfers], 6854 xfers); 6855 if (!ret) 6856 ret = xfers; 6857 } else { 6858 ret = adap->ddc_xfer(adap, &msgs[3 - xfers], xfers); 6859 } 6860 } while (ret != xfers && --retries); 6861 6862 /* All msg transfer successfully. */ 6863 return ret == xfers ? 0 : -1; 6864 } 6865 6866 int drm_do_get_edid(struct ddc_adapter *adap, u8 *edid) 6867 { 6868 int i, j, block_num, block = 0; 6869 bool edid_corrupt; 6870 #ifdef DEBUG 6871 u8 *buff; 6872 #endif 6873 6874 /* base block fetch */ 6875 for (i = 0; i < 4; i++) { 6876 if (drm_do_probe_ddc_edid(adap, edid, 0, HDMI_EDID_BLOCK_SIZE)) 6877 goto err; 6878 if (drm_edid_block_valid(edid, 0, true, 6879 &edid_corrupt)) 6880 break; 6881 if (i == 0 && drm_edid_is_zero(edid, HDMI_EDID_BLOCK_SIZE)) { 6882 printf("edid base block is 0, get edid failed\n"); 6883 goto err; 6884 } 6885 } 6886 6887 if (i == 4) 6888 goto err; 6889 6890 block++; 6891 /* get the number of extensions */ 6892 block_num = edid[0x7e]; 6893 6894 for (j = 1; j <= block_num; j++) { 6895 for (i = 0; i < 4; i++) { 6896 if (drm_do_probe_ddc_edid(adap, &edid[0x80 * j], j, 6897 HDMI_EDID_BLOCK_SIZE)) 6898 goto err; 6899 if (drm_edid_block_valid(&edid[0x80 * j], j, 6900 true, NULL)) 6901 break; 6902 } 6903 6904 if (i == 4) 6905 goto err; 6906 block++; 6907 } 6908 6909 #ifdef DEBUG 6910 printf("RAW EDID:\n"); 6911 for (i = 0; i < block_num + 1; i++) { 6912 buff = &edid[0x80 * i]; 6913 for (j = 0; j < HDMI_EDID_BLOCK_SIZE; j++) { 6914 if (j % 16 == 0) 6915 printf("\n"); 6916 printf("0x%02x, ", buff[j]); 6917 } 6918 printf("\n"); 6919 } 6920 #endif 6921 6922 return 0; 6923 6924 err: 6925 printf("can't get edid block:%d\n", block); 6926 /* clear all read edid block, include invalid block */ 6927 memset(edid, 0, HDMI_EDID_BLOCK_SIZE * (block + 1)); 6928 return -EFAULT; 6929 } 6930 6931 static ssize_t hdmi_ddc_read(struct ddc_adapter *adap, u16 addr, u8 offset, 6932 void *buffer, size_t size) 6933 { 6934 struct i2c_msg msgs[2] = { 6935 { 6936 .addr = addr, 6937 .flags = 0, 6938 .len = 1, 6939 .buf = &offset, 6940 }, { 6941 .addr = addr, 6942 .flags = I2C_M_RD, 6943 .len = size, 6944 .buf = buffer, 6945 } 6946 }; 6947 6948 return adap->ddc_xfer(adap, msgs, ARRAY_SIZE(msgs)); 6949 } 6950 6951 static ssize_t hdmi_ddc_write(struct ddc_adapter *adap, u16 addr, u8 offset, 6952 const void *buffer, size_t size) 6953 { 6954 struct i2c_msg msg = { 6955 .addr = addr, 6956 .flags = 0, 6957 .len = 1 + size, 6958 .buf = NULL, 6959 }; 6960 void *data; 6961 int err; 6962 6963 data = malloc(1 + size); 6964 if (!data) 6965 return -ENOMEM; 6966 6967 msg.buf = data; 6968 6969 memcpy(data, &offset, sizeof(offset)); 6970 memcpy(data + 1, buffer, size); 6971 6972 err = adap->ddc_xfer(adap, &msg, 1); 6973 6974 free(data); 6975 6976 return err; 6977 } 6978 6979 /** 6980 * drm_scdc_readb - read a single byte from SCDC 6981 * @adap: ddc adapter 6982 * @offset: offset of register to read 6983 * @value: return location for the register value 6984 * 6985 * Reads a single byte from SCDC. This is a convenience wrapper around the 6986 * drm_scdc_read() function. 6987 * 6988 * Returns: 6989 * 0 on success or a negative error code on failure. 6990 */ 6991 u8 drm_scdc_readb(struct ddc_adapter *adap, u8 offset, 6992 u8 *value) 6993 { 6994 return hdmi_ddc_read(adap, SCDC_I2C_SLAVE_ADDRESS, offset, value, 6995 sizeof(*value)); 6996 } 6997 6998 /** 6999 * drm_scdc_writeb - write a single byte to SCDC 7000 * @adap: ddc adapter 7001 * @offset: offset of register to read 7002 * @value: return location for the register value 7003 * 7004 * Writes a single byte to SCDC. This is a convenience wrapper around the 7005 * drm_scdc_write() function. 7006 * 7007 * Returns: 7008 * 0 on success or a negative error code on failure. 7009 */ 7010 u8 drm_scdc_writeb(struct ddc_adapter *adap, u8 offset, 7011 u8 value) 7012 { 7013 return hdmi_ddc_write(adap, SCDC_I2C_SLAVE_ADDRESS, offset, &value, 7014 sizeof(value)); 7015 } 7016 7017