| ec4670a1 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add LPDDR3 timing from stock boot0
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by:
sunxi: add LPDDR3 timing from stock boot0
As we added LPDDR3 support in the former patch, we need a set of timing
info to really enable it.
Add the timing info used by stock boot0.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 72cc9870 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.
Add support for LPDDR3 DRAM in the DesignWare-l
sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM controller
Some A64 boards (SoPine and Pinebook production batch) use LPDDR3 DRAM
chips.
Add support for LPDDR3 DRAM in the DesignWare-like DRAM controller code.
Real LPDDR3 chips' support is not added yet in this commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 7d06e59f | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: enable DRAM initialization and SPL for V3s SoC
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This p
sunxi: enable DRAM initialization and SPL for V3s SoC
As we have already support for the DesignWare DRAM controller and the
integrated DDR2 chip of V3s, let's enable the SPL support for V3s.
This patch also contains the default DRAM configuration for V3s.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 3ec0698b | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add support for V3s DRAM controller
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Rev
sunxi: add support for V3s DRAM controller
Allwinner V3s features a DRAM controller like the on in H3, but with a
DDR2 DRAM.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 67337e68 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add support for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz
sunxi: add support for the DDR2 in V3s SoC
Allwinner V3s SoC features a co-packaged DDR2 DRAM chip, which needs its
timing param.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 176868bc | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: enable dual rank detection in DesignWare-like DRAM code
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second ra
sunxi: enable dual rank detection in DesignWare-like DRAM code
The DesignWare-like DRAM code used to set the controller defaultly to
single rank mode, which makes it not able to detect the second rank.
Set the default value to dual rank, thus the rank detection code can
work and finally the rank setting will be the correct value.
Currently we know little about the dual-rank on R40, and the usage
of A15 address line seems to be breaking dual-rank support. The only R40
board currently available (Sinovoip Banana Pi M2 Ultra) uses A15 rather
than dual-rank, thus we cannot do research for it. So dual rank detection
is temporarily disabled on R40.
This change is tested on a Orange Pi One (H3, single rank), a Pine64+
2GiB version (A64, single rank) , a Pinebook early prototype with DDR3
(A64, dual rank) and a SoPine with some LPDDR3 patch (A64, dual CS pins
on one chip).
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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| f6457ce5 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
sunxi: Add selective DRAM type and timing
DRAM chip varies, and one code cannot satisfy all DRAMs.
Add options to select a timing set.
Currently only DDR3-1333 (the original set) is added into it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 66b12526 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add bank detection code to H3 DRAM initialization code
Some DDR2 DRAM have only four banks, not eight.
Add code to detect this situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Rev
sunxi: add bank detection code to H3 DRAM initialization code
Some DDR2 DRAM have only four banks, not eight.
Add code to detect this situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 87098d70 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng <icenowy@ao
sunxi: add option for 16-bit DW DRAM controller
Some Allwinner SoCs features a DesignWare-like controller with only 16
bit bus width.
Add support for them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| f43a0099 | 03-Jun-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit D
sunxi: Rename bus-width related macros in H3 DRAM code
The DesignWare DRAM controller used by H3 and newer SoCs use a bit to
identify whether the DRAM is half-width.
As H3 itself come with 32-bit DRAM, the two modes of the bit used to be
named "MCTL_CR_32BIT" and "MCTL_CR_16BIT", but for SoCs with 16-bit DRAM
they're really 8-bit and 16-bit.
Rename the bit's macro, and also rename the variable name in
dram_sun8i_h3.c.
This commit do not add 16-bit DRAM controller support, but the support
will be introduced in next commit.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
show more ...
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| 9946631a | 01-May-2017 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: add clock configuration of R40 sata
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1
sunxi: add clock configuration of R40 sata
R40 has a similar SATA controller with the ones on A10/A20, but with a
reset line added (like other peripherals on sun6i+), and two extra VDD
pins added (1.2v and 2.5v).
Add clock configuration of R40 SATA.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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| af83a604 | 28-Apr-2017 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
ARM: sunxi: use imply instead of bare default y in Kconfig
Fix annoying config redefines in SoC/board level Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ma
ARM: sunxi: use imply instead of bare default y in Kconfig
Fix annoying config redefines in SoC/board level Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
show more ...
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| a8f01ccf | 26-Apr-2017 |
Jernej Skrabec <jernej.skrabec@siol.net> |
sunxi: i2c: Add support for DM I2C
This commit adds support for DM I2C on sunxi platform. It can coexist
with old style sunxi I2C driver, because it is still used in SPL and
by some SoCs.
Because s
sunxi: i2c: Add support for DM I2C
This commit adds support for DM I2C on sunxi platform. It can coexist
with old style sunxi I2C driver, because it is still used in SPL and
by some SoCs.
Because sunxi platform doesn't yet support DM clk, reset and pinctrl
driver, workaround is needed to enable clocks and set resets and
pinctrls. This is done by calling i2c_init_board() in board_init().
This means that CONFIG_I2Cx_ENABLE options needs to be correctly set
in order to use needed I2C controller.
Commit is based on the previous patch made by Philipp Tomsich
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
show more ...
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| c199489f | 08-Apr-2017 |
Icenowy Zheng <icenowy@aosc.xyz> |
sunxi: add basic V3s support
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the D
sunxi: add basic V3s support
Basic U-Boot support is now present for V3s.
Some memory addresses are changed specially for V3s, as the original
address map cannot fit into a so small DRAM.
As the DRAM controller code needs a big refactor, the SPL support is
disabled in this version.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
show more ...
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