1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_QEMU_MIPS 16 bool "Support qemu-mips" 17 select SUPPORTS_BIG_ENDIAN 18 select SUPPORTS_LITTLE_ENDIAN 19 select SUPPORTS_CPU_MIPS32_R1 20 select SUPPORTS_CPU_MIPS32_R2 21 select SUPPORTS_CPU_MIPS64_R1 22 select SUPPORTS_CPU_MIPS64_R2 23 select ROM_EXCEPTION_VECTORS 24 25config TARGET_MALTA 26 bool "Support malta" 27 select DM 28 select DM_SERIAL 29 select DYNAMIC_IO_PORT_BASE 30 select MIPS_CM 31 select MIPS_L2_CACHE 32 select OF_CONTROL 33 select OF_ISA_BUS 34 select SUPPORTS_BIG_ENDIAN 35 select SUPPORTS_LITTLE_ENDIAN 36 select SUPPORTS_CPU_MIPS32_R1 37 select SUPPORTS_CPU_MIPS32_R2 38 select SUPPORTS_CPU_MIPS32_R6 39 select SUPPORTS_CPU_MIPS64_R1 40 select SUPPORTS_CPU_MIPS64_R2 41 select SUPPORTS_CPU_MIPS64_R6 42 select SWAP_IO_SPACE 43 select MIPS_L1_CACHE_SHIFT_6 44 select ROM_EXCEPTION_VECTORS 45 46config TARGET_VCT 47 bool "Support vct" 48 select SUPPORTS_BIG_ENDIAN 49 select SUPPORTS_CPU_MIPS32_R1 50 select SUPPORTS_CPU_MIPS32_R2 51 select SYS_MIPS_CACHE_INIT_RAM_LOAD 52 select ROM_EXCEPTION_VECTORS 53 54config TARGET_DBAU1X00 55 bool "Support dbau1x00" 56 select SUPPORTS_BIG_ENDIAN 57 select SUPPORTS_LITTLE_ENDIAN 58 select SUPPORTS_CPU_MIPS32_R1 59 select SUPPORTS_CPU_MIPS32_R2 60 select SYS_MIPS_CACHE_INIT_RAM_LOAD 61 select ROM_EXCEPTION_VECTORS 62 select MIPS_TUNE_4KC 63 64config TARGET_PB1X00 65 bool "Support pb1x00" 66 select SUPPORTS_LITTLE_ENDIAN 67 select SUPPORTS_CPU_MIPS32_R1 68 select SUPPORTS_CPU_MIPS32_R2 69 select SYS_MIPS_CACHE_INIT_RAM_LOAD 70 select ROM_EXCEPTION_VECTORS 71 select MIPS_TUNE_4KC 72 73config ARCH_ATH79 74 bool "Support QCA/Atheros ath79" 75 select OF_CONTROL 76 select DM 77 78config ARCH_BMIPS 79 bool "Support BMIPS SoCs" 80 select OF_CONTROL 81 select DM 82 select CLK 83 select CPU 84 select RAM 85 select SYSRESET 86 imply ENV_IS_NOWHERE 87 88config MACH_PIC32 89 bool "Support Microchip PIC32" 90 select OF_CONTROL 91 select DM 92 93config TARGET_BOSTON 94 bool "Support Boston" 95 select DM 96 select DM_SERIAL 97 select OF_CONTROL 98 select MIPS_CM 99 select MIPS_L1_CACHE_SHIFT_6 100 select MIPS_L2_CACHE 101 select OF_BOARD_SETUP 102 select SUPPORTS_BIG_ENDIAN 103 select SUPPORTS_LITTLE_ENDIAN 104 select SUPPORTS_CPU_MIPS32_R1 105 select SUPPORTS_CPU_MIPS32_R2 106 select SUPPORTS_CPU_MIPS32_R6 107 select SUPPORTS_CPU_MIPS64_R1 108 select SUPPORTS_CPU_MIPS64_R2 109 select SUPPORTS_CPU_MIPS64_R6 110 select ROM_EXCEPTION_VECTORS 111 112config TARGET_XILFPGA 113 bool "Support Imagination Xilfpga" 114 select OF_CONTROL 115 select DM 116 select DM_SERIAL 117 select DM_GPIO 118 select DM_ETH 119 select SUPPORTS_LITTLE_ENDIAN 120 select SUPPORTS_CPU_MIPS32_R1 121 select SUPPORTS_CPU_MIPS32_R2 122 select MIPS_L1_CACHE_SHIFT_4 123 select ROM_EXCEPTION_VECTORS 124 help 125 This supports IMGTEC MIPSfpga platform 126 127endchoice 128 129source "board/dbau1x00/Kconfig" 130source "board/imgtec/boston/Kconfig" 131source "board/imgtec/malta/Kconfig" 132source "board/imgtec/xilfpga/Kconfig" 133source "board/micronas/vct/Kconfig" 134source "board/pb1x00/Kconfig" 135source "board/qemu-mips/Kconfig" 136source "arch/mips/mach-ath79/Kconfig" 137source "arch/mips/mach-bmips/Kconfig" 138source "arch/mips/mach-pic32/Kconfig" 139 140if MIPS 141 142choice 143 prompt "Endianness selection" 144 help 145 Some MIPS boards can be configured for either little or big endian 146 byte order. These modes require different U-Boot images. In general there 147 is one preferred byteorder for a particular system but some systems are 148 just as commonly used in the one or the other endianness. 149 150config SYS_BIG_ENDIAN 151 bool "Big endian" 152 depends on SUPPORTS_BIG_ENDIAN 153 154config SYS_LITTLE_ENDIAN 155 bool "Little endian" 156 depends on SUPPORTS_LITTLE_ENDIAN 157 158endchoice 159 160choice 161 prompt "CPU selection" 162 default CPU_MIPS32_R2 163 164config CPU_MIPS32_R1 165 bool "MIPS32 Release 1" 166 depends on SUPPORTS_CPU_MIPS32_R1 167 select 32BIT 168 help 169 Choose this option to build an U-Boot for release 1 through 5 of the 170 MIPS32 architecture. 171 172config CPU_MIPS32_R2 173 bool "MIPS32 Release 2" 174 depends on SUPPORTS_CPU_MIPS32_R2 175 select 32BIT 176 help 177 Choose this option to build an U-Boot for release 2 through 5 of the 178 MIPS32 architecture. 179 180config CPU_MIPS32_R6 181 bool "MIPS32 Release 6" 182 depends on SUPPORTS_CPU_MIPS32_R6 183 select 32BIT 184 help 185 Choose this option to build an U-Boot for release 6 or later of the 186 MIPS32 architecture. 187 188config CPU_MIPS64_R1 189 bool "MIPS64 Release 1" 190 depends on SUPPORTS_CPU_MIPS64_R1 191 select 64BIT 192 help 193 Choose this option to build a kernel for release 1 through 5 of the 194 MIPS64 architecture. 195 196config CPU_MIPS64_R2 197 bool "MIPS64 Release 2" 198 depends on SUPPORTS_CPU_MIPS64_R2 199 select 64BIT 200 help 201 Choose this option to build a kernel for release 2 through 5 of the 202 MIPS64 architecture. 203 204config CPU_MIPS64_R6 205 bool "MIPS64 Release 6" 206 depends on SUPPORTS_CPU_MIPS64_R6 207 select 64BIT 208 help 209 Choose this option to build a kernel for release 6 or later of the 210 MIPS64 architecture. 211 212endchoice 213 214menu "General setup" 215 216config ROM_EXCEPTION_VECTORS 217 bool "Build U-Boot image with exception vectors" 218 help 219 Enable this to include exception vectors in the U-Boot image. This is 220 required if the U-Boot entry point is equal to the address of the 221 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 222 U-Boot booted from parallel NOR flash). 223 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 224 In that case the image size will be reduced by 0x500 bytes. 225 226config MIPS_CM_BASE 227 hex "MIPS CM GCR Base Address" 228 depends on MIPS_CM 229 default 0x16100000 if TARGET_BOSTON 230 default 0x1fbf8000 231 help 232 The physical base address at which to map the MIPS Coherence Manager 233 Global Configuration Registers (GCRs). This should be set such that 234 the GCRs occupy a region of the physical address space which is 235 otherwise unused, or at minimum that software doesn't need to access. 236 237endmenu 238 239menu "OS boot interface" 240 241config MIPS_BOOT_CMDLINE_LEGACY 242 bool "Hand over legacy command line to Linux kernel" 243 default y 244 help 245 Enable this option if you want U-Boot to hand over the Yamon-style 246 command line to the kernel. All bootargs will be prepared as argc/argv 247 compatible list. The argument count (argc) is stored in register $a0. 248 The address of the argument list (argv) is stored in register $a1. 249 250config MIPS_BOOT_ENV_LEGACY 251 bool "Hand over legacy environment to Linux kernel" 252 default y 253 help 254 Enable this option if you want U-Boot to hand over the Yamon-style 255 environment to the kernel. Information like memory size, initrd 256 address and size will be prepared as zero-terminated key/value list. 257 The address of the environment is stored in register $a2. 258 259config MIPS_BOOT_FDT 260 bool "Hand over a flattened device tree to Linux kernel" 261 default n 262 help 263 Enable this option if you want U-Boot to hand over a flattened 264 device tree to the kernel. According to UHI register $a0 will be set 265 to -2 and the FDT address is stored in $a1. 266 267endmenu 268 269config SUPPORTS_BIG_ENDIAN 270 bool 271 272config SUPPORTS_LITTLE_ENDIAN 273 bool 274 275config SUPPORTS_CPU_MIPS32_R1 276 bool 277 278config SUPPORTS_CPU_MIPS32_R2 279 bool 280 281config SUPPORTS_CPU_MIPS32_R6 282 bool 283 284config SUPPORTS_CPU_MIPS64_R1 285 bool 286 287config SUPPORTS_CPU_MIPS64_R2 288 bool 289 290config SUPPORTS_CPU_MIPS64_R6 291 bool 292 293config CPU_MIPS32 294 bool 295 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 296 297config CPU_MIPS64 298 bool 299 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 300 301config MIPS_TUNE_4KC 302 bool 303 304config MIPS_TUNE_14KC 305 bool 306 307config MIPS_TUNE_24KC 308 bool 309 310config MIPS_TUNE_34KC 311 bool 312 313config MIPS_TUNE_74KC 314 bool 315 316config 32BIT 317 bool 318 319config 64BIT 320 bool 321 322config SWAP_IO_SPACE 323 bool 324 325config SYS_MIPS_CACHE_INIT_RAM_LOAD 326 bool 327 328config MIPS_INIT_STACK_IN_SRAM 329 bool 330 default n 331 help 332 Select this if the initial stack frame could be setup in SRAM. 333 Normally the initial stack frame is set up in DRAM which is often 334 only available after lowlevel_init. With this option the initial 335 stack frame and the early C environment is set up before 336 lowlevel_init. Thus lowlevel_init does not need to be implemented 337 in assembler. 338 339config SYS_DCACHE_SIZE 340 int 341 default 0 342 help 343 The total size of the L1 Dcache, if known at compile time. 344 345config SYS_DCACHE_LINE_SIZE 346 int 347 default 0 348 help 349 The size of L1 Dcache lines, if known at compile time. 350 351config SYS_ICACHE_SIZE 352 int 353 default 0 354 help 355 The total size of the L1 ICache, if known at compile time. 356 357config SYS_ICACHE_LINE_SIZE 358 int 359 default 0 360 help 361 The size of L1 Icache lines, if known at compile time. 362 363config SYS_CACHE_SIZE_AUTO 364 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 365 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 366 help 367 Select this (or let it be auto-selected by not defining any cache 368 sizes) in order to allow U-Boot to automatically detect the sizes 369 of caches at runtime. This has a small cost in code size & runtime 370 so if you know the cache configuration for your system at compile 371 time it would be beneficial to configure it. 372 373config MIPS_L1_CACHE_SHIFT_4 374 bool 375 376config MIPS_L1_CACHE_SHIFT_5 377 bool 378 379config MIPS_L1_CACHE_SHIFT_6 380 bool 381 382config MIPS_L1_CACHE_SHIFT_7 383 bool 384 385config MIPS_L1_CACHE_SHIFT 386 int 387 default "7" if MIPS_L1_CACHE_SHIFT_7 388 default "6" if MIPS_L1_CACHE_SHIFT_6 389 default "5" if MIPS_L1_CACHE_SHIFT_5 390 default "4" if MIPS_L1_CACHE_SHIFT_4 391 default "5" 392 393config MIPS_L2_CACHE 394 bool 395 help 396 Select this if your system includes an L2 cache and you want U-Boot 397 to initialise & maintain it. 398 399config DYNAMIC_IO_PORT_BASE 400 bool 401 402config MIPS_CM 403 bool 404 help 405 Select this if your system contains a MIPS Coherence Manager and you 406 wish U-Boot to configure it or make use of it to retrieve system 407 information such as cache configuration. 408 409endif 410 411endmenu 412