1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T1024/T1023 RDB board configuration file 9 */ 10 11 #ifndef __T1024RDB_H 12 #define __T1024RDB_H 13 14 /* High Level Configuration Options */ 15 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 16 #define CONFIG_MP /* support multiple processors */ 17 #define CONFIG_ENABLE_36BIT_PHYS 18 19 #ifdef CONFIG_PHYS_64BIT 20 #define CONFIG_ADDR_MAP 1 21 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 22 #endif 23 24 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 25 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 26 27 #define CONFIG_ENV_OVERWRITE 28 29 /* support deep sleep */ 30 #ifdef CONFIG_ARCH_T1024 31 #define CONFIG_DEEP_SLEEP 32 #endif 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg 36 #define CONFIG_SPL_FLUSH_IMAGE 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SYS_TEXT_BASE 0x30001000 39 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 40 #define CONFIG_SPL_PAD_TO 0x40000 41 #define CONFIG_SPL_MAX_SIZE 0x28000 42 #define RESET_VECTOR_OFFSET 0x27FFC 43 #define BOOT_PAGE_OFFSET 0x27000 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #endif 49 50 #ifdef CONFIG_NAND 51 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 52 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 53 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 54 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 55 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 56 #if defined(CONFIG_TARGET_T1024RDB) 57 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg 58 #elif defined(CONFIG_TARGET_T1023RDB) 59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg 60 #endif 61 #define CONFIG_SPL_NAND_BOOT 62 #endif 63 64 #ifdef CONFIG_SPIFLASH 65 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 66 #define CONFIG_SPL_SPI_FLASH_MINIMAL 67 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 68 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 69 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 70 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 71 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 72 #ifndef CONFIG_SPL_BUILD 73 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 74 #endif 75 #if defined(CONFIG_TARGET_T1024RDB) 76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg 77 #elif defined(CONFIG_TARGET_T1023RDB) 78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg 79 #endif 80 #define CONFIG_SPL_SPI_BOOT 81 #endif 82 83 #ifdef CONFIG_SDCARD 84 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 85 #define CONFIG_SPL_MMC_MINIMAL 86 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 87 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 88 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 89 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 90 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 91 #ifndef CONFIG_SPL_BUILD 92 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 93 #endif 94 #if defined(CONFIG_TARGET_T1024RDB) 95 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg 96 #elif defined(CONFIG_TARGET_T1023RDB) 97 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg 98 #endif 99 #define CONFIG_SPL_MMC_BOOT 100 #endif 101 102 #endif /* CONFIG_RAMBOOT_PBL */ 103 104 #ifndef CONFIG_SYS_TEXT_BASE 105 #define CONFIG_SYS_TEXT_BASE 0xeff40000 106 #endif 107 108 #ifndef CONFIG_RESET_VECTOR_ADDRESS 109 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 110 #endif 111 112 #ifdef CONFIG_MTD_NOR_FLASH 113 #define CONFIG_FLASH_CFI_DRIVER 114 #define CONFIG_SYS_FLASH_CFI 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 116 #endif 117 118 /* PCIe Boot - Master */ 119 #define CONFIG_SRIO_PCIE_BOOT_MASTER 120 /* 121 * for slave u-boot IMAGE instored in master memory space, 122 * PHYS must be aligned based on the SIZE 123 */ 124 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 125 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 126 #ifdef CONFIG_PHYS_64BIT 127 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 128 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 129 #else 130 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 131 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 132 #endif 133 /* 134 * for slave UCODE and ENV instored in master memory space, 135 * PHYS must be aligned based on the SIZE 136 */ 137 #ifdef CONFIG_PHYS_64BIT 138 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 139 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 140 #else 141 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 142 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 143 #endif 144 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 145 /* slave core release by master*/ 146 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 147 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 148 149 /* PCIe Boot - Slave */ 150 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 151 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 152 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 153 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 154 /* Set 1M boot space for PCIe boot */ 155 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 156 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 157 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 158 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 159 #endif 160 161 #if defined(CONFIG_SPIFLASH) 162 #define CONFIG_SYS_EXTRA_ENV_RELOC 163 #define CONFIG_ENV_IS_IN_SPI_FLASH 164 #define CONFIG_ENV_SPI_BUS 0 165 #define CONFIG_ENV_SPI_CS 0 166 #define CONFIG_ENV_SPI_MAX_HZ 10000000 167 #define CONFIG_ENV_SPI_MODE 0 168 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 169 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 170 #if defined(CONFIG_TARGET_T1024RDB) 171 #define CONFIG_ENV_SECT_SIZE 0x10000 172 #elif defined(CONFIG_TARGET_T1023RDB) 173 #define CONFIG_ENV_SECT_SIZE 0x40000 174 #endif 175 #elif defined(CONFIG_SDCARD) 176 #define CONFIG_SYS_EXTRA_ENV_RELOC 177 #define CONFIG_SYS_MMC_ENV_DEV 0 178 #define CONFIG_ENV_SIZE 0x2000 179 #define CONFIG_ENV_OFFSET (512 * 0x800) 180 #elif defined(CONFIG_NAND) 181 #define CONFIG_SYS_EXTRA_ENV_RELOC 182 #define CONFIG_ENV_SIZE 0x2000 183 #if defined(CONFIG_TARGET_T1024RDB) 184 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) 185 #elif defined(CONFIG_TARGET_T1023RDB) 186 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 187 #endif 188 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 189 #define CONFIG_ENV_IS_IN_REMOTE 190 #define CONFIG_ENV_ADDR 0xffe20000 191 #define CONFIG_ENV_SIZE 0x2000 192 #elif defined(CONFIG_ENV_IS_NOWHERE) 193 #define CONFIG_ENV_SIZE 0x2000 194 #else 195 #define CONFIG_ENV_IS_IN_FLASH 196 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 197 #define CONFIG_ENV_SIZE 0x2000 198 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 199 #endif 200 201 #ifndef __ASSEMBLY__ 202 unsigned long get_board_sys_clk(void); 203 unsigned long get_board_ddr_clk(void); 204 #endif 205 206 #define CONFIG_SYS_CLK_FREQ 100000000 207 #define CONFIG_DDR_CLK_FREQ 100000000 208 209 /* 210 * These can be toggled for performance analysis, otherwise use default. 211 */ 212 #define CONFIG_SYS_CACHE_STASHING 213 #define CONFIG_BACKSIDE_L2_CACHE 214 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 215 #define CONFIG_BTB /* toggle branch predition */ 216 #define CONFIG_DDR_ECC 217 #ifdef CONFIG_DDR_ECC 218 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 219 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 220 #endif 221 222 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 223 #define CONFIG_SYS_MEMTEST_END 0x00400000 224 #define CONFIG_SYS_ALT_MEMTEST 225 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 226 227 /* 228 * Config the L3 Cache as L3 SRAM 229 */ 230 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 231 #define CONFIG_SYS_L3_SIZE (256 << 10) 232 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 233 #ifdef CONFIG_RAMBOOT_PBL 234 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 235 #endif 236 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 237 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 238 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 239 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 240 241 #ifdef CONFIG_PHYS_64BIT 242 #define CONFIG_SYS_DCSRBAR 0xf0000000 243 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 244 #endif 245 246 /* EEPROM */ 247 #define CONFIG_ID_EEPROM 248 #define CONFIG_SYS_I2C_EEPROM_NXID 249 #define CONFIG_SYS_EEPROM_BUS_NUM 0 250 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 251 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 252 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 253 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 254 255 /* 256 * DDR Setup 257 */ 258 #define CONFIG_VERY_BIG_RAM 259 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 260 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 261 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 262 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 263 #define CONFIG_FSL_DDR_INTERACTIVE 264 #if defined(CONFIG_TARGET_T1024RDB) 265 #define CONFIG_DDR_SPD 266 #define CONFIG_SYS_SPD_BUS_NUM 0 267 #define SPD_EEPROM_ADDRESS 0x51 268 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 269 #elif defined(CONFIG_TARGET_T1023RDB) 270 #define CONFIG_SYS_DDR_RAW_TIMING 271 #define CONFIG_SYS_SDRAM_SIZE 2048 272 #endif 273 274 /* 275 * IFC Definitions 276 */ 277 #define CONFIG_SYS_FLASH_BASE 0xe8000000 278 #ifdef CONFIG_PHYS_64BIT 279 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 280 #else 281 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 282 #endif 283 284 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 285 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 286 CSPR_PORT_SIZE_16 | \ 287 CSPR_MSEL_NOR | \ 288 CSPR_V) 289 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 290 291 /* NOR Flash Timing Params */ 292 #if defined(CONFIG_TARGET_T1024RDB) 293 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 294 #elif defined(CONFIG_TARGET_T1023RDB) 295 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ 296 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) 297 #endif 298 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 299 FTIM0_NOR_TEADC(0x5) | \ 300 FTIM0_NOR_TEAHC(0x5)) 301 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 302 FTIM1_NOR_TRAD_NOR(0x1A) |\ 303 FTIM1_NOR_TSEQRAD_NOR(0x13)) 304 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 305 FTIM2_NOR_TCH(0x4) | \ 306 FTIM2_NOR_TWPH(0x0E) | \ 307 FTIM2_NOR_TWP(0x1c)) 308 #define CONFIG_SYS_NOR_FTIM3 0x0 309 310 #define CONFIG_SYS_FLASH_QUIET_TEST 311 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 312 313 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 314 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 315 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 316 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 317 318 #define CONFIG_SYS_FLASH_EMPTY_INFO 319 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 320 321 #ifdef CONFIG_TARGET_T1024RDB 322 /* CPLD on IFC */ 323 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 324 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 325 #define CONFIG_SYS_CSPR2_EXT (0xf) 326 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ 327 | CSPR_PORT_SIZE_8 \ 328 | CSPR_MSEL_GPCM \ 329 | CSPR_V) 330 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 331 #define CONFIG_SYS_CSOR2 0x0 332 333 /* CPLD Timing parameters for IFC CS2 */ 334 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 335 FTIM0_GPCM_TEADC(0x0e) | \ 336 FTIM0_GPCM_TEAHC(0x0e)) 337 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 338 FTIM1_GPCM_TRAD(0x1f)) 339 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 340 FTIM2_GPCM_TCH(0x8) | \ 341 FTIM2_GPCM_TWP(0x1f)) 342 #define CONFIG_SYS_CS2_FTIM3 0x0 343 #endif 344 345 /* NAND Flash on IFC */ 346 #define CONFIG_NAND_FSL_IFC 347 #define CONFIG_SYS_NAND_BASE 0xff800000 348 #ifdef CONFIG_PHYS_64BIT 349 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 350 #else 351 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 352 #endif 353 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 354 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 355 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 356 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 357 | CSPR_V) 358 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 359 360 #if defined(CONFIG_TARGET_T1024RDB) 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 365 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 366 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 367 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 368 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 369 #elif defined(CONFIG_TARGET_T1023RDB) 370 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 371 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 372 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 373 | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ 374 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 375 | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ 376 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 377 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 378 #endif 379 380 #define CONFIG_SYS_NAND_ONFI_DETECTION 381 /* ONFI NAND Flash mode0 Timing Params */ 382 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 383 FTIM0_NAND_TWP(0x18) | \ 384 FTIM0_NAND_TWCHT(0x07) | \ 385 FTIM0_NAND_TWH(0x0a)) 386 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 387 FTIM1_NAND_TWBE(0x39) | \ 388 FTIM1_NAND_TRR(0x0e) | \ 389 FTIM1_NAND_TRP(0x18)) 390 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 391 FTIM2_NAND_TREH(0x0a) | \ 392 FTIM2_NAND_TWHRE(0x1e)) 393 #define CONFIG_SYS_NAND_FTIM3 0x0 394 395 #define CONFIG_SYS_NAND_DDR_LAW 11 396 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 397 #define CONFIG_SYS_MAX_NAND_DEVICE 1 398 #define CONFIG_CMD_NAND 399 400 #if defined(CONFIG_NAND) 401 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 402 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 403 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 404 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 405 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 406 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 407 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 408 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 409 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 410 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 411 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 412 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 413 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 414 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 415 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 416 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 417 #else 418 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 419 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 420 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 421 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 422 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 423 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 424 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 425 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 426 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 427 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 428 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 429 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 430 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 431 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 432 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 433 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 434 #endif 435 436 #ifdef CONFIG_SPL_BUILD 437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 438 #else 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 440 #endif 441 442 #if defined(CONFIG_RAMBOOT_PBL) 443 #define CONFIG_SYS_RAMBOOT 444 #endif 445 446 #define CONFIG_BOARD_EARLY_INIT_R 447 #define CONFIG_MISC_INIT_R 448 449 #define CONFIG_HWCONFIG 450 451 /* define to use L1 as initial stack */ 452 #define CONFIG_L1_INIT_RAM 453 #define CONFIG_SYS_INIT_RAM_LOCK 454 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 458 /* The assembler doesn't like typecast */ 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 460 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 461 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 462 #else 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 466 #endif 467 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 468 469 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 470 GENERATED_GBL_DATA_SIZE) 471 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 472 473 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 474 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 475 476 /* Serial Port */ 477 #define CONFIG_CONS_INDEX 1 478 #define CONFIG_SYS_NS16550_SERIAL 479 #define CONFIG_SYS_NS16550_REG_SIZE 1 480 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 481 482 #define CONFIG_SYS_BAUDRATE_TABLE \ 483 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 484 485 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 486 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 487 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 488 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 489 490 /* Video */ 491 #undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ 492 #ifdef CONFIG_FSL_DIU_FB 493 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 494 #define CONFIG_VIDEO_LOGO 495 #define CONFIG_VIDEO_BMP_LOGO 496 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 497 /* 498 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 499 * disable empty flash sector detection, which is I/O-intensive. 500 */ 501 #undef CONFIG_SYS_FLASH_EMPTY_INFO 502 #endif 503 504 /* I2C */ 505 #define CONFIG_SYS_I2C 506 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 507 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 508 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 509 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 510 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 511 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 512 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 513 514 #define I2C_PCA6408_BUS_NUM 1 515 #define I2C_PCA6408_ADDR 0x20 516 517 /* I2C bus multiplexer */ 518 #define I2C_MUX_CH_DEFAULT 0x8 519 520 /* 521 * RTC configuration 522 */ 523 #define RTC 524 #define CONFIG_RTC_DS1337 1 525 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 526 527 /* 528 * eSPI - Enhanced SPI 529 */ 530 #define CONFIG_SPI_FLASH_BAR 531 #define CONFIG_SF_DEFAULT_SPEED 10000000 532 #define CONFIG_SF_DEFAULT_MODE 0 533 534 /* 535 * General PCIe 536 * Memory space is mapped 1-1, but I/O space must start from 0. 537 */ 538 #define CONFIG_PCIE1 /* PCIE controller 1 */ 539 #define CONFIG_PCIE2 /* PCIE controller 2 */ 540 #define CONFIG_PCIE3 /* PCIE controller 3 */ 541 #ifdef CONFIG_ARCH_T1040 542 #define CONFIG_PCIE4 /* PCIE controller 4 */ 543 #endif 544 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 545 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 546 #define CONFIG_PCI_INDIRECT_BRIDGE 547 548 #ifdef CONFIG_PCI 549 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 550 #ifdef CONFIG_PCIE1 551 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 552 #ifdef CONFIG_PHYS_64BIT 553 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 554 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 555 #else 556 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 557 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 558 #endif 559 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 560 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 561 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 562 #ifdef CONFIG_PHYS_64BIT 563 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 564 #else 565 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 566 #endif 567 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 568 #endif 569 570 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 571 #ifdef CONFIG_PCIE2 572 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 573 #ifdef CONFIG_PHYS_64BIT 574 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 575 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 576 #else 577 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 578 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 579 #endif 580 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 581 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 582 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 583 #ifdef CONFIG_PHYS_64BIT 584 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 585 #else 586 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 587 #endif 588 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 589 #endif 590 591 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 592 #ifdef CONFIG_PCIE3 593 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 594 #ifdef CONFIG_PHYS_64BIT 595 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 596 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 597 #else 598 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 599 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 600 #endif 601 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 602 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 603 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 604 #ifdef CONFIG_PHYS_64BIT 605 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 606 #else 607 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 608 #endif 609 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 610 #endif 611 612 /* controller 4, Base address 203000, to be removed */ 613 #ifdef CONFIG_PCIE4 614 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 615 #ifdef CONFIG_PHYS_64BIT 616 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 617 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 618 #else 619 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 620 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 621 #endif 622 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 623 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 624 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 625 #ifdef CONFIG_PHYS_64BIT 626 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 627 #else 628 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 629 #endif 630 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 631 #endif 632 633 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 634 #endif /* CONFIG_PCI */ 635 636 /* 637 * USB 638 */ 639 #define CONFIG_HAS_FSL_DR_USB 640 641 #ifdef CONFIG_HAS_FSL_DR_USB 642 #define CONFIG_USB_EHCI_FSL 643 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 644 #endif 645 646 /* 647 * SDHC 648 */ 649 #ifdef CONFIG_MMC 650 #define CONFIG_FSL_ESDHC 651 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 652 #endif 653 654 /* Qman/Bman */ 655 #ifndef CONFIG_NOBQFMAN 656 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 657 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 658 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 659 #ifdef CONFIG_PHYS_64BIT 660 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 661 #else 662 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 663 #endif 664 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 665 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 666 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 667 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 668 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 669 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 670 CONFIG_SYS_BMAN_CENA_SIZE) 671 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 672 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 673 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 674 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 675 #ifdef CONFIG_PHYS_64BIT 676 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 677 #else 678 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 679 #endif 680 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 681 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 682 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 683 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 684 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 685 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 686 CONFIG_SYS_QMAN_CENA_SIZE) 687 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 688 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 689 690 #define CONFIG_SYS_DPAA_FMAN 691 692 #ifdef CONFIG_TARGET_T1024RDB 693 #define CONFIG_QE 694 #define CONFIG_U_QE 695 #endif 696 /* Default address of microcode for the Linux FMan driver */ 697 #if defined(CONFIG_SPIFLASH) 698 /* 699 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 700 * env, so we got 0x110000. 701 */ 702 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 703 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 704 #define CONFIG_SYS_QE_FW_ADDR 0x130000 705 #elif defined(CONFIG_SDCARD) 706 /* 707 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 708 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 709 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). 710 */ 711 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 712 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 713 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 714 #elif defined(CONFIG_NAND) 715 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 716 #if defined(CONFIG_TARGET_T1024RDB) 717 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 718 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 719 #elif defined(CONFIG_TARGET_T1023RDB) 720 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 721 #define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) 722 #endif 723 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 724 /* 725 * Slave has no ucode locally, it can fetch this from remote. When implementing 726 * in two corenet boards, slave's ucode could be stored in master's memory 727 * space, the address can be mapped from slave TLB->slave LAW-> 728 * slave SRIO or PCIE outbound window->master inbound window-> 729 * master LAW->the ucode address in master's memory space. 730 */ 731 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 732 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 733 #else 734 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 735 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 736 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 737 #endif 738 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 739 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 740 #endif /* CONFIG_NOBQFMAN */ 741 742 #ifdef CONFIG_SYS_DPAA_FMAN 743 #define CONFIG_FMAN_ENET 744 #define CONFIG_PHYLIB_10G 745 #define CONFIG_PHY_REALTEK 746 #define CONFIG_PHY_AQUANTIA 747 #if defined(CONFIG_TARGET_T1024RDB) 748 #define RGMII_PHY1_ADDR 0x2 749 #define RGMII_PHY2_ADDR 0x6 750 #define SGMII_AQR_PHY_ADDR 0x2 751 #define FM1_10GEC1_PHY_ADDR 0x1 752 #elif defined(CONFIG_TARGET_T1023RDB) 753 #define RGMII_PHY1_ADDR 0x1 754 #define SGMII_RTK_PHY_ADDR 0x3 755 #define SGMII_AQR_PHY_ADDR 0x2 756 #endif 757 #endif 758 759 #ifdef CONFIG_FMAN_ENET 760 #define CONFIG_MII /* MII PHY management */ 761 #define CONFIG_ETHPRIME "FM1@DTSEC4" 762 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 763 #endif 764 765 /* 766 * Dynamic MTD Partition support with mtdparts 767 */ 768 #ifdef CONFIG_MTD_NOR_FLASH 769 #define CONFIG_MTD_DEVICE 770 #define CONFIG_MTD_PARTITIONS 771 #define CONFIG_FLASH_CFI_MTD 772 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 773 "spi0=spife110000.1" 774 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 775 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 776 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 777 "1m(uboot),5m(kernel),128k(dtb),-(user)" 778 #endif 779 780 /* 781 * Environment 782 */ 783 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 784 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 785 786 /* 787 * Command line configuration. 788 */ 789 #define CONFIG_CMD_REGINFO 790 791 #ifdef CONFIG_PCI 792 #define CONFIG_CMD_PCI 793 #endif 794 795 /* 796 * Miscellaneous configurable options 797 */ 798 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 799 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 800 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 801 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 802 #ifdef CONFIG_CMD_KGDB 803 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 804 #else 805 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 806 #endif 807 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 808 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 809 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 810 811 /* 812 * For booting Linux, the board info and command line data 813 * have to be in the first 64 MB of memory, since this is 814 * the maximum mapped by the Linux kernel during initialization. 815 */ 816 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 817 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 818 819 #ifdef CONFIG_CMD_KGDB 820 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 821 #endif 822 823 /* 824 * Environment Configuration 825 */ 826 #define CONFIG_ROOTPATH "/opt/nfsroot" 827 #define CONFIG_BOOTFILE "uImage" 828 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 829 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ 830 #define __USB_PHY_TYPE utmi 831 832 #ifdef CONFIG_ARCH_T1024 833 #define CONFIG_BOARDNAME t1024rdb 834 #define BANK_INTLV cs0_cs1 835 #else 836 #define CONFIG_BOARDNAME t1023rdb 837 #define BANK_INTLV null 838 #endif 839 840 #define CONFIG_EXTRA_ENV_SETTINGS \ 841 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 842 "bank_intlv=" __stringify(BANK_INTLV) "\0" \ 843 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ 844 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ 845 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ 846 __stringify(CONFIG_BOARDNAME) ".dtb\0" \ 847 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 848 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 849 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ 850 "netdev=eth0\0" \ 851 "tftpflash=tftpboot $loadaddr $uboot && " \ 852 "protect off $ubootaddr +$filesize && " \ 853 "erase $ubootaddr +$filesize && " \ 854 "cp.b $loadaddr $ubootaddr $filesize && " \ 855 "protect on $ubootaddr +$filesize && " \ 856 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 857 "consoledev=ttyS0\0" \ 858 "ramdiskaddr=2000000\0" \ 859 "fdtaddr=1e00000\0" \ 860 "bdev=sda3\0" 861 862 #define CONFIG_LINUX \ 863 "setenv bootargs root=/dev/ram rw " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "setenv ramdiskaddr 0x02000000;" \ 866 "setenv fdtaddr 0x00c00000;" \ 867 "setenv loadaddr 0x1000000;" \ 868 "bootm $loadaddr $ramdiskaddr $fdtaddr" 869 870 #define CONFIG_NFSBOOTCOMMAND \ 871 "setenv bootargs root=/dev/nfs rw " \ 872 "nfsroot=$serverip:$rootpath " \ 873 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 874 "console=$consoledev,$baudrate $othbootargs;" \ 875 "tftp $loadaddr $bootfile;" \ 876 "tftp $fdtaddr $fdtfile;" \ 877 "bootm $loadaddr - $fdtaddr" 878 879 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 880 881 #include <asm/fsl_secure_boot.h> 882 883 #endif /* __T1024RDB_H */ 884