1 /* 2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T2080/T2081 QDS board configuration file 9 */ 10 11 #ifndef __T208xQDS_H 12 #define __T208xQDS_H 13 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 15 #if defined(CONFIG_ARCH_T2080) 16 #define CONFIG_FSL_SATA_V2 17 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 18 #define CONFIG_SRIO1 /* SRIO port 1 */ 19 #define CONFIG_SRIO2 /* SRIO port 2 */ 20 #elif defined(CONFIG_ARCH_T2081) 21 #endif 22 23 /* High Level Configuration Options */ 24 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 25 #define CONFIG_MP /* support multiple processors */ 26 #define CONFIG_ENABLE_36BIT_PHYS 27 28 #ifdef CONFIG_PHYS_64BIT 29 #define CONFIG_ADDR_MAP 1 30 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 31 #endif 32 33 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 34 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 35 #define CONFIG_ENV_OVERWRITE 36 37 #ifdef CONFIG_RAMBOOT_PBL 38 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg 39 40 #define CONFIG_SPL_FLUSH_IMAGE 41 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 42 #define CONFIG_SYS_TEXT_BASE 0x00201000 43 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 44 #define CONFIG_SPL_PAD_TO 0x40000 45 #define CONFIG_SPL_MAX_SIZE 0x28000 46 #define RESET_VECTOR_OFFSET 0x27FFC 47 #define BOOT_PAGE_OFFSET 0x27000 48 #ifdef CONFIG_SPL_BUILD 49 #define CONFIG_SPL_SKIP_RELOCATE 50 #define CONFIG_SPL_COMMON_INIT_DDR 51 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 52 #endif 53 54 #ifdef CONFIG_NAND 55 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 56 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 58 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #if defined(CONFIG_ARCH_T2080) 61 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg 62 #elif defined(CONFIG_ARCH_T2081) 63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg 64 #endif 65 #define CONFIG_SPL_NAND_BOOT 66 #endif 67 68 #ifdef CONFIG_SPIFLASH 69 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 70 #define CONFIG_SPL_SPI_FLASH_MINIMAL 71 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 72 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) 73 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) 74 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 75 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 76 #ifndef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 78 #endif 79 #if defined(CONFIG_ARCH_T2080) 80 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg 81 #elif defined(CONFIG_ARCH_T2081) 82 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg 83 #endif 84 #define CONFIG_SPL_SPI_BOOT 85 #endif 86 87 #ifdef CONFIG_SDCARD 88 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 89 #define CONFIG_SPL_MMC_MINIMAL 90 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 91 #define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) 92 #define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) 93 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 94 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 95 #ifndef CONFIG_SPL_BUILD 96 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 97 #endif 98 #if defined(CONFIG_ARCH_T2080) 99 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg 100 #elif defined(CONFIG_ARCH_T2081) 101 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg 102 #endif 103 #define CONFIG_SPL_MMC_BOOT 104 #endif 105 106 #endif /* CONFIG_RAMBOOT_PBL */ 107 108 #define CONFIG_SRIO_PCIE_BOOT_MASTER 109 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 110 /* Set 1M boot space */ 111 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 112 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 113 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 114 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 115 #endif 116 117 #ifndef CONFIG_SYS_TEXT_BASE 118 #define CONFIG_SYS_TEXT_BASE 0xeff40000 119 #endif 120 121 #ifndef CONFIG_RESET_VECTOR_ADDRESS 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 123 #endif 124 125 /* 126 * These can be toggled for performance analysis, otherwise use default. 127 */ 128 #define CONFIG_SYS_CACHE_STASHING 129 #define CONFIG_BTB /* toggle branch predition */ 130 #define CONFIG_DDR_ECC 131 #ifdef CONFIG_DDR_ECC 132 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 133 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 134 #endif 135 136 #ifdef CONFIG_MTD_NOR_FLASH 137 #define CONFIG_FLASH_CFI_DRIVER 138 #define CONFIG_SYS_FLASH_CFI 139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 140 #endif 141 142 #if defined(CONFIG_SPIFLASH) 143 #define CONFIG_SYS_EXTRA_ENV_RELOC 144 #define CONFIG_ENV_IS_IN_SPI_FLASH 145 #define CONFIG_ENV_SPI_BUS 0 146 #define CONFIG_ENV_SPI_CS 0 147 #define CONFIG_ENV_SPI_MAX_HZ 10000000 148 #define CONFIG_ENV_SPI_MODE 0 149 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 150 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 151 #define CONFIG_ENV_SECT_SIZE 0x10000 152 #elif defined(CONFIG_SDCARD) 153 #define CONFIG_SYS_EXTRA_ENV_RELOC 154 #define CONFIG_SYS_MMC_ENV_DEV 0 155 #define CONFIG_ENV_SIZE 0x2000 156 #define CONFIG_ENV_OFFSET (512 * 0x800) 157 #elif defined(CONFIG_NAND) 158 #define CONFIG_SYS_EXTRA_ENV_RELOC 159 #define CONFIG_ENV_SIZE 0x2000 160 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 161 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 162 #define CONFIG_ENV_IS_IN_REMOTE 163 #define CONFIG_ENV_ADDR 0xffe20000 164 #define CONFIG_ENV_SIZE 0x2000 165 #elif defined(CONFIG_ENV_IS_NOWHERE) 166 #define CONFIG_ENV_SIZE 0x2000 167 #else 168 #define CONFIG_ENV_IS_IN_FLASH 169 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 170 #define CONFIG_ENV_SIZE 0x2000 171 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 172 #endif 173 174 #ifndef __ASSEMBLY__ 175 unsigned long get_board_sys_clk(void); 176 unsigned long get_board_ddr_clk(void); 177 #endif 178 179 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 180 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 181 182 /* 183 * Config the L3 Cache as L3 SRAM 184 */ 185 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 186 #define CONFIG_SYS_L3_SIZE (512 << 10) 187 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 188 #ifdef CONFIG_RAMBOOT_PBL 189 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 190 #endif 191 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 192 #define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) 193 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 194 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 195 196 #define CONFIG_SYS_DCSRBAR 0xf0000000 197 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 198 199 /* EEPROM */ 200 #define CONFIG_ID_EEPROM 201 #define CONFIG_SYS_I2C_EEPROM_NXID 202 #define CONFIG_SYS_EEPROM_BUS_NUM 0 203 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 204 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 205 206 /* 207 * DDR Setup 208 */ 209 #define CONFIG_VERY_BIG_RAM 210 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 211 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 212 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 213 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 214 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 215 #define CONFIG_DDR_SPD 216 #define CONFIG_FSL_DDR_INTERACTIVE 217 #define CONFIG_SYS_SPD_BUS_NUM 0 218 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 219 #define SPD_EEPROM_ADDRESS1 0x51 220 #define SPD_EEPROM_ADDRESS2 0x52 221 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 222 #define CTRL_INTLV_PREFERED cacheline 223 224 /* 225 * IFC Definitions 226 */ 227 #define CONFIG_SYS_FLASH_BASE 0xe0000000 228 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 229 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 230 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 231 + 0x8000000) | \ 232 CSPR_PORT_SIZE_16 | \ 233 CSPR_MSEL_NOR | \ 234 CSPR_V) 235 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 236 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 237 CSPR_PORT_SIZE_16 | \ 238 CSPR_MSEL_NOR | \ 239 CSPR_V) 240 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 241 /* NOR Flash Timing Params */ 242 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 243 244 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 245 FTIM0_NOR_TEADC(0x5) | \ 246 FTIM0_NOR_TEAHC(0x5)) 247 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 248 FTIM1_NOR_TRAD_NOR(0x1A) |\ 249 FTIM1_NOR_TSEQRAD_NOR(0x13)) 250 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 251 FTIM2_NOR_TCH(0x4) | \ 252 FTIM2_NOR_TWPH(0x0E) | \ 253 FTIM2_NOR_TWP(0x1c)) 254 #define CONFIG_SYS_NOR_FTIM3 0x0 255 256 #define CONFIG_SYS_FLASH_QUIET_TEST 257 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 258 259 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 260 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 261 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 262 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 263 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 266 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 267 268 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 269 #define QIXIS_BASE 0xffdf0000 270 #define QIXIS_LBMAP_SWITCH 6 271 #define QIXIS_LBMAP_MASK 0x0f 272 #define QIXIS_LBMAP_SHIFT 0 273 #define QIXIS_LBMAP_DFLTBANK 0x00 274 #define QIXIS_LBMAP_ALTBANK 0x04 275 #define QIXIS_LBMAP_NAND 0x09 276 #define QIXIS_LBMAP_SD 0x00 277 #define QIXIS_RCW_SRC_NAND 0x104 278 #define QIXIS_RCW_SRC_SD 0x040 279 #define QIXIS_RST_CTL_RESET 0x83 280 #define QIXIS_RST_FORCE_MEM 0x1 281 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 282 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 283 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 284 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 285 286 #define CONFIG_SYS_CSPR3_EXT (0xf) 287 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 288 | CSPR_PORT_SIZE_8 \ 289 | CSPR_MSEL_GPCM \ 290 | CSPR_V) 291 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 292 #define CONFIG_SYS_CSOR3 0x0 293 /* QIXIS Timing parameters for IFC CS3 */ 294 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 295 FTIM0_GPCM_TEADC(0x0e) | \ 296 FTIM0_GPCM_TEAHC(0x0e)) 297 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 298 FTIM1_GPCM_TRAD(0x3f)) 299 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 300 FTIM2_GPCM_TCH(0x8) | \ 301 FTIM2_GPCM_TWP(0x1f)) 302 #define CONFIG_SYS_CS3_FTIM3 0x0 303 304 /* NAND Flash on IFC */ 305 #define CONFIG_NAND_FSL_IFC 306 #define CONFIG_SYS_NAND_BASE 0xff800000 307 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 308 309 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 310 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 311 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 312 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 313 | CSPR_V) 314 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 315 316 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 317 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 318 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 319 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 320 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 321 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 322 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 323 324 #define CONFIG_SYS_NAND_ONFI_DETECTION 325 326 /* ONFI NAND Flash mode0 Timing Params */ 327 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 328 FTIM0_NAND_TWP(0x18) | \ 329 FTIM0_NAND_TWCHT(0x07) | \ 330 FTIM0_NAND_TWH(0x0a)) 331 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 332 FTIM1_NAND_TWBE(0x39) | \ 333 FTIM1_NAND_TRR(0x0e) | \ 334 FTIM1_NAND_TRP(0x18)) 335 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 336 FTIM2_NAND_TREH(0x0a) | \ 337 FTIM2_NAND_TWHRE(0x1e)) 338 #define CONFIG_SYS_NAND_FTIM3 0x0 339 340 #define CONFIG_SYS_NAND_DDR_LAW 11 341 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 342 #define CONFIG_SYS_MAX_NAND_DEVICE 1 343 #define CONFIG_CMD_NAND 344 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 345 346 #if defined(CONFIG_NAND) 347 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 348 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 349 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 350 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 351 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 352 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 353 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 354 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 355 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 356 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 357 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 358 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 359 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 360 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 361 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 362 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 363 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 364 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 365 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 366 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 367 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 368 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 369 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 370 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 371 #else 372 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 373 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 374 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 375 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 376 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 377 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 378 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 379 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 380 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 381 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 382 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 383 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 384 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 385 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 386 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 387 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 388 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 389 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 390 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 391 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 392 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 393 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 394 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 395 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 396 #endif 397 398 #if defined(CONFIG_RAMBOOT_PBL) 399 #define CONFIG_SYS_RAMBOOT 400 #endif 401 402 #ifdef CONFIG_SPL_BUILD 403 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 404 #else 405 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 406 #endif 407 408 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 409 #define CONFIG_MISC_INIT_R 410 #define CONFIG_HWCONFIG 411 412 /* define to use L1 as initial stack */ 413 #define CONFIG_L1_INIT_RAM 414 #define CONFIG_SYS_INIT_RAM_LOCK 415 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 416 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 417 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 418 /* The assembler doesn't like typecast */ 419 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 420 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 421 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 422 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 423 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 424 GENERATED_GBL_DATA_SIZE) 425 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 426 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 427 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 428 429 /* 430 * Serial Port 431 */ 432 #define CONFIG_CONS_INDEX 1 433 #define CONFIG_SYS_NS16550_SERIAL 434 #define CONFIG_SYS_NS16550_REG_SIZE 1 435 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 436 #define CONFIG_SYS_BAUDRATE_TABLE \ 437 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 438 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 439 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 440 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 441 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 442 443 /* 444 * I2C 445 */ 446 #define CONFIG_SYS_I2C 447 #define CONFIG_SYS_I2C_FSL 448 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 449 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 450 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 451 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 452 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 453 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 454 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 455 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 456 #define CONFIG_SYS_FSL_I2C_SPEED 100000 457 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 458 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 459 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 460 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 461 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 462 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 463 #define I2C_MUX_CH_DEFAULT 0x8 464 465 #define I2C_MUX_CH_VOL_MONITOR 0xa 466 467 /* Voltage monitor on channel 2*/ 468 #define I2C_VOL_MONITOR_ADDR 0x40 469 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 470 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 471 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 472 473 #define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" 474 #ifndef CONFIG_SPL_BUILD 475 #define CONFIG_VID 476 #endif 477 #define CONFIG_VOL_MONITOR_IR36021_SET 478 #define CONFIG_VOL_MONITOR_IR36021_READ 479 /* The lowest and highest voltage allowed for T208xQDS */ 480 #define VDD_MV_MIN 819 481 #define VDD_MV_MAX 1212 482 483 /* 484 * RapidIO 485 */ 486 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 487 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 488 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 489 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 490 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 491 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 492 /* 493 * for slave u-boot IMAGE instored in master memory space, 494 * PHYS must be aligned based on the SIZE 495 */ 496 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 497 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 498 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 499 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 500 /* 501 * for slave UCODE and ENV instored in master memory space, 502 * PHYS must be aligned based on the SIZE 503 */ 504 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 505 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 506 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 507 508 /* slave core release by master*/ 509 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 510 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 511 512 /* 513 * SRIO_PCIE_BOOT - SLAVE 514 */ 515 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 516 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 517 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 518 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 519 #endif 520 521 /* 522 * eSPI - Enhanced SPI 523 */ 524 #ifdef CONFIG_SPI_FLASH 525 #ifndef CONFIG_SPL_BUILD 526 #endif 527 528 #define CONFIG_SPI_FLASH_BAR 529 #define CONFIG_SF_DEFAULT_SPEED 10000000 530 #define CONFIG_SF_DEFAULT_MODE 0 531 #endif 532 533 /* 534 * General PCI 535 * Memory space is mapped 1-1, but I/O space must start from 0. 536 */ 537 #define CONFIG_PCIE1 /* PCIE controller 1 */ 538 #define CONFIG_PCIE2 /* PCIE controller 2 */ 539 #define CONFIG_PCIE3 /* PCIE controller 3 */ 540 #define CONFIG_PCIE4 /* PCIE controller 4 */ 541 #define CONFIG_FSL_PCIE_RESET 542 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 543 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 544 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 545 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 546 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 547 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 548 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 549 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 550 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 551 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 552 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 553 554 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 555 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 556 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 557 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 558 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 559 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 560 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 561 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 562 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 563 564 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 565 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 566 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 567 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 568 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 569 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 570 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 571 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 572 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 573 574 /* controller 4, Base address 203000 */ 575 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 576 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 577 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 578 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 579 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 580 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 581 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 582 583 #ifdef CONFIG_PCI 584 #define CONFIG_PCI_INDIRECT_BRIDGE 585 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 586 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 587 #endif 588 589 /* Qman/Bman */ 590 #ifndef CONFIG_NOBQFMAN 591 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 592 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 593 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 594 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 595 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 596 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 597 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 598 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 599 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 600 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 601 CONFIG_SYS_BMAN_CENA_SIZE) 602 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 603 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 604 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 605 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 606 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 607 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 608 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 609 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 610 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 611 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 612 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 613 CONFIG_SYS_QMAN_CENA_SIZE) 614 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 615 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 616 617 #define CONFIG_SYS_DPAA_FMAN 618 #define CONFIG_SYS_DPAA_PME 619 #define CONFIG_SYS_PMAN 620 #define CONFIG_SYS_DPAA_DCE 621 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 622 #define CONFIG_SYS_INTERLAKEN 623 624 /* Default address of microcode for the Linux Fman driver */ 625 #if defined(CONFIG_SPIFLASH) 626 /* 627 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 628 * env, so we got 0x110000. 629 */ 630 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 631 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 632 #elif defined(CONFIG_SDCARD) 633 /* 634 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 635 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 636 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 637 */ 638 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 639 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 640 #elif defined(CONFIG_NAND) 641 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 642 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 643 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 644 /* 645 * Slave has no ucode locally, it can fetch this from remote. When implementing 646 * in two corenet boards, slave's ucode could be stored in master's memory 647 * space, the address can be mapped from slave TLB->slave LAW-> 648 * slave SRIO or PCIE outbound window->master inbound window-> 649 * master LAW->the ucode address in master's memory space. 650 */ 651 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 652 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 653 #else 654 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 655 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 656 #endif 657 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 658 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 659 #endif /* CONFIG_NOBQFMAN */ 660 661 #ifdef CONFIG_SYS_DPAA_FMAN 662 #define CONFIG_FMAN_ENET 663 #define CONFIG_PHYLIB_10G 664 #define CONFIG_PHY_VITESSE 665 #define CONFIG_PHY_REALTEK 666 #define CONFIG_PHY_TERANETICS 667 #define RGMII_PHY1_ADDR 0x1 668 #define RGMII_PHY2_ADDR 0x2 669 #define FM1_10GEC1_PHY_ADDR 0x3 670 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 671 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 672 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 673 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 674 #endif 675 676 #ifdef CONFIG_FMAN_ENET 677 #define CONFIG_MII /* MII PHY management */ 678 #define CONFIG_ETHPRIME "FM1@DTSEC3" 679 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 680 #endif 681 682 /* 683 * SATA 684 */ 685 #ifdef CONFIG_FSL_SATA_V2 686 #define CONFIG_LIBATA 687 #define CONFIG_FSL_SATA 688 #define CONFIG_SYS_SATA_MAX_DEVICE 2 689 #define CONFIG_SATA1 690 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 691 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 692 #define CONFIG_SATA2 693 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 694 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 695 #define CONFIG_LBA48 696 #endif 697 698 /* 699 * USB 700 */ 701 #ifdef CONFIG_USB_EHCI_HCD 702 #define CONFIG_USB_EHCI_FSL 703 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 704 #define CONFIG_HAS_FSL_DR_USB 705 #endif 706 707 /* 708 * SDHC 709 */ 710 #ifdef CONFIG_MMC 711 #define CONFIG_FSL_ESDHC 712 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 713 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 714 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 715 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 716 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 717 #endif 718 719 /* 720 * Dynamic MTD Partition support with mtdparts 721 */ 722 #ifdef CONFIG_MTD_NOR_FLASH 723 #define CONFIG_MTD_DEVICE 724 #define CONFIG_MTD_PARTITIONS 725 #define CONFIG_FLASH_CFI_MTD 726 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 727 "spi0=spife110000.0" 728 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 729 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \ 730 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \ 731 "1m(uboot),5m(kernel),128k(dtb),-(user)" 732 #endif 733 734 /* 735 * Environment 736 */ 737 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 738 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 739 740 /* 741 * Command line configuration. 742 */ 743 #define CONFIG_CMD_REGINFO 744 745 #ifdef CONFIG_PCI 746 #define CONFIG_CMD_PCI 747 #endif 748 749 /* 750 * Miscellaneous configurable options 751 */ 752 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 753 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 754 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 755 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 756 #ifdef CONFIG_CMD_KGDB 757 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 758 #else 759 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 760 #endif 761 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 762 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 763 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 764 765 /* 766 * For booting Linux, the board info and command line data 767 * have to be in the first 64 MB of memory, since this is 768 * the maximum mapped by the Linux kernel during initialization. 769 */ 770 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 771 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 772 773 #ifdef CONFIG_CMD_KGDB 774 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 775 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 776 #endif 777 778 /* 779 * Environment Configuration 780 */ 781 #define CONFIG_ROOTPATH "/opt/nfsroot" 782 #define CONFIG_BOOTFILE "uImage" 783 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 784 785 /* default location for tftp and bootm */ 786 #define CONFIG_LOADADDR 1000000 787 #define __USB_PHY_TYPE utmi 788 789 #define CONFIG_EXTRA_ENV_SETTINGS \ 790 "hwconfig=fsl_ddr:" \ 791 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 792 "bank_intlv=auto;" \ 793 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 794 "netdev=eth0\0" \ 795 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 796 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 797 "tftpflash=tftpboot $loadaddr $uboot && " \ 798 "protect off $ubootaddr +$filesize && " \ 799 "erase $ubootaddr +$filesize && " \ 800 "cp.b $loadaddr $ubootaddr $filesize && " \ 801 "protect on $ubootaddr +$filesize && " \ 802 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 803 "consoledev=ttyS0\0" \ 804 "ramdiskaddr=2000000\0" \ 805 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 806 "fdtaddr=1e00000\0" \ 807 "fdtfile=t2080qds/t2080qds.dtb\0" \ 808 "bdev=sda3\0" 809 810 /* 811 * For emulation this causes u-boot to jump to the start of the 812 * proof point app code automatically 813 */ 814 #define CONFIG_PROOF_POINTS \ 815 "setenv bootargs root=/dev/$bdev rw " \ 816 "console=$consoledev,$baudrate $othbootargs;" \ 817 "cpu 1 release 0x29000000 - - -;" \ 818 "cpu 2 release 0x29000000 - - -;" \ 819 "cpu 3 release 0x29000000 - - -;" \ 820 "cpu 4 release 0x29000000 - - -;" \ 821 "cpu 5 release 0x29000000 - - -;" \ 822 "cpu 6 release 0x29000000 - - -;" \ 823 "cpu 7 release 0x29000000 - - -;" \ 824 "go 0x29000000" 825 826 #define CONFIG_HVBOOT \ 827 "setenv bootargs config-addr=0x60000000; " \ 828 "bootm 0x01000000 - 0x00f00000" 829 830 #define CONFIG_ALU \ 831 "setenv bootargs root=/dev/$bdev rw " \ 832 "console=$consoledev,$baudrate $othbootargs;" \ 833 "cpu 1 release 0x01000000 - - -;" \ 834 "cpu 2 release 0x01000000 - - -;" \ 835 "cpu 3 release 0x01000000 - - -;" \ 836 "cpu 4 release 0x01000000 - - -;" \ 837 "cpu 5 release 0x01000000 - - -;" \ 838 "cpu 6 release 0x01000000 - - -;" \ 839 "cpu 7 release 0x01000000 - - -;" \ 840 "go 0x01000000" 841 842 #define CONFIG_LINUX \ 843 "setenv bootargs root=/dev/ram rw " \ 844 "console=$consoledev,$baudrate $othbootargs;" \ 845 "setenv ramdiskaddr 0x02000000;" \ 846 "setenv fdtaddr 0x00c00000;" \ 847 "setenv loadaddr 0x1000000;" \ 848 "bootm $loadaddr $ramdiskaddr $fdtaddr" 849 850 #define CONFIG_HDBOOT \ 851 "setenv bootargs root=/dev/$bdev rw " \ 852 "console=$consoledev,$baudrate $othbootargs;" \ 853 "tftp $loadaddr $bootfile;" \ 854 "tftp $fdtaddr $fdtfile;" \ 855 "bootm $loadaddr - $fdtaddr" 856 857 #define CONFIG_NFSBOOTCOMMAND \ 858 "setenv bootargs root=/dev/nfs rw " \ 859 "nfsroot=$serverip:$rootpath " \ 860 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 861 "console=$consoledev,$baudrate $othbootargs;" \ 862 "tftp $loadaddr $bootfile;" \ 863 "tftp $fdtaddr $fdtfile;" \ 864 "bootm $loadaddr - $fdtaddr" 865 866 #define CONFIG_RAMBOOTCOMMAND \ 867 "setenv bootargs root=/dev/ram rw " \ 868 "console=$consoledev,$baudrate $othbootargs;" \ 869 "tftp $ramdiskaddr $ramdiskfile;" \ 870 "tftp $loadaddr $bootfile;" \ 871 "tftp $fdtaddr $fdtfile;" \ 872 "bootm $loadaddr $ramdiskaddr $fdtaddr" 873 874 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 875 876 #include <asm/fsl_secure_boot.h> 877 878 #endif /* __T208xQDS_H */ 879