1 /* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef __CONFIG_H 24 #define __CONFIG_H 25 26 /* 27 * T1040 QDS board configuration file 28 */ 29 30 #ifdef CONFIG_RAMBOOT_PBL 31 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 33 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 39 #define CONFIG_MP /* support multiple processors */ 40 41 /* support deep sleep */ 42 #define CONFIG_DEEP_SLEEP 43 44 #ifndef CONFIG_SYS_TEXT_BASE 45 #define CONFIG_SYS_TEXT_BASE 0xeff40000 46 #endif 47 48 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #endif 51 52 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 53 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 54 #define CONFIG_PCI_INDIRECT_BRIDGE 55 #define CONFIG_PCIE1 /* PCIE controller 1 */ 56 #define CONFIG_PCIE2 /* PCIE controller 2 */ 57 #define CONFIG_PCIE3 /* PCIE controller 3 */ 58 #define CONFIG_PCIE4 /* PCIE controller 4 */ 59 60 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 61 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 62 63 #define CONFIG_ENV_OVERWRITE 64 65 #ifndef CONFIG_MTD_NOR_FLASH 66 #else 67 #define CONFIG_FLASH_CFI_DRIVER 68 #define CONFIG_SYS_FLASH_CFI 69 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 70 #endif 71 72 #ifdef CONFIG_MTD_NOR_FLASH 73 #if defined(CONFIG_SPIFLASH) 74 #define CONFIG_SYS_EXTRA_ENV_RELOC 75 #define CONFIG_ENV_IS_IN_SPI_FLASH 76 #define CONFIG_ENV_SPI_BUS 0 77 #define CONFIG_ENV_SPI_CS 0 78 #define CONFIG_ENV_SPI_MAX_HZ 10000000 79 #define CONFIG_ENV_SPI_MODE 0 80 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 81 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 82 #define CONFIG_ENV_SECT_SIZE 0x10000 83 #elif defined(CONFIG_SDCARD) 84 #define CONFIG_SYS_EXTRA_ENV_RELOC 85 #define CONFIG_SYS_MMC_ENV_DEV 0 86 #define CONFIG_ENV_SIZE 0x2000 87 #define CONFIG_ENV_OFFSET (512 * 1658) 88 #elif defined(CONFIG_NAND) 89 #define CONFIG_SYS_EXTRA_ENV_RELOC 90 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 91 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 92 #else 93 #define CONFIG_ENV_IS_IN_FLASH 94 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 95 #define CONFIG_ENV_SIZE 0x2000 96 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 97 #endif 98 #else /* CONFIG_MTD_NOR_FLASH */ 99 #define CONFIG_ENV_SIZE 0x2000 100 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 101 #endif 102 103 #ifndef __ASSEMBLY__ 104 unsigned long get_board_sys_clk(void); 105 unsigned long get_board_ddr_clk(void); 106 #endif 107 108 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 109 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 110 111 /* 112 * These can be toggled for performance analysis, otherwise use default. 113 */ 114 #define CONFIG_SYS_CACHE_STASHING 115 #define CONFIG_BACKSIDE_L2_CACHE 116 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 117 #define CONFIG_BTB /* toggle branch predition */ 118 #define CONFIG_DDR_ECC 119 #ifdef CONFIG_DDR_ECC 120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 121 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 122 #endif 123 124 #define CONFIG_ENABLE_36BIT_PHYS 125 126 #define CONFIG_ADDR_MAP 127 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 128 129 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 130 #define CONFIG_SYS_MEMTEST_END 0x00400000 131 #define CONFIG_SYS_ALT_MEMTEST 132 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 133 134 /* 135 * Config the L3 Cache as L3 SRAM 136 */ 137 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 138 139 #define CONFIG_SYS_DCSRBAR 0xf0000000 140 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 141 142 /* EEPROM */ 143 #define CONFIG_ID_EEPROM 144 #define CONFIG_SYS_I2C_EEPROM_NXID 145 #define CONFIG_SYS_EEPROM_BUS_NUM 0 146 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 147 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 148 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 149 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 150 151 /* 152 * DDR Setup 153 */ 154 #define CONFIG_VERY_BIG_RAM 155 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 156 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 157 158 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 159 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 160 161 #define CONFIG_DDR_SPD 162 #define CONFIG_FSL_DDR_INTERACTIVE 163 164 #define CONFIG_SYS_SPD_BUS_NUM 0 165 #define SPD_EEPROM_ADDRESS 0x51 166 167 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 168 169 /* 170 * IFC Definitions 171 */ 172 #define CONFIG_SYS_FLASH_BASE 0xe0000000 173 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 174 175 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 176 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 177 + 0x8000000) | \ 178 CSPR_PORT_SIZE_16 | \ 179 CSPR_MSEL_NOR | \ 180 CSPR_V) 181 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 182 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 183 CSPR_PORT_SIZE_16 | \ 184 CSPR_MSEL_NOR | \ 185 CSPR_V) 186 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 187 188 /* 189 * TDM Definition 190 */ 191 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 192 193 /* NOR Flash Timing Params */ 194 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 195 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 196 FTIM0_NOR_TEADC(0x5) | \ 197 FTIM0_NOR_TEAHC(0x5)) 198 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 199 FTIM1_NOR_TRAD_NOR(0x1A) |\ 200 FTIM1_NOR_TSEQRAD_NOR(0x13)) 201 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 202 FTIM2_NOR_TCH(0x4) | \ 203 FTIM2_NOR_TWPH(0x0E) | \ 204 FTIM2_NOR_TWP(0x1c)) 205 #define CONFIG_SYS_NOR_FTIM3 0x0 206 207 #define CONFIG_SYS_FLASH_QUIET_TEST 208 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 209 210 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 211 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 212 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 213 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 214 215 #define CONFIG_SYS_FLASH_EMPTY_INFO 216 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 217 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 218 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 219 #define QIXIS_BASE 0xffdf0000 220 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 221 #define QIXIS_LBMAP_SWITCH 0x06 222 #define QIXIS_LBMAP_MASK 0x0f 223 #define QIXIS_LBMAP_SHIFT 0 224 #define QIXIS_LBMAP_DFLTBANK 0x00 225 #define QIXIS_LBMAP_ALTBANK 0x04 226 #define QIXIS_RST_CTL_RESET 0x31 227 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 228 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 229 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 230 #define QIXIS_RST_FORCE_MEM 0x01 231 232 #define CONFIG_SYS_CSPR3_EXT (0xf) 233 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 234 | CSPR_PORT_SIZE_8 \ 235 | CSPR_MSEL_GPCM \ 236 | CSPR_V) 237 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 238 #define CONFIG_SYS_CSOR3 0x0 239 /* QIXIS Timing parameters for IFC CS3 */ 240 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 241 FTIM0_GPCM_TEADC(0x0e) | \ 242 FTIM0_GPCM_TEAHC(0x0e)) 243 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 244 FTIM1_GPCM_TRAD(0x3f)) 245 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 246 FTIM2_GPCM_TCH(0x8) | \ 247 FTIM2_GPCM_TWP(0x1f)) 248 #define CONFIG_SYS_CS3_FTIM3 0x0 249 250 #define CONFIG_NAND_FSL_IFC 251 #define CONFIG_SYS_NAND_BASE 0xff800000 252 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 253 254 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 255 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 257 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 258 | CSPR_V) 259 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 260 261 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 262 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 263 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 264 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 265 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 266 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 267 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 268 269 #define CONFIG_SYS_NAND_ONFI_DETECTION 270 271 /* ONFI NAND Flash mode0 Timing Params */ 272 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 273 FTIM0_NAND_TWP(0x18) | \ 274 FTIM0_NAND_TWCHT(0x07) | \ 275 FTIM0_NAND_TWH(0x0a)) 276 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 277 FTIM1_NAND_TWBE(0x39) | \ 278 FTIM1_NAND_TRR(0x0e) | \ 279 FTIM1_NAND_TRP(0x18)) 280 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 281 FTIM2_NAND_TREH(0x0a) | \ 282 FTIM2_NAND_TWHRE(0x1e)) 283 #define CONFIG_SYS_NAND_FTIM3 0x0 284 285 #define CONFIG_SYS_NAND_DDR_LAW 11 286 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 287 #define CONFIG_SYS_MAX_NAND_DEVICE 1 288 #define CONFIG_CMD_NAND 289 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 291 292 #if defined(CONFIG_NAND) 293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 301 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 302 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 303 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 304 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 305 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 306 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 307 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 308 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 309 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 310 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 311 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #else 318 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 319 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 320 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 321 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 322 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 323 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 324 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 325 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 326 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 327 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 328 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 335 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 336 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 337 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 338 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 339 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 340 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 341 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 342 #endif 343 344 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 345 346 #if defined(CONFIG_RAMBOOT_PBL) 347 #define CONFIG_SYS_RAMBOOT 348 #endif 349 350 #define CONFIG_BOARD_EARLY_INIT_R 351 #define CONFIG_MISC_INIT_R 352 353 #define CONFIG_HWCONFIG 354 355 /* define to use L1 as initial stack */ 356 #define CONFIG_L1_INIT_RAM 357 #define CONFIG_SYS_INIT_RAM_LOCK 358 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 359 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 360 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 361 /* The assembler doesn't like typecast */ 362 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 363 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 364 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 365 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 366 367 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 368 GENERATED_GBL_DATA_SIZE) 369 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 370 371 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 372 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 373 374 /* Serial Port - controlled on board with jumper J8 375 * open - index 2 376 * shorted - index 1 377 */ 378 #define CONFIG_CONS_INDEX 1 379 #define CONFIG_SYS_NS16550_SERIAL 380 #define CONFIG_SYS_NS16550_REG_SIZE 1 381 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 382 383 #define CONFIG_SYS_BAUDRATE_TABLE \ 384 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 385 386 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 387 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 388 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 389 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 390 391 /* Video */ 392 #define CONFIG_FSL_DIU_FB 393 #ifdef CONFIG_FSL_DIU_FB 394 #define CONFIG_FSL_DIU_CH7301 395 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 396 #define CONFIG_VIDEO_LOGO 397 #define CONFIG_VIDEO_BMP_LOGO 398 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS 399 /* 400 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so 401 * disable empty flash sector detection, which is I/O-intensive. 402 */ 403 #undef CONFIG_SYS_FLASH_EMPTY_INFO 404 #endif 405 406 /* I2C */ 407 #define CONFIG_SYS_I2C 408 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 409 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 410 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 411 #define CONFIG_SYS_FSL_I2C3_SPEED 50000 412 #define CONFIG_SYS_FSL_I2C4_SPEED 50000 413 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 415 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 417 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 418 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 419 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 420 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 421 422 #define I2C_MUX_PCA_ADDR 0x77 423 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 424 425 /* I2C bus multiplexer */ 426 #define I2C_MUX_CH_DEFAULT 0x8 427 #define I2C_MUX_CH_DIU 0xC 428 429 /* LDI/DVI Encoder for display */ 430 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 431 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 432 433 /* 434 * RTC configuration 435 */ 436 #define RTC 437 #define CONFIG_RTC_DS3231 1 438 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 439 440 /* 441 * eSPI - Enhanced SPI 442 */ 443 #define CONFIG_SF_DEFAULT_SPEED 10000000 444 #define CONFIG_SF_DEFAULT_MODE 0 445 446 /* 447 * General PCI 448 * Memory space is mapped 1-1, but I/O space must start from 0. 449 */ 450 451 #ifdef CONFIG_PCI 452 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 453 #ifdef CONFIG_PCIE1 454 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 455 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 456 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 457 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 458 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 459 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 460 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 461 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 462 #endif 463 464 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 465 #ifdef CONFIG_PCIE2 466 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 467 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 468 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 469 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 470 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 471 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 472 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 473 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 474 #endif 475 476 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 477 #ifdef CONFIG_PCIE3 478 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 479 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 480 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 481 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 482 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 483 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 484 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 485 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 486 #endif 487 488 /* controller 4, Base address 203000 */ 489 #ifdef CONFIG_PCIE4 490 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 491 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 492 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 493 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 494 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 495 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 496 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 497 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 498 #endif 499 500 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 501 #endif /* CONFIG_PCI */ 502 503 /* SATA */ 504 #define CONFIG_FSL_SATA_V2 505 #ifdef CONFIG_FSL_SATA_V2 506 #define CONFIG_LIBATA 507 #define CONFIG_FSL_SATA 508 509 #define CONFIG_SYS_SATA_MAX_DEVICE 2 510 #define CONFIG_SATA1 511 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 512 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 513 #define CONFIG_SATA2 514 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 515 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 516 517 #define CONFIG_LBA48 518 #endif 519 520 /* 521 * USB 522 */ 523 #define CONFIG_HAS_FSL_DR_USB 524 525 #ifdef CONFIG_HAS_FSL_DR_USB 526 #ifdef CONFIG_USB_EHCI_HCD 527 #define CONFIG_USB_EHCI_FSL 528 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 529 #endif 530 #endif 531 532 #ifdef CONFIG_MMC 533 #define CONFIG_FSL_ESDHC 534 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK 535 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 536 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT 537 #endif 538 539 /* Qman/Bman */ 540 #ifndef CONFIG_NOBQFMAN 541 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 542 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 543 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 544 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 545 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 546 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 547 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 548 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 549 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 550 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 551 CONFIG_SYS_BMAN_CENA_SIZE) 552 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 553 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 554 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 555 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 556 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 557 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 558 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 559 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 560 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 561 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 562 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 563 CONFIG_SYS_QMAN_CENA_SIZE) 564 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 565 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 566 567 #define CONFIG_SYS_DPAA_FMAN 568 #define CONFIG_SYS_DPAA_PME 569 570 #define CONFIG_QE 571 #define CONFIG_U_QE 572 /* Default address of microcode for the Linux Fman driver */ 573 #if defined(CONFIG_SPIFLASH) 574 /* 575 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 576 * env, so we got 0x110000. 577 */ 578 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 579 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 580 #elif defined(CONFIG_SDCARD) 581 /* 582 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 583 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 584 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 585 */ 586 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 587 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 588 #elif defined(CONFIG_NAND) 589 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 590 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 591 #else 592 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 593 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 594 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 595 #endif 596 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 597 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 598 #endif /* CONFIG_NOBQFMAN */ 599 600 #ifdef CONFIG_SYS_DPAA_FMAN 601 #define CONFIG_FMAN_ENET 602 #define CONFIG_PHYLIB_10G 603 #define CONFIG_PHY_VITESSE 604 #define CONFIG_PHY_REALTEK 605 #define CONFIG_PHY_TERANETICS 606 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 607 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 608 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 609 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 610 #endif 611 612 #ifdef CONFIG_FMAN_ENET 613 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 614 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 615 616 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 617 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 618 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 619 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 620 621 #define CONFIG_MII /* MII PHY management */ 622 #define CONFIG_ETHPRIME "FM1@DTSEC1" 623 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 624 #endif 625 626 /* Enable VSC9953 L2 Switch driver */ 627 #define CONFIG_VSC9953 628 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 629 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 630 631 /* 632 * Dynamic MTD Partition support with mtdparts 633 */ 634 #ifdef CONFIG_MTD_NOR_FLASH 635 #define CONFIG_MTD_DEVICE 636 #define CONFIG_MTD_PARTITIONS 637 #define CONFIG_FLASH_CFI_MTD 638 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 639 "spi0=spife110000.0" 640 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 641 "128k(dtb),96m(fs),-(user);"\ 642 "fff800000.flash:2m(uboot),9m(kernel),"\ 643 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 644 "2m(uboot),9m(kernel),128k(dtb),-(user)" 645 #endif 646 647 /* 648 * Environment 649 */ 650 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 651 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 652 653 /* 654 * Command line configuration. 655 */ 656 #define CONFIG_CMD_REGINFO 657 658 #ifdef CONFIG_PCI 659 #define CONFIG_CMD_PCI 660 #endif 661 662 /* 663 * Miscellaneous configurable options 664 */ 665 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 666 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 667 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 668 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 669 #ifdef CONFIG_CMD_KGDB 670 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 671 #else 672 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 673 #endif 674 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 675 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 676 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 677 678 /* 679 * For booting Linux, the board info and command line data 680 * have to be in the first 64 MB of memory, since this is 681 * the maximum mapped by the Linux kernel during initialization. 682 */ 683 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 684 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 685 686 #ifdef CONFIG_CMD_KGDB 687 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 688 #endif 689 690 /* 691 * Environment Configuration 692 */ 693 #define CONFIG_ROOTPATH "/opt/nfsroot" 694 #define CONFIG_BOOTFILE "uImage" 695 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 696 697 /* default location for tftp and bootm */ 698 #define CONFIG_LOADADDR 1000000 699 700 #define __USB_PHY_TYPE utmi 701 702 #define CONFIG_EXTRA_ENV_SETTINGS \ 703 "hwconfig=fsl_ddr:bank_intlv=auto;" \ 704 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 705 "netdev=eth0\0" \ 706 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ 707 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 708 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 709 "tftpflash=tftpboot $loadaddr $uboot && " \ 710 "protect off $ubootaddr +$filesize && " \ 711 "erase $ubootaddr +$filesize && " \ 712 "cp.b $loadaddr $ubootaddr $filesize && " \ 713 "protect on $ubootaddr +$filesize && " \ 714 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 715 "consoledev=ttyS0\0" \ 716 "ramdiskaddr=2000000\0" \ 717 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 718 "fdtaddr=1e00000\0" \ 719 "fdtfile=t1040qds/t1040qds.dtb\0" \ 720 "bdev=sda3\0" 721 722 #define CONFIG_LINUX \ 723 "setenv bootargs root=/dev/ram rw " \ 724 "console=$consoledev,$baudrate $othbootargs;" \ 725 "setenv ramdiskaddr 0x02000000;" \ 726 "setenv fdtaddr 0x00c00000;" \ 727 "setenv loadaddr 0x1000000;" \ 728 "bootm $loadaddr $ramdiskaddr $fdtaddr" 729 730 #define CONFIG_HDBOOT \ 731 "setenv bootargs root=/dev/$bdev rw " \ 732 "console=$consoledev,$baudrate $othbootargs;" \ 733 "tftp $loadaddr $bootfile;" \ 734 "tftp $fdtaddr $fdtfile;" \ 735 "bootm $loadaddr - $fdtaddr" 736 737 #define CONFIG_NFSBOOTCOMMAND \ 738 "setenv bootargs root=/dev/nfs rw " \ 739 "nfsroot=$serverip:$rootpath " \ 740 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 741 "console=$consoledev,$baudrate $othbootargs;" \ 742 "tftp $loadaddr $bootfile;" \ 743 "tftp $fdtaddr $fdtfile;" \ 744 "bootm $loadaddr - $fdtaddr" 745 746 #define CONFIG_RAMBOOTCOMMAND \ 747 "setenv bootargs root=/dev/ram rw " \ 748 "console=$consoledev,$baudrate $othbootargs;" \ 749 "tftp $ramdiskaddr $ramdiskfile;" \ 750 "tftp $loadaddr $bootfile;" \ 751 "tftp $fdtaddr $fdtfile;" \ 752 "bootm $loadaddr $ramdiskaddr $fdtaddr" 753 754 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 755 756 #include <asm/fsl_secure_boot.h> 757 758 #endif /* __CONFIG_H */ 759