1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * T4240 QDS board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_FSL_SATA_V2 14 #define CONFIG_PCIE4 15 16 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 17 18 #ifdef CONFIG_RAMBOOT_PBL 19 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg 20 #if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x00201000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #define RESET_VECTOR_OFFSET 0x27FFC 31 #define BOOT_PAGE_OFFSET 0x27000 32 33 #ifdef CONFIG_NAND 34 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 37 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 38 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 39 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg 40 #define CONFIG_SPL_NAND_BOOT 41 #endif 42 43 #ifdef CONFIG_SDCARD 44 #define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC 45 #define CONFIG_SPL_MMC_MINIMAL 46 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 47 #define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 48 #define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 49 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 50 #ifndef CONFIG_SPL_BUILD 51 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 52 #endif 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 54 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg 55 #define CONFIG_SPL_MMC_BOOT 56 #endif 57 58 #ifdef CONFIG_SPL_BUILD 59 #define CONFIG_SPL_SKIP_RELOCATE 60 #define CONFIG_SPL_COMMON_INIT_DDR 61 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 62 #endif 63 64 #endif 65 #endif /* CONFIG_RAMBOOT_PBL */ 66 67 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 68 /* Set 1M boot space */ 69 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 70 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 71 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 72 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 73 #endif 74 75 #define CONFIG_SRIO_PCIE_BOOT_MASTER 76 #define CONFIG_DDR_ECC 77 78 #include "t4qds.h" 79 80 #ifndef CONFIG_MTD_NOR_FLASH 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_BUS 0 91 #define CONFIG_ENV_SPI_CS 0 92 #define CONFIG_ENV_SPI_MAX_HZ 10000000 93 #define CONFIG_ENV_SPI_MODE 0 94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 96 #define CONFIG_ENV_SECT_SIZE 0x10000 97 #elif defined(CONFIG_SDCARD) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_SYS_MMC_ENV_DEV 0 100 #define CONFIG_ENV_SIZE 0x2000 101 #define CONFIG_ENV_OFFSET (512 * 0x800) 102 #elif defined(CONFIG_NAND) 103 #define CONFIG_SYS_EXTRA_ENV_RELOC 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 106 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 107 #define CONFIG_ENV_IS_IN_REMOTE 108 #define CONFIG_ENV_ADDR 0xffe20000 109 #define CONFIG_ENV_SIZE 0x2000 110 #elif defined(CONFIG_ENV_IS_NOWHERE) 111 #define CONFIG_ENV_SIZE 0x2000 112 #else 113 #define CONFIG_ENV_IS_IN_FLASH 114 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 115 #define CONFIG_ENV_SIZE 0x2000 116 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 117 #endif 118 119 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 120 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 121 122 #ifndef __ASSEMBLY__ 123 unsigned long get_board_sys_clk(void); 124 unsigned long get_board_ddr_clk(void); 125 #endif 126 127 /* EEPROM */ 128 #define CONFIG_ID_EEPROM 129 #define CONFIG_SYS_I2C_EEPROM_NXID 130 #define CONFIG_SYS_EEPROM_BUS_NUM 0 131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 133 134 /* 135 * DDR Setup 136 */ 137 #define CONFIG_SYS_SPD_BUS_NUM 0 138 #define SPD_EEPROM_ADDRESS1 0x51 139 #define SPD_EEPROM_ADDRESS2 0x52 140 #define SPD_EEPROM_ADDRESS3 0x53 141 #define SPD_EEPROM_ADDRESS4 0x54 142 #define SPD_EEPROM_ADDRESS5 0x55 143 #define SPD_EEPROM_ADDRESS6 0x56 144 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 145 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 146 147 /* 148 * IFC Definitions 149 */ 150 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 151 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 152 + 0x8000000) | \ 153 CSPR_PORT_SIZE_16 | \ 154 CSPR_MSEL_NOR | \ 155 CSPR_V) 156 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 157 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 158 CSPR_PORT_SIZE_16 | \ 159 CSPR_MSEL_NOR | \ 160 CSPR_V) 161 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 162 /* NOR Flash Timing Params */ 163 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 164 165 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 166 FTIM0_NOR_TEADC(0x5) | \ 167 FTIM0_NOR_TEAHC(0x5)) 168 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 169 FTIM1_NOR_TRAD_NOR(0x1A) |\ 170 FTIM1_NOR_TSEQRAD_NOR(0x13)) 171 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 172 FTIM2_NOR_TCH(0x4) | \ 173 FTIM2_NOR_TWPH(0x0E) | \ 174 FTIM2_NOR_TWP(0x1c)) 175 #define CONFIG_SYS_NOR_FTIM3 0x0 176 177 #define CONFIG_SYS_FLASH_QUIET_TEST 178 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 179 180 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 181 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 182 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 183 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 184 185 #define CONFIG_SYS_FLASH_EMPTY_INFO 186 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 187 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 188 189 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 190 #define QIXIS_BASE 0xffdf0000 191 #define QIXIS_LBMAP_SWITCH 6 192 #define QIXIS_LBMAP_MASK 0x0f 193 #define QIXIS_LBMAP_SHIFT 0 194 #define QIXIS_LBMAP_DFLTBANK 0x00 195 #define QIXIS_LBMAP_ALTBANK 0x04 196 #define QIXIS_RST_CTL_RESET 0x83 197 #define QIXIS_RST_FORCE_MEM 0x1 198 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 199 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 200 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 201 #define QIXIS_BRDCFG5 0x55 202 #define QIXIS_MUX_SDHC 2 203 #define QIXIS_MUX_SDHC_WIDTH8 1 204 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 205 206 #define CONFIG_SYS_CSPR3_EXT (0xf) 207 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 208 | CSPR_PORT_SIZE_8 \ 209 | CSPR_MSEL_GPCM \ 210 | CSPR_V) 211 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 212 #define CONFIG_SYS_CSOR3 0x0 213 /* QIXIS Timing parameters for IFC CS3 */ 214 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 215 FTIM0_GPCM_TEADC(0x0e) | \ 216 FTIM0_GPCM_TEAHC(0x0e)) 217 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 218 FTIM1_GPCM_TRAD(0x3f)) 219 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 220 FTIM2_GPCM_TCH(0x8) | \ 221 FTIM2_GPCM_TWP(0x1f)) 222 #define CONFIG_SYS_CS3_FTIM3 0x0 223 224 /* NAND Flash on IFC */ 225 #define CONFIG_NAND_FSL_IFC 226 #define CONFIG_SYS_NAND_BASE 0xff800000 227 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 228 229 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 230 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 231 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 232 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 233 | CSPR_V) 234 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 235 236 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 237 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 238 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 239 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 240 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 241 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 242 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 243 244 #define CONFIG_SYS_NAND_ONFI_DETECTION 245 246 /* ONFI NAND Flash mode0 Timing Params */ 247 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 248 FTIM0_NAND_TWP(0x18) | \ 249 FTIM0_NAND_TWCHT(0x07) | \ 250 FTIM0_NAND_TWH(0x0a)) 251 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 252 FTIM1_NAND_TWBE(0x39) | \ 253 FTIM1_NAND_TRR(0x0e) | \ 254 FTIM1_NAND_TRP(0x18)) 255 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 256 FTIM2_NAND_TREH(0x0a) | \ 257 FTIM2_NAND_TWHRE(0x1e)) 258 #define CONFIG_SYS_NAND_FTIM3 0x0 259 260 #define CONFIG_SYS_NAND_DDR_LAW 11 261 262 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 263 #define CONFIG_SYS_MAX_NAND_DEVICE 1 264 #define CONFIG_CMD_NAND 265 266 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 267 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 268 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 269 270 #if defined(CONFIG_NAND) 271 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 272 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 273 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 274 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 275 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 276 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 277 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 278 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 279 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 280 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 281 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 282 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 283 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 284 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 285 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 286 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 287 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 288 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 289 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 290 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 291 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 292 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 293 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 294 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 295 #else 296 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 297 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 298 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 299 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 300 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 301 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 302 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 303 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 304 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 305 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 306 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 307 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 308 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 309 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 310 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 311 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 312 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 313 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 314 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 315 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 316 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 317 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 318 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 319 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 320 #endif 321 322 #if defined(CONFIG_RAMBOOT_PBL) 323 #define CONFIG_SYS_RAMBOOT 324 #endif 325 326 /* I2C */ 327 #define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ 328 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ 329 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 330 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ 331 332 #define I2C_MUX_CH_DEFAULT 0x8 333 #define I2C_MUX_CH_VOL_MONITOR 0xa 334 #define I2C_MUX_CH_VSC3316_FS 0xc 335 #define I2C_MUX_CH_VSC3316_BS 0xd 336 337 /* Voltage monitor on channel 2*/ 338 #define I2C_VOL_MONITOR_ADDR 0x40 339 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 340 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 341 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 342 343 /* VSC Crossbar switches */ 344 #define CONFIG_VSC_CROSSBAR 345 #define VSC3316_FSM_TX_ADDR 0x70 346 #define VSC3316_FSM_RX_ADDR 0x71 347 348 /* 349 * RapidIO 350 */ 351 352 /* 353 * for slave u-boot IMAGE instored in master memory space, 354 * PHYS must be aligned based on the SIZE 355 */ 356 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 360 /* 361 * for slave UCODE and ENV instored in master memory space, 362 * PHYS must be aligned based on the SIZE 363 */ 364 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 367 368 /* slave core release by master*/ 369 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 370 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 371 372 /* 373 * SRIO_PCIE_BOOT - SLAVE 374 */ 375 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 376 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 378 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 379 #endif 380 /* 381 * eSPI - Enhanced SPI 382 */ 383 #define CONFIG_SF_DEFAULT_SPEED 10000000 384 #define CONFIG_SF_DEFAULT_MODE 0 385 386 /* Qman/Bman */ 387 #ifndef CONFIG_NOBQFMAN 388 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 389 #define CONFIG_SYS_BMAN_NUM_PORTALS 50 390 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 391 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 392 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 393 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 394 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 395 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 396 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 397 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 398 CONFIG_SYS_BMAN_CENA_SIZE) 399 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 400 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 401 #define CONFIG_SYS_QMAN_NUM_PORTALS 50 402 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 403 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 404 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 405 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 406 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 407 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 408 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 409 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 410 CONFIG_SYS_QMAN_CENA_SIZE) 411 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 412 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 413 414 #define CONFIG_SYS_DPAA_FMAN 415 #define CONFIG_SYS_DPAA_PME 416 #define CONFIG_SYS_PMAN 417 #define CONFIG_SYS_DPAA_DCE 418 #define CONFIG_SYS_DPAA_RMAN 419 #define CONFIG_SYS_INTERLAKEN 420 421 /* Default address of microcode for the Linux Fman driver */ 422 #if defined(CONFIG_SPIFLASH) 423 /* 424 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 425 * env, so we got 0x110000. 426 */ 427 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 428 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 429 #elif defined(CONFIG_SDCARD) 430 /* 431 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 432 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 433 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 434 */ 435 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 436 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 437 #elif defined(CONFIG_NAND) 438 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 439 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) 440 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 441 /* 442 * Slave has no ucode locally, it can fetch this from remote. When implementing 443 * in two corenet boards, slave's ucode could be stored in master's memory 444 * space, the address can be mapped from slave TLB->slave LAW-> 445 * slave SRIO or PCIE outbound window->master inbound window-> 446 * master LAW->the ucode address in master's memory space. 447 */ 448 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 449 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 450 #else 451 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 452 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 453 #endif 454 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 455 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 456 #endif /* CONFIG_NOBQFMAN */ 457 458 #ifdef CONFIG_SYS_DPAA_FMAN 459 #define CONFIG_FMAN_ENET 460 #define CONFIG_PHYLIB_10G 461 #define CONFIG_PHY_VITESSE 462 #define CONFIG_PHY_TERANETICS 463 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 464 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 465 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 466 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 467 #define FM1_10GEC1_PHY_ADDR 0x0 468 #define FM1_10GEC2_PHY_ADDR 0x1 469 #define FM2_10GEC1_PHY_ADDR 0x2 470 #define FM2_10GEC2_PHY_ADDR 0x3 471 #endif 472 473 /* SATA */ 474 #ifdef CONFIG_FSL_SATA_V2 475 #define CONFIG_LIBATA 476 #define CONFIG_FSL_SATA 477 478 #define CONFIG_SYS_SATA_MAX_DEVICE 2 479 #define CONFIG_SATA1 480 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 481 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 482 #define CONFIG_SATA2 483 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 484 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 485 486 #define CONFIG_LBA48 487 #endif 488 489 #ifdef CONFIG_FMAN_ENET 490 #define CONFIG_MII /* MII PHY management */ 491 #define CONFIG_ETHPRIME "FM1@DTSEC1" 492 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 493 #endif 494 495 /* 496 * USB 497 */ 498 #define CONFIG_USB_EHCI_FSL 499 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 500 #define CONFIG_HAS_FSL_DR_USB 501 502 #ifdef CONFIG_MMC 503 #define CONFIG_FSL_ESDHC 504 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 505 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 506 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 507 #define CONFIG_ESDHC_DETECT_QUIRK \ 508 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ 509 IS_SVR_REV(get_svr(), 1, 0)) 510 #define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ 511 (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) 512 #endif 513 514 515 #define __USB_PHY_TYPE utmi 516 517 /* 518 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be 519 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way 520 * interleaving. It can be cacheline, page, bank, superbank. 521 * See doc/README.fsl-ddr for details. 522 */ 523 #ifdef CONFIG_ARCH_T4240 524 #define CTRL_INTLV_PREFERED 3way_4KB 525 #else 526 #define CTRL_INTLV_PREFERED cacheline 527 #endif 528 529 #define CONFIG_EXTRA_ENV_SETTINGS \ 530 "hwconfig=fsl_ddr:" \ 531 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 532 "bank_intlv=auto;" \ 533 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 534 "netdev=eth0\0" \ 535 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 536 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 537 "tftpflash=tftpboot $loadaddr $uboot && " \ 538 "protect off $ubootaddr +$filesize && " \ 539 "erase $ubootaddr +$filesize && " \ 540 "cp.b $loadaddr $ubootaddr $filesize && " \ 541 "protect on $ubootaddr +$filesize && " \ 542 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 543 "consoledev=ttyS0\0" \ 544 "ramdiskaddr=2000000\0" \ 545 "ramdiskfile=t4240qds/ramdisk.uboot\0" \ 546 "fdtaddr=1e00000\0" \ 547 "fdtfile=t4240qds/t4240qds.dtb\0" \ 548 "bdev=sda3\0" 549 550 #define CONFIG_HVBOOT \ 551 "setenv bootargs config-addr=0x60000000; " \ 552 "bootm 0x01000000 - 0x00f00000" 553 554 #define CONFIG_ALU \ 555 "setenv bootargs root=/dev/$bdev rw " \ 556 "console=$consoledev,$baudrate $othbootargs;" \ 557 "cpu 1 release 0x01000000 - - -;" \ 558 "cpu 2 release 0x01000000 - - -;" \ 559 "cpu 3 release 0x01000000 - - -;" \ 560 "cpu 4 release 0x01000000 - - -;" \ 561 "cpu 5 release 0x01000000 - - -;" \ 562 "cpu 6 release 0x01000000 - - -;" \ 563 "cpu 7 release 0x01000000 - - -;" \ 564 "go 0x01000000" 565 566 #define CONFIG_LINUX \ 567 "setenv bootargs root=/dev/ram rw " \ 568 "console=$consoledev,$baudrate $othbootargs;" \ 569 "setenv ramdiskaddr 0x02000000;" \ 570 "setenv fdtaddr 0x00c00000;" \ 571 "setenv loadaddr 0x1000000;" \ 572 "bootm $loadaddr $ramdiskaddr $fdtaddr" 573 574 #define CONFIG_HDBOOT \ 575 "setenv bootargs root=/dev/$bdev rw " \ 576 "console=$consoledev,$baudrate $othbootargs;" \ 577 "tftp $loadaddr $bootfile;" \ 578 "tftp $fdtaddr $fdtfile;" \ 579 "bootm $loadaddr - $fdtaddr" 580 581 #define CONFIG_NFSBOOTCOMMAND \ 582 "setenv bootargs root=/dev/nfs rw " \ 583 "nfsroot=$serverip:$rootpath " \ 584 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 585 "console=$consoledev,$baudrate $othbootargs;" \ 586 "tftp $loadaddr $bootfile;" \ 587 "tftp $fdtaddr $fdtfile;" \ 588 "bootm $loadaddr - $fdtaddr" 589 590 #define CONFIG_RAMBOOTCOMMAND \ 591 "setenv bootargs root=/dev/ram rw " \ 592 "console=$consoledev,$baudrate $othbootargs;" \ 593 "tftp $ramdiskaddr $ramdiskfile;" \ 594 "tftp $loadaddr $bootfile;" \ 595 "tftp $fdtaddr $fdtfile;" \ 596 "bootm $loadaddr $ramdiskaddr $fdtaddr" 597 598 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 599 600 #include <asm/fsl_secure_boot.h> 601 602 #endif /* __CONFIG_H */ 603