1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #if defined(CONFIG_SPIFLASH) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_IS_IN_SPI_FLASH 78 #define CONFIG_ENV_SPI_BUS 0 79 #define CONFIG_ENV_SPI_CS 0 80 #define CONFIG_ENV_SPI_MAX_HZ 10000000 81 #define CONFIG_ENV_SPI_MODE 0 82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 84 #define CONFIG_ENV_SECT_SIZE 0x10000 85 #elif defined(CONFIG_SDCARD) 86 #define CONFIG_SYS_EXTRA_ENV_RELOC 87 #define CONFIG_FSL_FIXED_MMC_LOCATION 88 #define CONFIG_SYS_MMC_ENV_DEV 0 89 #define CONFIG_ENV_SIZE 0x2000 90 #define CONFIG_ENV_OFFSET (512 * 1658) 91 #elif defined(CONFIG_NAND) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 94 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 95 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 96 #define CONFIG_ENV_IS_IN_REMOTE 97 #define CONFIG_ENV_ADDR 0xffe20000 98 #define CONFIG_ENV_SIZE 0x2000 99 #elif defined(CONFIG_ENV_IS_NOWHERE) 100 #define CONFIG_ENV_SIZE 0x2000 101 #else 102 #define CONFIG_ENV_IS_IN_FLASH 103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 104 #define CONFIG_ENV_SIZE 0x2000 105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 106 #endif 107 108 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 109 110 /* 111 * These can be toggled for performance analysis, otherwise use default. 112 */ 113 #define CONFIG_SYS_CACHE_STASHING 114 #define CONFIG_BACKSIDE_L2_CACHE 115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 116 #define CONFIG_BTB /* toggle branch predition */ 117 #define CONFIG_DDR_ECC 118 #ifdef CONFIG_DDR_ECC 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 121 #endif 122 123 #define CONFIG_ENABLE_36BIT_PHYS 124 125 #ifdef CONFIG_PHYS_64BIT 126 #define CONFIG_ADDR_MAP 127 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 128 #endif 129 130 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 131 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 132 #define CONFIG_SYS_MEMTEST_END 0x00400000 133 #define CONFIG_SYS_ALT_MEMTEST 134 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 135 136 /* 137 * Config the L3 Cache as L3 SRAM 138 */ 139 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 140 #ifdef CONFIG_PHYS_64BIT 141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 142 #else 143 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 144 #endif 145 #define CONFIG_SYS_L3_SIZE (1024 << 10) 146 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 147 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_DCSRBAR 0xf0000000 150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 151 #endif 152 153 /* EEPROM */ 154 #define CONFIG_ID_EEPROM 155 #define CONFIG_SYS_I2C_EEPROM_NXID 156 #define CONFIG_SYS_EEPROM_BUS_NUM 0 157 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 158 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 159 160 /* 161 * DDR Setup 162 */ 163 #define CONFIG_VERY_BIG_RAM 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 166 167 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 170 #define CONFIG_DDR_SPD 171 172 #define CONFIG_SYS_SPD_BUS_NUM 1 173 #define SPD_EEPROM_ADDRESS1 0x51 174 #define SPD_EEPROM_ADDRESS2 0x52 175 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 176 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 177 178 /* 179 * Local Bus Definitions 180 */ 181 182 /* Set the local bus clock 1/8 of platform clock */ 183 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 184 185 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 186 #ifdef CONFIG_PHYS_64BIT 187 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 188 #else 189 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 190 #endif 191 192 #define CONFIG_SYS_FLASH_BR_PRELIM \ 193 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 194 | BR_PS_16 | BR_V) 195 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 196 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 197 198 #define CONFIG_SYS_BR1_PRELIM \ 199 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 200 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 201 202 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 203 #ifdef CONFIG_PHYS_64BIT 204 #define PIXIS_BASE_PHYS 0xfffdf0000ull 205 #else 206 #define PIXIS_BASE_PHYS PIXIS_BASE 207 #endif 208 209 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 210 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 211 212 #define PIXIS_LBMAP_SWITCH 7 213 #define PIXIS_LBMAP_MASK 0xf0 214 #define PIXIS_LBMAP_SHIFT 4 215 #define PIXIS_LBMAP_ALTBANK 0x40 216 217 #define CONFIG_SYS_FLASH_QUIET_TEST 218 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 219 220 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 221 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 222 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 223 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 224 225 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 226 227 #if defined(CONFIG_RAMBOOT_PBL) 228 #define CONFIG_SYS_RAMBOOT 229 #endif 230 231 /* Nand Flash */ 232 #ifdef CONFIG_NAND_FSL_ELBC 233 #define CONFIG_SYS_NAND_BASE 0xffa00000 234 #ifdef CONFIG_PHYS_64BIT 235 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 236 #else 237 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 238 #endif 239 240 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 241 #define CONFIG_SYS_MAX_NAND_DEVICE 1 242 #define CONFIG_CMD_NAND 243 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 244 245 /* NAND flash config */ 246 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 247 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 248 | BR_PS_8 /* Port Size = 8 bit */ \ 249 | BR_MS_FCM /* MSEL = FCM */ \ 250 | BR_V) /* valid */ 251 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 252 | OR_FCM_PGS /* Large Page*/ \ 253 | OR_FCM_CSCT \ 254 | OR_FCM_CST \ 255 | OR_FCM_CHT \ 256 | OR_FCM_SCY_1 \ 257 | OR_FCM_TRLX \ 258 | OR_FCM_EHTR) 259 260 #ifdef CONFIG_NAND 261 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 262 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 263 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 264 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 265 #else 266 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 267 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 268 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 269 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 270 #endif 271 #else 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #endif /* CONFIG_NAND_FSL_ELBC */ 275 276 #define CONFIG_SYS_FLASH_EMPTY_INFO 277 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 278 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 279 280 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 281 #define CONFIG_MISC_INIT_R 282 283 #define CONFIG_HWCONFIG 284 285 /* define to use L1 as initial stack */ 286 #define CONFIG_L1_INIT_RAM 287 #define CONFIG_SYS_INIT_RAM_LOCK 288 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 289 #ifdef CONFIG_PHYS_64BIT 290 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 292 /* The assembler doesn't like typecast */ 293 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 294 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 295 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 296 #else 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 300 #endif 301 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 302 303 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 304 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 305 306 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 307 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 308 309 /* Serial Port - controlled on board with jumper J8 310 * open - index 2 311 * shorted - index 1 312 */ 313 #define CONFIG_CONS_INDEX 1 314 #define CONFIG_SYS_NS16550_SERIAL 315 #define CONFIG_SYS_NS16550_REG_SIZE 1 316 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 317 318 #define CONFIG_SYS_BAUDRATE_TABLE \ 319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 320 321 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 322 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 323 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 324 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 325 326 /* I2C */ 327 #define CONFIG_SYS_I2C 328 #define CONFIG_SYS_I2C_FSL 329 #define CONFIG_SYS_FSL_I2C_SPEED 400000 330 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 331 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 332 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 333 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 334 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 335 336 /* 337 * RapidIO 338 */ 339 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 340 #ifdef CONFIG_PHYS_64BIT 341 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 342 #else 343 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 344 #endif 345 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 346 347 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 348 #ifdef CONFIG_PHYS_64BIT 349 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 350 #else 351 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 352 #endif 353 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 354 355 /* 356 * for slave u-boot IMAGE instored in master memory space, 357 * PHYS must be aligned based on the SIZE 358 */ 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 361 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 362 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 363 /* 364 * for slave UCODE and ENV instored in master memory space, 365 * PHYS must be aligned based on the SIZE 366 */ 367 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 368 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 369 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 370 371 /* slave core release by master*/ 372 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 373 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 374 375 /* 376 * SRIO_PCIE_BOOT - SLAVE 377 */ 378 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 379 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 380 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 381 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 382 #endif 383 384 /* 385 * eSPI - Enhanced SPI 386 */ 387 #define CONFIG_SF_DEFAULT_SPEED 10000000 388 #define CONFIG_SF_DEFAULT_MODE 0 389 390 /* 391 * General PCI 392 * Memory space is mapped 1-1, but I/O space must start from 0. 393 */ 394 395 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 396 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 397 #ifdef CONFIG_PHYS_64BIT 398 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 399 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 400 #else 401 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 402 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 403 #endif 404 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 405 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 406 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 409 #else 410 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 411 #endif 412 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 413 414 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 415 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 416 #ifdef CONFIG_PHYS_64BIT 417 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 418 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 419 #else 420 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 422 #endif 423 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 424 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 425 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 428 #else 429 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 430 #endif 431 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 432 433 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 434 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 435 #ifdef CONFIG_PHYS_64BIT 436 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 437 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 438 #else 439 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 440 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 441 #endif 442 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 443 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 444 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 447 #else 448 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 449 #endif 450 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 451 452 /* controller 4, Base address 203000 */ 453 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 454 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 455 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 456 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 457 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 458 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 459 460 /* Qman/Bman */ 461 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 462 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 463 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 466 #else 467 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 468 #endif 469 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 470 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 471 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 472 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 473 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 474 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 475 CONFIG_SYS_BMAN_CENA_SIZE) 476 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 477 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 478 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 479 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 480 #ifdef CONFIG_PHYS_64BIT 481 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 482 #else 483 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 484 #endif 485 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 486 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 487 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 488 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 489 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 490 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 491 CONFIG_SYS_QMAN_CENA_SIZE) 492 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 493 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 494 495 #define CONFIG_SYS_DPAA_FMAN 496 #define CONFIG_SYS_DPAA_PME 497 /* Default address of microcode for the Linux Fman driver */ 498 #if defined(CONFIG_SPIFLASH) 499 /* 500 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 501 * env, so we got 0x110000. 502 */ 503 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 504 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 505 #elif defined(CONFIG_SDCARD) 506 /* 507 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 508 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 509 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 510 */ 511 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 512 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 513 #elif defined(CONFIG_NAND) 514 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 515 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 516 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 517 /* 518 * Slave has no ucode locally, it can fetch this from remote. When implementing 519 * in two corenet boards, slave's ucode could be stored in master's memory 520 * space, the address can be mapped from slave TLB->slave LAW-> 521 * slave SRIO or PCIE outbound window->master inbound window-> 522 * master LAW->the ucode address in master's memory space. 523 */ 524 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 525 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 526 #else 527 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 528 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 529 #endif 530 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 531 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 532 533 #ifdef CONFIG_SYS_DPAA_FMAN 534 #define CONFIG_FMAN_ENET 535 #define CONFIG_PHYLIB_10G 536 #define CONFIG_PHY_VITESSE 537 #define CONFIG_PHY_TERANETICS 538 #endif 539 540 #ifdef CONFIG_PCI 541 #define CONFIG_PCI_INDIRECT_BRIDGE 542 543 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 544 #endif /* CONFIG_PCI */ 545 546 /* SATA */ 547 #ifdef CONFIG_FSL_SATA_V2 548 #define CONFIG_LIBATA 549 #define CONFIG_FSL_SATA 550 551 #define CONFIG_SYS_SATA_MAX_DEVICE 2 552 #define CONFIG_SATA1 553 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 554 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 555 #define CONFIG_SATA2 556 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 557 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 558 559 #define CONFIG_LBA48 560 #endif 561 562 #ifdef CONFIG_FMAN_ENET 563 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 564 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 565 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 566 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 567 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 568 569 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 570 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 571 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 572 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 573 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 574 575 #define CONFIG_SYS_TBIPA_VALUE 8 576 #define CONFIG_MII /* MII PHY management */ 577 #define CONFIG_ETHPRIME "FM1@DTSEC1" 578 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 579 #endif 580 581 /* 582 * Environment 583 */ 584 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 585 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 586 587 /* 588 * Command line configuration. 589 */ 590 #define CONFIG_CMD_REGINFO 591 592 #ifdef CONFIG_PCI 593 #define CONFIG_CMD_PCI 594 #endif 595 596 /* 597 * USB 598 */ 599 #define CONFIG_HAS_FSL_DR_USB 600 #define CONFIG_HAS_FSL_MPH_USB 601 602 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 603 #define CONFIG_USB_EHCI_FSL 604 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 605 #endif 606 607 #ifdef CONFIG_MMC 608 #define CONFIG_FSL_ESDHC 609 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 610 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 611 #endif 612 613 /* 614 * Miscellaneous configurable options 615 */ 616 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 617 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 618 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 619 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 620 #ifdef CONFIG_CMD_KGDB 621 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 622 #else 623 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 624 #endif 625 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 626 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 627 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 628 629 /* 630 * For booting Linux, the board info and command line data 631 * have to be in the first 64 MB of memory, since this is 632 * the maximum mapped by the Linux kernel during initialization. 633 */ 634 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 635 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 636 637 #ifdef CONFIG_CMD_KGDB 638 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 639 #endif 640 641 /* 642 * Environment Configuration 643 */ 644 #define CONFIG_ROOTPATH "/opt/nfsroot" 645 #define CONFIG_BOOTFILE "uImage" 646 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 647 648 /* default location for tftp and bootm */ 649 #define CONFIG_LOADADDR 1000000 650 651 #ifdef CONFIG_TARGET_P4080DS 652 #define __USB_PHY_TYPE ulpi 653 #else 654 #define __USB_PHY_TYPE utmi 655 #endif 656 657 #define CONFIG_EXTRA_ENV_SETTINGS \ 658 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 659 "bank_intlv=cs0_cs1;" \ 660 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 661 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 662 "netdev=eth0\0" \ 663 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 664 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 665 "tftpflash=tftpboot $loadaddr $uboot && " \ 666 "protect off $ubootaddr +$filesize && " \ 667 "erase $ubootaddr +$filesize && " \ 668 "cp.b $loadaddr $ubootaddr $filesize && " \ 669 "protect on $ubootaddr +$filesize && " \ 670 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 671 "consoledev=ttyS0\0" \ 672 "ramdiskaddr=2000000\0" \ 673 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 674 "fdtaddr=1e00000\0" \ 675 "fdtfile=p4080ds/p4080ds.dtb\0" \ 676 "bdev=sda3\0" 677 678 #define CONFIG_HDBOOT \ 679 "setenv bootargs root=/dev/$bdev rw " \ 680 "console=$consoledev,$baudrate $othbootargs;" \ 681 "tftp $loadaddr $bootfile;" \ 682 "tftp $fdtaddr $fdtfile;" \ 683 "bootm $loadaddr - $fdtaddr" 684 685 #define CONFIG_NFSBOOTCOMMAND \ 686 "setenv bootargs root=/dev/nfs rw " \ 687 "nfsroot=$serverip:$rootpath " \ 688 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 689 "console=$consoledev,$baudrate $othbootargs;" \ 690 "tftp $loadaddr $bootfile;" \ 691 "tftp $fdtaddr $fdtfile;" \ 692 "bootm $loadaddr - $fdtaddr" 693 694 #define CONFIG_RAMBOOTCOMMAND \ 695 "setenv bootargs root=/dev/ram rw " \ 696 "console=$consoledev,$baudrate $othbootargs;" \ 697 "tftp $ramdiskaddr $ramdiskfile;" \ 698 "tftp $loadaddr $bootfile;" \ 699 "tftp $fdtaddr $fdtfile;" \ 700 "bootm $loadaddr $ramdiskaddr $fdtaddr" 701 702 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 703 704 #include <asm/fsl_secure_boot.h> 705 706 #endif /* __CONFIG_H */ 707