1 /* 2 + * Copyright 2014 Freescale Semiconductor, Inc. 3 + * 4 + * SPDX-License-Identifier: GPL-2.0+ 5 + */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 /* 11 * T104x RDB board configuration file 12 */ 13 #include <asm/config_mpc85xx.h> 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 17 #ifndef CONFIG_SECURE_BOOT 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg 19 #else 20 #define CONFIG_SYS_FSL_PBL_PBI \ 21 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg 22 #endif 23 24 #define CONFIG_SPL_FLUSH_IMAGE 25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 26 #define CONFIG_SYS_TEXT_BASE 0x30001000 27 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 28 #define CONFIG_SPL_PAD_TO 0x40000 29 #define CONFIG_SPL_MAX_SIZE 0x28000 30 #ifdef CONFIG_SPL_BUILD 31 #define CONFIG_SPL_SKIP_RELOCATE 32 #define CONFIG_SPL_COMMON_INIT_DDR 33 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 34 #endif 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 38 #ifdef CONFIG_NAND 39 #ifdef CONFIG_SECURE_BOOT 40 #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) 41 /* 42 * HDR would be appended at end of image and copied to DDR along 43 * with U-Boot image. 44 */ 45 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ 46 CONFIG_U_BOOT_HDR_SIZE) 47 #else 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 49 #endif 50 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 51 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 52 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 53 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 54 #ifdef CONFIG_TARGET_T1040RDB 55 #define CONFIG_SYS_FSL_PBL_RCW \ 56 $(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg 57 #endif 58 #ifdef CONFIG_TARGET_T1042RDB_PI 59 #define CONFIG_SYS_FSL_PBL_RCW \ 60 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg 61 #endif 62 #ifdef CONFIG_TARGET_T1042RDB 63 #define CONFIG_SYS_FSL_PBL_RCW \ 64 $(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg 65 #endif 66 #ifdef CONFIG_TARGET_T1040D4RDB 67 #define CONFIG_SYS_FSL_PBL_RCW \ 68 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg 69 #endif 70 #ifdef CONFIG_TARGET_T1042D4RDB 71 #define CONFIG_SYS_FSL_PBL_RCW \ 72 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg 73 #endif 74 #define CONFIG_SPL_NAND_BOOT 75 #endif 76 77 #ifdef CONFIG_SPIFLASH 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 79 #define CONFIG_SPL_SPI_FLASH_MINIMAL 80 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) 81 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) 82 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) 83 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) 84 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 85 #ifndef CONFIG_SPL_BUILD 86 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 87 #endif 88 #ifdef CONFIG_TARGET_T1040RDB 89 #define CONFIG_SYS_FSL_PBL_RCW \ 90 $(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg 91 #endif 92 #ifdef CONFIG_TARGET_T1042RDB_PI 93 #define CONFIG_SYS_FSL_PBL_RCW \ 94 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg 95 #endif 96 #ifdef CONFIG_TARGET_T1042RDB 97 #define CONFIG_SYS_FSL_PBL_RCW \ 98 $(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg 99 #endif 100 #ifdef CONFIG_TARGET_T1040D4RDB 101 #define CONFIG_SYS_FSL_PBL_RCW \ 102 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg 103 #endif 104 #ifdef CONFIG_TARGET_T1042D4RDB 105 #define CONFIG_SYS_FSL_PBL_RCW \ 106 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg 107 #endif 108 #define CONFIG_SPL_SPI_BOOT 109 #endif 110 111 #ifdef CONFIG_SDCARD 112 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC 113 #define CONFIG_SPL_MMC_MINIMAL 114 #define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) 115 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) 116 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) 117 #define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) 118 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" 119 #ifndef CONFIG_SPL_BUILD 120 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 121 #endif 122 #ifdef CONFIG_TARGET_T1040RDB 123 #define CONFIG_SYS_FSL_PBL_RCW \ 124 $(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg 125 #endif 126 #ifdef CONFIG_TARGET_T1042RDB_PI 127 #define CONFIG_SYS_FSL_PBL_RCW \ 128 $(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg 129 #endif 130 #ifdef CONFIG_TARGET_T1042RDB 131 #define CONFIG_SYS_FSL_PBL_RCW \ 132 $(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg 133 #endif 134 #ifdef CONFIG_TARGET_T1040D4RDB 135 #define CONFIG_SYS_FSL_PBL_RCW \ 136 $(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg 137 #endif 138 #ifdef CONFIG_TARGET_T1042D4RDB 139 #define CONFIG_SYS_FSL_PBL_RCW \ 140 $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg 141 #endif 142 #define CONFIG_SPL_MMC_BOOT 143 #endif 144 145 #endif 146 147 /* High Level Configuration Options */ 148 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 149 #define CONFIG_MP /* support multiple processors */ 150 151 /* support deep sleep */ 152 #define CONFIG_DEEP_SLEEP 153 154 #ifndef CONFIG_SYS_TEXT_BASE 155 #define CONFIG_SYS_TEXT_BASE 0xeff40000 156 #endif 157 158 #ifndef CONFIG_RESET_VECTOR_ADDRESS 159 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 160 #endif 161 162 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 163 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 164 #define CONFIG_PCI_INDIRECT_BRIDGE 165 #define CONFIG_PCIE1 /* PCIE controller 1 */ 166 #define CONFIG_PCIE2 /* PCIE controller 2 */ 167 #define CONFIG_PCIE3 /* PCIE controller 3 */ 168 #define CONFIG_PCIE4 /* PCIE controller 4 */ 169 170 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 171 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 172 173 #define CONFIG_ENV_OVERWRITE 174 175 #ifdef CONFIG_MTD_NOR_FLASH 176 #define CONFIG_FLASH_CFI_DRIVER 177 #define CONFIG_SYS_FLASH_CFI 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 179 #endif 180 181 #if defined(CONFIG_SPIFLASH) 182 #define CONFIG_SYS_EXTRA_ENV_RELOC 183 #define CONFIG_ENV_IS_IN_SPI_FLASH 184 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 185 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 186 #define CONFIG_ENV_SECT_SIZE 0x10000 187 #elif defined(CONFIG_SDCARD) 188 #define CONFIG_SYS_EXTRA_ENV_RELOC 189 #define CONFIG_SYS_MMC_ENV_DEV 0 190 #define CONFIG_ENV_SIZE 0x2000 191 #define CONFIG_ENV_OFFSET (512 * 0x800) 192 #elif defined(CONFIG_NAND) 193 #ifdef CONFIG_SECURE_BOOT 194 #define CONFIG_RAMBOOT_NAND 195 #define CONFIG_BOOTSCRIPT_COPY_RAM 196 #endif 197 #define CONFIG_SYS_EXTRA_ENV_RELOC 198 #define CONFIG_ENV_SIZE 0x2000 199 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 200 #else 201 #define CONFIG_ENV_IS_IN_FLASH 202 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 203 #define CONFIG_ENV_SIZE 0x2000 204 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 205 #endif 206 207 #define CONFIG_SYS_CLK_FREQ 100000000 208 #define CONFIG_DDR_CLK_FREQ 66666666 209 210 /* 211 * These can be toggled for performance analysis, otherwise use default. 212 */ 213 #define CONFIG_SYS_CACHE_STASHING 214 #define CONFIG_BACKSIDE_L2_CACHE 215 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 216 #define CONFIG_BTB /* toggle branch predition */ 217 #define CONFIG_DDR_ECC 218 #ifdef CONFIG_DDR_ECC 219 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 220 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 221 #endif 222 223 #define CONFIG_ENABLE_36BIT_PHYS 224 225 #define CONFIG_ADDR_MAP 226 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 227 228 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 229 #define CONFIG_SYS_MEMTEST_END 0x00400000 230 #define CONFIG_SYS_ALT_MEMTEST 231 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 232 233 /* 234 * Config the L3 Cache as L3 SRAM 235 */ 236 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 237 /* 238 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence 239 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address 240 * (CONFIG_SYS_INIT_L3_VADDR) will be different. 241 */ 242 #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 243 #define CONFIG_SYS_L3_SIZE 256 << 10 244 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) 245 #ifdef CONFIG_RAMBOOT_PBL 246 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 247 #endif 248 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 249 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 250 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 251 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 252 253 #define CONFIG_SYS_DCSRBAR 0xf0000000 254 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 255 256 /* 257 * DDR Setup 258 */ 259 #define CONFIG_VERY_BIG_RAM 260 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 261 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 262 263 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 264 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 265 266 #define CONFIG_DDR_SPD 267 268 #define CONFIG_SYS_SPD_BUS_NUM 0 269 #define SPD_EEPROM_ADDRESS 0x51 270 271 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 272 273 /* 274 * IFC Definitions 275 */ 276 #define CONFIG_SYS_FLASH_BASE 0xe8000000 277 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 278 279 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 280 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 281 CSPR_PORT_SIZE_16 | \ 282 CSPR_MSEL_NOR | \ 283 CSPR_V) 284 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 285 286 /* 287 * TDM Definition 288 */ 289 #define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 290 291 /* NOR Flash Timing Params */ 292 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 293 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 294 FTIM0_NOR_TEADC(0x5) | \ 295 FTIM0_NOR_TEAHC(0x5)) 296 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 297 FTIM1_NOR_TRAD_NOR(0x1A) |\ 298 FTIM1_NOR_TSEQRAD_NOR(0x13)) 299 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 300 FTIM2_NOR_TCH(0x4) | \ 301 FTIM2_NOR_TWPH(0x0E) | \ 302 FTIM2_NOR_TWP(0x1c)) 303 #define CONFIG_SYS_NOR_FTIM3 0x0 304 305 #define CONFIG_SYS_FLASH_QUIET_TEST 306 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 307 308 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 309 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 310 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 311 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 312 313 #define CONFIG_SYS_FLASH_EMPTY_INFO 314 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 315 316 /* CPLD on IFC */ 317 #define CPLD_LBMAP_MASK 0x3F 318 #define CPLD_BANK_SEL_MASK 0x07 319 #define CPLD_BANK_OVERRIDE 0x40 320 #define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ 321 #define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ 322 #define CPLD_LBMAP_RESET 0xFF 323 #define CPLD_LBMAP_SHIFT 0x03 324 325 #if defined(CONFIG_TARGET_T1042RDB_PI) 326 #define CPLD_DIU_SEL_DFP 0x80 327 #elif defined(CONFIG_TARGET_T1042D4RDB) 328 #define CPLD_DIU_SEL_DFP 0xc0 329 #endif 330 331 #if defined(CONFIG_TARGET_T1040D4RDB) 332 #define CPLD_INT_MASK_ALL 0xFF 333 #define CPLD_INT_MASK_THERM 0x80 334 #define CPLD_INT_MASK_DVI_DFP 0x40 335 #define CPLD_INT_MASK_QSGMII1 0x20 336 #define CPLD_INT_MASK_QSGMII2 0x10 337 #define CPLD_INT_MASK_SGMI1 0x08 338 #define CPLD_INT_MASK_SGMI2 0x04 339 #define CPLD_INT_MASK_TDMR1 0x02 340 #define CPLD_INT_MASK_TDMR2 0x01 341 #endif 342 343 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 344 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 345 #define CONFIG_SYS_CSPR2_EXT (0xf) 346 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 347 | CSPR_PORT_SIZE_8 \ 348 | CSPR_MSEL_GPCM \ 349 | CSPR_V) 350 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 351 #define CONFIG_SYS_CSOR2 0x0 352 /* CPLD Timing parameters for IFC CS2 */ 353 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 354 FTIM0_GPCM_TEADC(0x0e) | \ 355 FTIM0_GPCM_TEAHC(0x0e)) 356 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 357 FTIM1_GPCM_TRAD(0x1f)) 358 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 359 FTIM2_GPCM_TCH(0x8) | \ 360 FTIM2_GPCM_TWP(0x1f)) 361 #define CONFIG_SYS_CS2_FTIM3 0x0 362 363 /* NAND Flash on IFC */ 364 #define CONFIG_NAND_FSL_IFC 365 #define CONFIG_SYS_NAND_BASE 0xff800000 366 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 367 368 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 369 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 370 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 371 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 372 | CSPR_V) 373 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 374 375 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 376 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 377 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 378 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 379 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 380 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 381 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 382 383 #define CONFIG_SYS_NAND_ONFI_DETECTION 384 385 /* ONFI NAND Flash mode0 Timing Params */ 386 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 387 FTIM0_NAND_TWP(0x18) | \ 388 FTIM0_NAND_TWCHT(0x07) | \ 389 FTIM0_NAND_TWH(0x0a)) 390 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 391 FTIM1_NAND_TWBE(0x39) | \ 392 FTIM1_NAND_TRR(0x0e) | \ 393 FTIM1_NAND_TRP(0x18)) 394 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 395 FTIM2_NAND_TREH(0x0a) | \ 396 FTIM2_NAND_TWHRE(0x1e)) 397 #define CONFIG_SYS_NAND_FTIM3 0x0 398 399 #define CONFIG_SYS_NAND_DDR_LAW 11 400 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 401 #define CONFIG_SYS_MAX_NAND_DEVICE 1 402 #define CONFIG_CMD_NAND 403 404 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 405 406 #if defined(CONFIG_NAND) 407 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 408 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 409 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 410 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 411 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 412 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 413 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 414 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 415 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 416 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 417 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 418 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 419 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 420 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 421 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 422 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 423 #else 424 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 425 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 426 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 427 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 428 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 429 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 430 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 431 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 432 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 433 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 434 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 435 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 436 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 437 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 438 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 439 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 440 #endif 441 442 #ifdef CONFIG_SPL_BUILD 443 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 444 #else 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 446 #endif 447 448 #if defined(CONFIG_RAMBOOT_PBL) 449 #define CONFIG_SYS_RAMBOOT 450 #endif 451 452 #ifdef CONFIG_SYS_FSL_ERRATUM_A008044 453 #if defined(CONFIG_NAND) 454 #define CONFIG_A008044_WORKAROUND 455 #endif 456 #endif 457 458 #define CONFIG_BOARD_EARLY_INIT_R 459 #define CONFIG_MISC_INIT_R 460 461 #define CONFIG_HWCONFIG 462 463 /* define to use L1 as initial stack */ 464 #define CONFIG_L1_INIT_RAM 465 #define CONFIG_SYS_INIT_RAM_LOCK 466 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 467 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 468 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 469 /* The assembler doesn't like typecast */ 470 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 471 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 472 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 473 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 474 475 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 476 GENERATED_GBL_DATA_SIZE) 477 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 478 479 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 480 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 481 482 /* Serial Port - controlled on board with jumper J8 483 * open - index 2 484 * shorted - index 1 485 */ 486 #define CONFIG_CONS_INDEX 1 487 #define CONFIG_SYS_NS16550_SERIAL 488 #define CONFIG_SYS_NS16550_REG_SIZE 1 489 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 490 491 #define CONFIG_SYS_BAUDRATE_TABLE \ 492 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 493 494 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 495 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 496 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 497 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 498 499 #if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) 500 /* Video */ 501 #define CONFIG_FSL_DIU_FB 502 503 #ifdef CONFIG_FSL_DIU_FB 504 #define CONFIG_FSL_DIU_CH7301 505 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) 506 #define CONFIG_VIDEO_LOGO 507 #define CONFIG_VIDEO_BMP_LOGO 508 #endif 509 #endif 510 511 /* I2C */ 512 #define CONFIG_SYS_I2C 513 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 514 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 515 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 516 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 517 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 518 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 519 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 520 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 521 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 522 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 523 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 524 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 525 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 526 527 /* I2C bus multiplexer */ 528 #define I2C_MUX_PCA_ADDR 0x70 529 #define I2C_MUX_CH_DEFAULT 0x8 530 531 #if defined(CONFIG_TARGET_T1042RDB_PI) || \ 532 defined(CONFIG_TARGET_T1040D4RDB) || \ 533 defined(CONFIG_TARGET_T1042D4RDB) 534 /* LDI/DVI Encoder for display */ 535 #define CONFIG_SYS_I2C_LDI_ADDR 0x38 536 #define CONFIG_SYS_I2C_DVI_ADDR 0x75 537 538 /* 539 * RTC configuration 540 */ 541 #define RTC 542 #define CONFIG_RTC_DS1337 1 543 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 544 545 /*DVI encoder*/ 546 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 547 #endif 548 549 /* 550 * eSPI - Enhanced SPI 551 */ 552 #define CONFIG_SPI_FLASH_BAR 553 #define CONFIG_SF_DEFAULT_SPEED 10000000 554 #define CONFIG_SF_DEFAULT_MODE 0 555 #define CONFIG_ENV_SPI_BUS 0 556 #define CONFIG_ENV_SPI_CS 0 557 #define CONFIG_ENV_SPI_MAX_HZ 10000000 558 #define CONFIG_ENV_SPI_MODE 0 559 560 /* 561 * General PCI 562 * Memory space is mapped 1-1, but I/O space must start from 0. 563 */ 564 565 #ifdef CONFIG_PCI 566 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 567 #ifdef CONFIG_PCIE1 568 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 569 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 570 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 571 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 572 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 573 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 574 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 575 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 576 #endif 577 578 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 579 #ifdef CONFIG_PCIE2 580 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 581 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 582 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 583 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 584 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 585 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 586 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 587 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 588 #endif 589 590 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 591 #ifdef CONFIG_PCIE3 592 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 593 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 594 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 595 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 596 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 597 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 598 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 599 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 600 #endif 601 602 /* controller 4, Base address 203000 */ 603 #ifdef CONFIG_PCIE4 604 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 605 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 606 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 607 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 608 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 609 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 610 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 611 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 612 #endif 613 614 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 615 #endif /* CONFIG_PCI */ 616 617 /* SATA */ 618 #define CONFIG_FSL_SATA_V2 619 #ifdef CONFIG_FSL_SATA_V2 620 #define CONFIG_LIBATA 621 #define CONFIG_FSL_SATA 622 623 #define CONFIG_SYS_SATA_MAX_DEVICE 1 624 #define CONFIG_SATA1 625 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 626 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 627 628 #define CONFIG_LBA48 629 #endif 630 631 /* 632 * USB 633 */ 634 #define CONFIG_HAS_FSL_DR_USB 635 636 #ifdef CONFIG_HAS_FSL_DR_USB 637 #ifdef CONFIG_USB_EHCI_HCD 638 #define CONFIG_USB_EHCI_FSL 639 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 640 #endif 641 #endif 642 643 #ifdef CONFIG_MMC 644 #define CONFIG_FSL_ESDHC 645 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 646 #endif 647 648 /* Qman/Bman */ 649 #ifndef CONFIG_NOBQFMAN 650 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 651 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 652 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 653 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 654 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 655 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 656 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 657 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 658 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 659 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 660 CONFIG_SYS_BMAN_CENA_SIZE) 661 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 662 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 663 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 664 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 665 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 666 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 667 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 668 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 669 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 670 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 671 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 672 CONFIG_SYS_QMAN_CENA_SIZE) 673 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 674 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 675 676 #define CONFIG_SYS_DPAA_FMAN 677 #define CONFIG_SYS_DPAA_PME 678 679 #define CONFIG_QE 680 #define CONFIG_U_QE 681 682 /* Default address of microcode for the Linux Fman driver */ 683 #if defined(CONFIG_SPIFLASH) 684 /* 685 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 686 * env, so we got 0x110000. 687 */ 688 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 689 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 690 #elif defined(CONFIG_SDCARD) 691 /* 692 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 693 * about 1MB (2048 blocks), Env is stored after the image, and the env size is 694 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. 695 */ 696 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 697 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) 698 #elif defined(CONFIG_NAND) 699 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 700 #define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 701 #else 702 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 703 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 704 #endif 705 706 #if defined(CONFIG_SPIFLASH) 707 #define CONFIG_SYS_QE_FW_ADDR 0x130000 708 #elif defined(CONFIG_SDCARD) 709 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) 710 #elif defined(CONFIG_NAND) 711 #define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 712 #else 713 #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 714 #endif 715 716 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 717 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 718 #endif /* CONFIG_NOBQFMAN */ 719 720 #ifdef CONFIG_SYS_DPAA_FMAN 721 #define CONFIG_FMAN_ENET 722 #define CONFIG_PHY_VITESSE 723 #define CONFIG_PHY_REALTEK 724 #endif 725 726 #ifdef CONFIG_FMAN_ENET 727 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) 728 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 729 #elif defined(CONFIG_TARGET_T1040D4RDB) 730 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 731 #elif defined(CONFIG_TARGET_T1042D4RDB) 732 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 733 #define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 734 #define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 735 #endif 736 737 #if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) 738 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 739 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 740 #else 741 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 742 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 743 #endif 744 745 /* Enable VSC9953 L2 Switch driver on T1040 SoC */ 746 #if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) 747 #define CONFIG_VSC9953 748 #ifdef CONFIG_TARGET_T1040RDB 749 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 750 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 751 #else 752 #define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 753 #define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c 754 #endif 755 #endif 756 757 #define CONFIG_MII /* MII PHY management */ 758 #define CONFIG_ETHPRIME "FM1@DTSEC4" 759 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 760 #endif 761 762 /* 763 * Environment 764 */ 765 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 766 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 767 768 /* 769 * Command line configuration. 770 */ 771 #define CONFIG_CMD_REGINFO 772 773 #ifdef CONFIG_PCI 774 #define CONFIG_CMD_PCI 775 #endif 776 777 /* 778 * Miscellaneous configurable options 779 */ 780 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 781 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 782 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 783 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 784 #ifdef CONFIG_CMD_KGDB 785 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 786 #else 787 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 788 #endif 789 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 790 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 791 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 792 793 /* 794 * For booting Linux, the board info and command line data 795 * have to be in the first 64 MB of memory, since this is 796 * the maximum mapped by the Linux kernel during initialization. 797 */ 798 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 799 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 800 801 #ifdef CONFIG_CMD_KGDB 802 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 803 #endif 804 805 /* 806 * Dynamic MTD Partition support with mtdparts 807 */ 808 #ifdef CONFIG_MTD_NOR_FLASH 809 #define CONFIG_MTD_DEVICE 810 #define CONFIG_MTD_PARTITIONS 811 #define CONFIG_FLASH_CFI_MTD 812 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \ 813 "spi0=spife110000.0" 814 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \ 815 "128k(dtb),96m(fs),-(user);"\ 816 "fff800000.flash:2m(uboot),9m(kernel),"\ 817 "128k(dtb),96m(fs),-(user);spife110000.0:" \ 818 "2m(uboot),9m(kernel),128k(dtb),-(user)" 819 #endif 820 821 /* 822 * Environment Configuration 823 */ 824 #define CONFIG_ROOTPATH "/opt/nfsroot" 825 #define CONFIG_BOOTFILE "uImage" 826 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 827 828 /* default location for tftp and bootm */ 829 #define CONFIG_LOADADDR 1000000 830 831 #define __USB_PHY_TYPE utmi 832 #define RAMDISKFILE "t104xrdb/ramdisk.uboot" 833 834 #ifdef CONFIG_TARGET_T1040RDB 835 #define FDTFILE "t1040rdb/t1040rdb.dtb" 836 #elif defined(CONFIG_TARGET_T1042RDB_PI) 837 #define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" 838 #elif defined(CONFIG_TARGET_T1042RDB) 839 #define FDTFILE "t1042rdb/t1042rdb.dtb" 840 #elif defined(CONFIG_TARGET_T1040D4RDB) 841 #define FDTFILE "t1042rdb/t1040d4rdb.dtb" 842 #elif defined(CONFIG_TARGET_T1042D4RDB) 843 #define FDTFILE "t1042rdb/t1042d4rdb.dtb" 844 #endif 845 846 #ifdef CONFIG_FSL_DIU_FB 847 #define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" 848 #else 849 #define DIU_ENVIRONMENT 850 #endif 851 852 #define CONFIG_EXTRA_ENV_SETTINGS \ 853 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 854 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 855 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 856 "netdev=eth0\0" \ 857 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ 858 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 859 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 860 "tftpflash=tftpboot $loadaddr $uboot && " \ 861 "protect off $ubootaddr +$filesize && " \ 862 "erase $ubootaddr +$filesize && " \ 863 "cp.b $loadaddr $ubootaddr $filesize && " \ 864 "protect on $ubootaddr +$filesize && " \ 865 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 866 "consoledev=ttyS0\0" \ 867 "ramdiskaddr=2000000\0" \ 868 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ 869 "fdtaddr=1e00000\0" \ 870 "fdtfile=" __stringify(FDTFILE) "\0" \ 871 "bdev=sda3\0" 872 873 #define CONFIG_LINUX \ 874 "setenv bootargs root=/dev/ram rw " \ 875 "console=$consoledev,$baudrate $othbootargs;" \ 876 "setenv ramdiskaddr 0x02000000;" \ 877 "setenv fdtaddr 0x00c00000;" \ 878 "setenv loadaddr 0x1000000;" \ 879 "bootm $loadaddr $ramdiskaddr $fdtaddr" 880 881 #define CONFIG_HDBOOT \ 882 "setenv bootargs root=/dev/$bdev rw " \ 883 "console=$consoledev,$baudrate $othbootargs;" \ 884 "tftp $loadaddr $bootfile;" \ 885 "tftp $fdtaddr $fdtfile;" \ 886 "bootm $loadaddr - $fdtaddr" 887 888 #define CONFIG_NFSBOOTCOMMAND \ 889 "setenv bootargs root=/dev/nfs rw " \ 890 "nfsroot=$serverip:$rootpath " \ 891 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 892 "console=$consoledev,$baudrate $othbootargs;" \ 893 "tftp $loadaddr $bootfile;" \ 894 "tftp $fdtaddr $fdtfile;" \ 895 "bootm $loadaddr - $fdtaddr" 896 897 #define CONFIG_RAMBOOTCOMMAND \ 898 "setenv bootargs root=/dev/ram rw " \ 899 "console=$consoledev,$baudrate $othbootargs;" \ 900 "tftp $ramdiskaddr $ramdiskfile;" \ 901 "tftp $loadaddr $bootfile;" \ 902 "tftp $fdtaddr $fdtfile;" \ 903 "bootm $loadaddr $ramdiskaddr $fdtaddr" 904 905 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 906 907 #include <asm/fsl_secure_boot.h> 908 909 #endif /* __CONFIG_H */ 910