| 42de214f | 04-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "Print newline after hex address in aarch64 el3_panic function" into integration |
| 805f22ba | 16-Feb-2021 |
Pali Rohár <pali@kernel.org> |
Print newline after hex address in aarch64 el3_panic function
Make the aarch64's el3_panic() function print a newline character after
PC address, otherwise the output can get mangled in one line wit
Print newline after hex address in aarch64 el3_panic function
Make the aarch64's el3_panic() function print a newline character after
PC address, otherwise the output can get mangled in one line with output
from other firmware. Here is an example of how the output of el3_panic()
got mangled with Linux' console output:
ERROR: Unhandled External Abort received on 0x80000001 at EL3!
ERROR: exception reason=1 syndrome=0x92000210
PANIC at PC : 0x0000000004027400[13438.473133] rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
[13438.479255] rcu: 1-...0: (4 ticks this GP) idle=35e/1/0x4000000000000000 softirq=146459/146459 fqs=2625
The aarch32 version of this function already does this.
Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9f0d032c6cd1e2be7a1837f9c8e8244d30633993
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| 893716d7 | 03-Mar-2021 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge "docs: Add GIC600AE FVP model version information" into integration |
| 88ddb601 | 03-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "mediatek: mt8192: Add MPU Support for SCP/PCIe" into integration |
| 258f6a2d | 03-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I4bd4612a,Id13a06d4,I0ea7f610,Ie6a7063b into integration
* changes:
mediatek: mt8192: Add Vcore DVFS driver
mediatek: mt8192: Add SPM suspend driver
mediatek: mt8192: supports mc
Merge changes I4bd4612a,Id13a06d4,I0ea7f610,Ie6a7063b into integration
* changes:
mediatek: mt8192: Add Vcore DVFS driver
mediatek: mt8192: Add SPM suspend driver
mediatek: mt8192: supports mcusys off when system suspend
mediatek: mt8192: Add lpm driver
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| a564bdc5 | 06-Jan-2021 |
Xi Chen <xixi.chen@mediatek.com> |
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
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| f3febcca | 14-Dec-2020 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add Vcore DVFS driver
Change-Id: I4bd4612a7c7727a5be70957ae940e5f51c7ca5e6
Signed-off-by: Roger Lu <roger.lu@mediatek.com> |
| ebb44440 | 03-Jan-2021 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add SPM suspend driver
Supports dram/mainpll/26m off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: Id13a06d4132f00fb60066de75920ecac18306e32 |
| df60025f | 03-Jan-2021 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: supports mcusys off when system suspend
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I0ea7f61085ea9ba26c580107ef0cb9940a25f5e2 |
| cab49199 | 14-Dec-2020 |
Roger Lu <roger.lu@mediatek.com> |
mediatek: mt8192: Add lpm driver
Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.
Change-Id: Ie6a7063b666cf338
mediatek: mt8192: Add lpm driver
Low Power Management (LPM) helps find a suitable configuration
for letting system entering idle or suspend with the most
resources off.
Change-Id: Ie6a7063b666cf338cff5bc972c9025b26de482eb
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
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| 1b7e5ca9 | 03-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d,
plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices
Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.
Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe
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| c0f0ab53 | 02-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fdts: enable virtIO P9 device for morello fvp platform" into integration |
| 8ef06b6c | 02-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu CPU lib" into integration |
| 0cd5d1d1 | 02-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "lib/extensions/ras: fix bug of binary search" into integration |
| 4bf98b27 | 12-Feb-2021 |
sah01 <sahil@arm.com> |
fdts: enable virtIO P9 device for morello fvp platform
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: Ic11d739c0bf2076354716cc06fbe25e9000a21e7 |
| ef4c1e19 | 02-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "Enable v8.6 AMU enhancements (FEAT_AMUv1p1)" into integration |
| 4d9b9b23 | 25-Feb-2021 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f
plat: xilinx: Add timeout while waiting for IPI Ack
Return timeout error if, IPI is not acked in specified timeout.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Change-Id: I27be3d4d4eb5bc57f6a84c839e2586278c0aec19
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| aaabf978 | 15-Oct-2020 |
johpow01 <john.powell@arm.com> |
Add Makalu CPU lib
Add basic support for Makalu CPU.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I4e85d425eedea499adf585eb8ab548931185043d |
| 174551d5 | 01-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "trng-svc" into integration
* changes:
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
plat/arm: juno: Condition Juno entropy source with CRC instructio
Merge changes from topic "trng-svc" into integration
* changes:
plat/arm: juno: Use TRNG entropy source for SMCCC TRNG interface
plat/arm: juno: Condition Juno entropy source with CRC instructions
show more ...
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| 051906bb | 01-Mar-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.
Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe
docs: Add GIC600AE FVP model version information
Added GIC600AE FVP model version information.
Change-Id: I15d25fbdb8e09900976d5993032ec049f8db79f2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 206fa996 | 01-Mar-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
qemu/qemu_sbsa: fix memory type of secure NOR flash
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.or
qemu/qemu_sbsa: fix memory type of secure NOR flash
This commit fixes the wrong memory type, secure NOR flash
shall be mapped as MT_DEVICE.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I9c9ed51675d84ded675bb56b2e4ec7a08184c602
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| cf952b0f | 02-Feb-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
qemu/qemu_sbsa: spm_mm supports 512 cores
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also incr
qemu/qemu_sbsa: spm_mm supports 512 cores
sbsa-ref in QEMU may create up to 512 cores.
This commit prepares the MP information to support 512 cores.
The number of xlat tables for spm_mm is also increased.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I2788eaf6d14e188e9b5d1102d359b2899e02df7c
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| 0aa70f4c | 25-Feb-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "plat/qemu: trigger reboot with secure pl061" into integration |
| 873d4241 | 02-Oct-2020 |
johpow01 <john.powell@arm.com> |
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3
Enable v8.6 AMU enhancements (FEAT_AMUv1p1)
ARMv8.6 adds virtual offset registers to support virtualization of the
event counters in EL1 and EL0. This patch enables support for this
feature in EL3 firmware.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
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| 8909fa9b | 25-Feb-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mappin
Merge changes I23f600b5,Icf9ffdf2,Iee7a51d1,I99afc312,I4bf8e8c0, ... into integration
* changes:
plat/marvell/armada: cleanup MSS SRAM if used for copy
plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stage
plat/marvell/armada/common/mss: use MSS SRAM in secure mode
include/drivers/marvell/mochi: add detection of secure mode
plat/marvell: fix SPD handling in dram port
marvell: drivers: move XOR0/1 DIOB from WIN 0 to 1
drivers/marvell/mochi: add support for cn913x in PCIe EP mode
drivers/marvell/mochi: add missing stream IDs configurations
plat/marvell/armada/a8k: support HW RNG by SMC
drivers/rambus: add TRNG-IP-76 driver
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