1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x400000 19 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20 #define MTK_DEV_RNG1_SIZE 0xa110000 21 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22 #define MTK_DEV_RNG2_SIZE 0x600000 23 24 25 /******************************************************************************* 26 * UART related constants 27 ******************************************************************************/ 28 #define UART0_BASE (IO_PHYS + 0x01001100) 29 #define UART1_BASE (IO_PHYS + 0x01001200) 30 31 #define UART_BAUDRATE 115200 32 33 /******************************************************************************* 34 * System counter frequency related constants 35 ******************************************************************************/ 36 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 37 #define SYS_COUNTER_FREQ_IN_MHZ 13 38 39 /******************************************************************************* 40 * GIC-600 & interrupt handling related constants 41 ******************************************************************************/ 42 /* Base MTK_platform compatible GIC memory map */ 43 #define BASE_GICD_BASE MT_GIC_BASE 44 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 45 46 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 47 #define CIRQ_REG_NUM 23 48 #define CIRQ_IRQ_NUM 730 49 #define CIRQ_SPI_START 96 50 #define MD_WDT_IRQ_BIT_ID 141 51 /******************************************************************************* 52 * Platform binary types for linking 53 ******************************************************************************/ 54 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 55 #define PLATFORM_LINKER_ARCH aarch64 56 57 /******************************************************************************* 58 * Generic platform constants 59 ******************************************************************************/ 60 #define PLATFORM_STACK_SIZE 0x800 61 62 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 63 64 #define PLAT_MAX_PWR_LVL U(3) 65 #define PLAT_MAX_RET_STATE U(1) 66 #define PLAT_MAX_OFF_STATE U(9) 67 68 #define PLATFORM_SYSTEM_COUNT U(1) 69 #define PLATFORM_MCUSYS_COUNT U(1) 70 #define PLATFORM_CLUSTER_COUNT U(1) 71 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 72 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 73 74 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 75 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 76 77 #define SOC_CHIP_ID U(0x8195) 78 79 /******************************************************************************* 80 * Platform memory map related constants 81 ******************************************************************************/ 82 #define TZRAM_BASE 0x54600000 83 #define TZRAM_SIZE 0x00030000 84 85 /******************************************************************************* 86 * BL31 specific defines. 87 ******************************************************************************/ 88 /* 89 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 90 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 91 * little space for growth. 92 */ 93 #define BL31_BASE (TZRAM_BASE + 0x1000) 94 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 95 96 /******************************************************************************* 97 * Platform specific page table and MMU setup constants 98 ******************************************************************************/ 99 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 100 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 101 #define MAX_XLAT_TABLES 16 102 #define MAX_MMAP_REGIONS 16 103 104 /******************************************************************************* 105 * Declarations and constants to access the mailboxes safely. Each mailbox is 106 * aligned on the biggest cache line size in the platform. This is known only 107 * to the platform as it might have a combination of integrated and external 108 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 109 * line at any cache level. They could belong to different cpus/clusters & 110 * get written while being protected by different locks causing corruption of 111 * a valid mailbox address. 112 ******************************************************************************/ 113 #define CACHE_WRITEBACK_SHIFT 6 114 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 115 #endif /* PLATFORM_DEF_H */ 116