1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x400000 19 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20 #define MTK_DEV_RNG1_SIZE 0xa110000 21 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22 #define MTK_DEV_RNG2_SIZE 0x600000 23 #define MTK_MCDI_SRAM_BASE 0x11B000 24 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 25 26 #define SPM_BASE (IO_PHYS + 0x00006000) 27 28 /******************************************************************************* 29 * GPIO related constants 30 ******************************************************************************/ 31 #define GPIO_BASE (IO_PHYS + 0x00005000) 32 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 33 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 34 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 35 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 36 #define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000) 37 #define IOCFG_TL_BASE (IO_PHYS + 0x01F40000) 38 39 /******************************************************************************* 40 * UART related constants 41 ******************************************************************************/ 42 #define UART0_BASE (IO_PHYS + 0x01001100) 43 #define UART1_BASE (IO_PHYS + 0x01001200) 44 45 #define UART_BAUDRATE 115200 46 47 /******************************************************************************* 48 * System counter frequency related constants 49 ******************************************************************************/ 50 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 51 #define SYS_COUNTER_FREQ_IN_MHZ 13 52 53 /******************************************************************************* 54 * GIC-600 & interrupt handling related constants 55 ******************************************************************************/ 56 /* Base MTK_platform compatible GIC memory map */ 57 #define BASE_GICD_BASE MT_GIC_BASE 58 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 59 60 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 61 #define CIRQ_REG_NUM 23 62 #define CIRQ_IRQ_NUM 730 63 #define CIRQ_SPI_START 96 64 #define MD_WDT_IRQ_BIT_ID 141 65 /******************************************************************************* 66 * Platform binary types for linking 67 ******************************************************************************/ 68 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 69 #define PLATFORM_LINKER_ARCH aarch64 70 71 /******************************************************************************* 72 * Generic platform constants 73 ******************************************************************************/ 74 #define PLATFORM_STACK_SIZE 0x800 75 76 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 77 78 #define PLAT_MAX_PWR_LVL U(3) 79 #define PLAT_MAX_RET_STATE U(1) 80 #define PLAT_MAX_OFF_STATE U(9) 81 82 #define PLATFORM_SYSTEM_COUNT U(1) 83 #define PLATFORM_MCUSYS_COUNT U(1) 84 #define PLATFORM_CLUSTER_COUNT U(1) 85 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 86 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 87 88 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 89 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 90 91 #define SOC_CHIP_ID U(0x8195) 92 93 /******************************************************************************* 94 * Platform memory map related constants 95 ******************************************************************************/ 96 #define TZRAM_BASE 0x54600000 97 #define TZRAM_SIZE 0x00030000 98 99 /******************************************************************************* 100 * BL31 specific defines. 101 ******************************************************************************/ 102 /* 103 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 104 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 105 * little space for growth. 106 */ 107 #define BL31_BASE (TZRAM_BASE + 0x1000) 108 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 109 110 /******************************************************************************* 111 * Platform specific page table and MMU setup constants 112 ******************************************************************************/ 113 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 114 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 115 #define MAX_XLAT_TABLES 16 116 #define MAX_MMAP_REGIONS 16 117 118 /******************************************************************************* 119 * Declarations and constants to access the mailboxes safely. Each mailbox is 120 * aligned on the biggest cache line size in the platform. This is known only 121 * to the platform as it might have a combination of integrated and external 122 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 123 * line at any cache level. They could belong to different cpus/clusters & 124 * get written while being protected by different locks causing corruption of 125 * a valid mailbox address. 126 ******************************************************************************/ 127 #define CACHE_WRITEBACK_SHIFT 6 128 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 129 #endif /* PLATFORM_DEF_H */ 130