1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x400000 19 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20 #define MTK_DEV_RNG1_SIZE 0xa110000 21 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22 #define MTK_DEV_RNG2_SIZE 0x600000 23 #define MTK_MCDI_SRAM_BASE 0x11B000 24 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 25 26 #define SPM_BASE (IO_PHYS + 0x00006000) 27 28 /******************************************************************************* 29 * UART related constants 30 ******************************************************************************/ 31 #define UART0_BASE (IO_PHYS + 0x01001100) 32 #define UART1_BASE (IO_PHYS + 0x01001200) 33 34 #define UART_BAUDRATE 115200 35 36 /******************************************************************************* 37 * System counter frequency related constants 38 ******************************************************************************/ 39 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 40 #define SYS_COUNTER_FREQ_IN_MHZ 13 41 42 /******************************************************************************* 43 * GIC-600 & interrupt handling related constants 44 ******************************************************************************/ 45 /* Base MTK_platform compatible GIC memory map */ 46 #define BASE_GICD_BASE MT_GIC_BASE 47 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 48 49 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 50 #define CIRQ_REG_NUM 23 51 #define CIRQ_IRQ_NUM 730 52 #define CIRQ_SPI_START 96 53 #define MD_WDT_IRQ_BIT_ID 141 54 /******************************************************************************* 55 * Platform binary types for linking 56 ******************************************************************************/ 57 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 58 #define PLATFORM_LINKER_ARCH aarch64 59 60 /******************************************************************************* 61 * Generic platform constants 62 ******************************************************************************/ 63 #define PLATFORM_STACK_SIZE 0x800 64 65 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 66 67 #define PLAT_MAX_PWR_LVL U(3) 68 #define PLAT_MAX_RET_STATE U(1) 69 #define PLAT_MAX_OFF_STATE U(9) 70 71 #define PLATFORM_SYSTEM_COUNT U(1) 72 #define PLATFORM_MCUSYS_COUNT U(1) 73 #define PLATFORM_CLUSTER_COUNT U(1) 74 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 75 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 76 77 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 78 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 79 80 #define SOC_CHIP_ID U(0x8195) 81 82 /******************************************************************************* 83 * Platform memory map related constants 84 ******************************************************************************/ 85 #define TZRAM_BASE 0x54600000 86 #define TZRAM_SIZE 0x00030000 87 88 /******************************************************************************* 89 * BL31 specific defines. 90 ******************************************************************************/ 91 /* 92 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 93 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 94 * little space for growth. 95 */ 96 #define BL31_BASE (TZRAM_BASE + 0x1000) 97 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 98 99 /******************************************************************************* 100 * Platform specific page table and MMU setup constants 101 ******************************************************************************/ 102 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 103 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 104 #define MAX_XLAT_TABLES 16 105 #define MAX_MMAP_REGIONS 16 106 107 /******************************************************************************* 108 * Declarations and constants to access the mailboxes safely. Each mailbox is 109 * aligned on the biggest cache line size in the platform. This is known only 110 * to the platform as it might have a combination of integrated and external 111 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 112 * line at any cache level. They could belong to different cpus/clusters & 113 * get written while being protected by different locks causing corruption of 114 * a valid mailbox address. 115 ******************************************************************************/ 116 #define CACHE_WRITEBACK_SHIFT 6 117 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 118 #endif /* PLATFORM_DEF_H */ 119