1 /* 2 * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #define PLAT_PRIMARY_CPU 0x0 11 12 #define MT_GIC_BASE (0x0C000000) 13 #define MCUCFG_BASE (0x0C530000) 14 #define IO_PHYS (0x10000000) 15 16 /* Aggregate of all devices for MMU mapping */ 17 #define MTK_DEV_RNG0_BASE IO_PHYS 18 #define MTK_DEV_RNG0_SIZE 0x400000 19 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) 20 #define MTK_DEV_RNG1_SIZE 0xa110000 21 #define MTK_DEV_RNG2_BASE MT_GIC_BASE 22 #define MTK_DEV_RNG2_SIZE 0x600000 23 24 #define SPM_BASE (IO_PHYS + 0x00006000) 25 26 /******************************************************************************* 27 * UART related constants 28 ******************************************************************************/ 29 #define UART0_BASE (IO_PHYS + 0x01001100) 30 #define UART1_BASE (IO_PHYS + 0x01001200) 31 32 #define UART_BAUDRATE 115200 33 34 /******************************************************************************* 35 * System counter frequency related constants 36 ******************************************************************************/ 37 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 38 #define SYS_COUNTER_FREQ_IN_MHZ 13 39 40 /******************************************************************************* 41 * GIC-600 & interrupt handling related constants 42 ******************************************************************************/ 43 /* Base MTK_platform compatible GIC memory map */ 44 #define BASE_GICD_BASE MT_GIC_BASE 45 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 46 47 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 48 #define CIRQ_REG_NUM 23 49 #define CIRQ_IRQ_NUM 730 50 #define CIRQ_SPI_START 96 51 #define MD_WDT_IRQ_BIT_ID 141 52 /******************************************************************************* 53 * Platform binary types for linking 54 ******************************************************************************/ 55 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 56 #define PLATFORM_LINKER_ARCH aarch64 57 58 /******************************************************************************* 59 * Generic platform constants 60 ******************************************************************************/ 61 #define PLATFORM_STACK_SIZE 0x800 62 63 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 64 65 #define PLAT_MAX_PWR_LVL U(3) 66 #define PLAT_MAX_RET_STATE U(1) 67 #define PLAT_MAX_OFF_STATE U(9) 68 69 #define PLATFORM_SYSTEM_COUNT U(1) 70 #define PLATFORM_MCUSYS_COUNT U(1) 71 #define PLATFORM_CLUSTER_COUNT U(1) 72 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 73 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 74 75 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 76 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 77 78 #define SOC_CHIP_ID U(0x8195) 79 80 /******************************************************************************* 81 * Platform memory map related constants 82 ******************************************************************************/ 83 #define TZRAM_BASE 0x54600000 84 #define TZRAM_SIZE 0x00030000 85 86 /******************************************************************************* 87 * BL31 specific defines. 88 ******************************************************************************/ 89 /* 90 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 91 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 92 * little space for growth. 93 */ 94 #define BL31_BASE (TZRAM_BASE + 0x1000) 95 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 96 97 /******************************************************************************* 98 * Platform specific page table and MMU setup constants 99 ******************************************************************************/ 100 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 101 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 102 #define MAX_XLAT_TABLES 16 103 #define MAX_MMAP_REGIONS 16 104 105 /******************************************************************************* 106 * Declarations and constants to access the mailboxes safely. Each mailbox is 107 * aligned on the biggest cache line size in the platform. This is known only 108 * to the platform as it might have a combination of integrated and external 109 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 110 * line at any cache level. They could belong to different cpus/clusters & 111 * get written while being protected by different locks causing corruption of 112 * a valid mailbox address. 113 ******************************************************************************/ 114 #define CACHE_WRITEBACK_SHIFT 6 115 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 116 #endif /* PLATFORM_DEF_H */ 117