1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 11 #define PLAT_PRIMARY_CPU 0x0 12 13 #define MT_GIC_BASE 0x0c000000 14 #define PLAT_MT_CCI_BASE 0x0c500000 15 #define MCUCFG_BASE 0x0c530000 16 17 #define IO_PHYS 0x10000000 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE IO_PHYS 21 #define MTK_DEV_RNG0_SIZE 0x10000000 22 #define MTK_DEV_RNG1_BASE (IO_PHYS + 0x10000000) 23 #define MTK_DEV_RNG1_SIZE 0x10000000 24 #define MTK_DEV_RNG2_BASE 0x0c000000 25 #define MTK_DEV_RNG2_SIZE 0x600000 26 #define MTK_MCDI_SRAM_BASE 0x11B000 27 #define MTK_MCDI_SRAM_MAP_SIZE 0x1000 28 29 #define TOPCKGEN_BASE (IO_PHYS + 0x00000000) 30 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 31 #define GPIO_BASE (IO_PHYS + 0x00005000) 32 #define SPM_BASE (IO_PHYS + 0x00006000) 33 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 34 #define DVFSRC_BASE (IO_PHYS + 0x00012000) 35 #define PMIC_WRAP_BASE (IO_PHYS + 0x00026000) 36 #define EMI_BASE (IO_PHYS + 0x00219000) 37 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 38 #define SSPM_MBOX_BASE (IO_PHYS + 0x00480000) 39 #define IOCFG_RM_BASE (IO_PHYS + 0x01C20000) 40 #define IOCFG_BM_BASE (IO_PHYS + 0x01D10000) 41 #define IOCFG_BL_BASE (IO_PHYS + 0x01D30000) 42 #define IOCFG_BR_BASE (IO_PHYS + 0x01D40000) 43 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 44 #define IOCFG_LB_BASE (IO_PHYS + 0x01E70000) 45 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 46 #define IOCFG_LT_BASE (IO_PHYS + 0x01F20000) 47 #define IOCFG_TL_BASE (IO_PHYS + 0x01F30000) 48 #define MMSYS_BASE (IO_PHYS + 0x04000000) 49 /******************************************************************************* 50 * UART related constants 51 ******************************************************************************/ 52 #define UART0_BASE (IO_PHYS + 0x01002000) 53 #define UART1_BASE (IO_PHYS + 0x01003000) 54 55 #define UART_BAUDRATE 115200 56 57 /******************************************************************************* 58 * System counter frequency related constants 59 ******************************************************************************/ 60 #define SYS_COUNTER_FREQ_IN_TICKS 13000000 61 #define SYS_COUNTER_FREQ_IN_MHZ 13 62 63 /******************************************************************************* 64 * GIC-600 & interrupt handling related constants 65 ******************************************************************************/ 66 67 /* Base MTK_platform compatible GIC memory map */ 68 #define BASE_GICD_BASE MT_GIC_BASE 69 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 70 71 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 72 #define CIRQ_REG_NUM 14 73 #define CIRQ_IRQ_NUM 439 74 #define CIRQ_SPI_START 64 75 #define MD_WDT_IRQ_BIT_ID 110 76 77 /******************************************************************************* 78 * Platform binary types for linking 79 ******************************************************************************/ 80 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 81 #define PLATFORM_LINKER_ARCH aarch64 82 83 /******************************************************************************* 84 * Generic platform constants 85 ******************************************************************************/ 86 #define PLATFORM_STACK_SIZE 0x800 87 88 #define PLAT_MAX_PWR_LVL U(3) 89 #define PLAT_MAX_RET_STATE U(1) 90 #define PLAT_MAX_OFF_STATE U(9) 91 92 #define PLATFORM_SYSTEM_COUNT U(1) 93 #define PLATFORM_MCUSYS_COUNT U(1) 94 #define PLATFORM_CLUSTER_COUNT U(1) 95 #define PLATFORM_CLUSTER0_CORE_COUNT U(8) 96 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 97 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(8) 98 99 #define SOC_CHIP_ID U(0x8192) 100 101 /******************************************************************************* 102 * Platform memory map related constants 103 ******************************************************************************/ 104 #define TZRAM_BASE 0x54600000 105 #define TZRAM_SIZE 0x00030000 106 107 /******************************************************************************* 108 * BL31 specific defines. 109 ******************************************************************************/ 110 /* 111 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 112 * present). BL31_BASE is calculated using the current BL31 debug size plus a 113 * little space for growth. 114 */ 115 #define BL31_BASE (TZRAM_BASE + 0x1000) 116 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 117 118 /******************************************************************************* 119 * Platform specific page table and MMU setup constants 120 ******************************************************************************/ 121 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 122 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 123 #define MAX_XLAT_TABLES 16 124 #define MAX_MMAP_REGIONS 16 125 126 /******************************************************************************* 127 * Declarations and constants to access the mailboxes safely. Each mailbox is 128 * aligned on the biggest cache line size in the platform. This is known only 129 * to the platform as it might have a combination of integrated and external 130 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 131 * line at any cache level. They could belong to different cpus/clusters & 132 * get written while being protected by different locks causing corruption of 133 * a valid mailbox address. 134 ******************************************************************************/ 135 #define CACHE_WRITEBACK_SHIFT 6 136 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 137 #endif /* PLATFORM_DEF_H */ 138