Merge changes from topics "ck/tf-a-build-fixes", "ck/tf-a-romlib-build-fixes" into integration

* changes:
build(romlib): don't timestamp generated wrappers
build(romlib): de-duplicate ROMLib wra

Merge changes from topics "ck/tf-a-build-fixes", "ck/tf-a-romlib-build-fixes" into integration

* changes:
build(romlib): don't timestamp generated wrappers
build(romlib): de-duplicate ROMLib wrapper sources
fix(build): fix incorrectly-escaped armlink preprocessor definitions

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Merge "fix(nuvoton): fix MMU mapping settings" into integration

Merge "feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs" into integration

fix(gpt): fix RME GPT library bug

This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.

Change-Id: I3eedd6

fix(gpt): fix RME GPT library bug

This patch fixes fill_l1_tbl() function bug
for RME_GPT_MAX_BLOCK build option set to 0
disabling filling L1 tables with Contiguous
descriptors.

Change-Id: I3eedd6c1bb55b7c207bb3630d1ab2fda8f72eb17
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs

Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the f

feat(xilinx): remove PM_IOCTL and PM_QUERY_DATA APIs

Today, the PM_IOCTL and PM_QUERY_DATA APIs are there to maintain
backward compatibility. Now, the usage of these APIs on the Linux
side and the firmware side is updated. Hence remove the deprecated
PM_IOCTL and PM_QUERY_DATA EEMI API from the TF-A to make TF-A pass
through.

Note: Only use the newer kernel to access the deprecated features in
this patch. Otherwise, the system may not function correctly.

Change-Id: I23effb7ff62e7f83563c2b422ea64a0289fd880f
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(nuvoton): fix MMU mapping settings

MAP_DEVICE0 for internal (register) space access settings
flag MT_NS was changed to MT_SECURE to enable access
to the TSGEN register, otherwise it brings to MC

fix(nuvoton): fix MMU mapping settings

MAP_DEVICE0 for internal (register) space access settings
flag MT_NS was changed to MT_SECURE to enable access
to the TSGEN register, otherwise it brings to MCR violation,
because access to the TSGEN register is locked and enabled
for secure only

Change-Id: Id2fe90d30342706c58064161360d8be6e0d5616b
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>

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refactor(fdts): remove unused nodes from CoT device tree

Since the CoT device tree is intended solely for BL2, remove the
nodes that are not handled by BL2.

Change-Id: I977eec902f16de59743e97d15148

refactor(fdts): remove unused nodes from CoT device tree

Since the CoT device tree is intended solely for BL2, remove the
nodes that are not handled by BL2.

Change-Id: I977eec902f16de59743e97d15148d63934b7b863
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common

refactor(juno): add explicit entry for HW_CONFIG in BL2 CoT file

Add an explicit entry for HW_CONFIG in the BL2 CoT file for the Juno
platform, as the HW_CONFIG node has been removed from the common CoT
file.

Change-Id: I8a1a22dd1023895cfc5730101fad20a80390ce17
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was

refactor(auth): remove HW_CONFIG reference from BL1 CoT file

Remove the 'HW_CONFIG' reference from the BL1 CoT file, as BL1
does not play any role in loading the hw_config image. This
reference was incorrectly added to the BL1 CoT file.

Change-Id: I9c1d9abce65844eaa1f41ab4f98d3c258ab7a8d2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lau

refactor(fvp): add CoT desc dtsi

Adding CoT descriptor dtsi file to streamline fvp_tb_fw_config DTB file.

Change-Id: I0bbaef764b100ed0e749ec5f0c78a366398b3519
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to

feat(arm): add COT_DESC_IN_DTB option for Dualroot

Add support for BL2 to get the Dualroot chain of trust description
through the Firmware Configuration Framework (FCONF). This makes it
possible to export the part of the Dualroot chain of trust enforced by
BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2 will parse
it when setting up the platform.

The feature can be enabled through the COT_DESC_IN_DTB=1 option. The
default behavior (COT_DESC_IN_DTB=0) remains to hard-code the Dualroot
CoT into BL2 images.

Change-Id: I3497b1daf14be09b5ce3a74d39df7551819255c2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format.

feat(fvp): add Dualroot CoT in DTB support

Adding support for Dualroot CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file in
DTB format. With this, the CoT description may be updated without
rebuilding BL2 image.

This feature can be enabled by building BL2 with COT_DESC_IN_DTB=1 and
COT=dualroot. The default behavior remains to embed the CoT description
into BL2 image.

Change-Id: I343931b145aa8a53b0a5d4b8aefb273ffb5a9163
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(dt-bindings): introduce Dualroot CoT DTB

Add Dualroot CoT DTB, which allows Dualroot platforms to get their chain
of trust description from a configuration file, rather than hard-coding
it into

feat(dt-bindings): introduce Dualroot CoT DTB

Add Dualroot CoT DTB, which allows Dualroot platforms to get their chain
of trust description from a configuration file, rather than hard-coding
it into the firmware source code itself.

Change-Id: I03af8f28ba7ad56b883ff5e7961500ffdb8c3957
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98a

feat(tc): bind SMMU-600 with the DPU on TC3 FPGA

The SMMU 600 is used on TC3 FPGA board with the display device, add the
device tree binding for it.

Change-Id: Iadf85873720ca47bbbda999aa7b18a9db98ae945
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): bind SMMU-700 with DPU on TC3

TC3 adds a new SMMU-700 specifically for the DPU. This is used as the
DPU SMMU instead of the existing SMMU used for the DPU. Update the
device tree to reflec

feat(tc): bind SMMU-700 with DPU on TC3

TC3 adds a new SMMU-700 specifically for the DPU. This is used as the
DPU SMMU instead of the existing SMMU used for the DPU. Update the
device tree to reflect this.

Change-Id: I865140f8f53bceaa8849f6583190b240eeee0539
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "feat(fvp): fdts: add stdout-path to the Foundation FVPs" into integration

refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Us

refactor(tc): append binding for SMMU-700

The usage for SMMU-700 is not consistent across TC platforms:

SMMU-700 on TC2:

| FVP | FPGA
--------+-------+------
Display | Used | Used
GPU | Used | Used

SMMU-700 on TC3:

| FVP | FPGA
--------+-------+------
Display | No | No
GPU | Used | No

This commit changes to use append mode for SMMU-700 to bind it on TC2
and TC3 separately. As a result, the TC_IOMMU_EN configuration is not
used, remove it.

Change-Id: Ic4152eb4c8ef97bf27b8a97c3c6cb86e32a2e8eb
Signed-off-by: Leo Yan <leo.yan@arm.com>

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build(romlib): don't timestamp generated wrappers

The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
genera

build(romlib): don't timestamp generated wrappers

The Makefile rule for the libwrappers object files places a dependency
on a timestamp file. This timestamp file is created by the recipe that
generates the libwrappers sources, and was presumably introduced to
indicate to Make that all of the source files are generated
simultaneously by that rule.

Instead, we can use a grouped target rule, which uses `&:` instead of
`:`. This communicates to Make that all of the targets listed are
generated at once.

To demonstrate, the following two Makefile rules differ in their
behaviour:

a.x b.x c.x: # targets may be updated independently
... # generate a.x, b.x and c.x

a.x b.x c.x &: # all targets are updated at once
... # generate a.x, b.x and c.x

While both recipes do generate all three files, only the second rule
communicates this fact to Make. As such, Make can reason that if one of
the files is up to date then all of them are, and avoid re-running the
rule for any generated file that it has not already run it for.

Change-Id: I10b49eb72b5276c7f9bd933900833b03a61cff2f
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build(romlib): de-duplicate ROMLib wrapper sources

The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
wi

build(romlib): de-duplicate ROMLib wrapper sources

The `romlib_generator.py` script may generate duplicate wrapper sources,
which is undesirable when using them to generate Makefile rules as Make
will warn about duplicated targets.

This change sorts the wrapper sources returned from this script, which
has the effect of also de-duplicating them.

Change-Id: I109607ef94f77113a48cc0d6e07877efd1971dbc
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(build): fix incorrectly-escaped armlink preprocessor definitions

Preprocessor definitions that are passed to armlink are currently not
correctly escaped, resulting in the shell trying to parse t

fix(build): fix incorrectly-escaped armlink preprocessor definitions

Preprocessor definitions that are passed to armlink are currently not
correctly escaped, resulting in the shell trying to parse the
parentheses contained in some of the preprocessor definitions:

```
LD build/tegra/t210/release/bl31/bl31.elf
/bin/sh: 1: Syntax error: "(" unexpected
```

This change ensures that these preprocessor definitions are adequately
escaped for the shell.

Change-Id: I9d2c60fa60c0aa00770417a68f900e9fb84b4669
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interfac

feat(tc): configure MCN rdalloc and wralloc mode

SLC WRALLOCMODE and RDALLOCMODE are configured by default to 0b01
(always alloc), configure both to mode 0b10 (use bus signal attribute
from interface).

Change-Id: Ic8cd3ee988dd0772cfb9b639dea0cc335ab70539
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf dr

feat(tc): add dts entries for MCN PMU nodes

TC3 has 4 MCN instances, each of them have PMU registers to count
different MCN cache access events, add entries for MCN PMU so that Linux
MCN PMU perf driver can be used with perf.

Change-Id: I7e0ac5025231c3f19d5291292d4cae186accc544
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux

feat(tc): enable MCN non-secure access to pmu counters on TC3

MCN PMU counters are by default non-accesible from non-secure world, so
enable the non-secure access to those PMU counters so that linux perf
driver can read them. FVP has a different address space size.

Change-Id: I2a3758faca5f7cab6d3146a1beb7b289eec0294d
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>

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Merge "docs(gpt): update GPT library documentation" into integration

docs(gpt): update GPT library documentation

This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
m

docs(gpt): update GPT library documentation

This patch updates GPT library design documentation
with the changes introduced by patches which add
support for large GPT mappings and configuration of
memory size protected by bitlock.

Change-Id: I1f97fa8f003deb07a5f32b7237c1927581a788c8
Signed-off-by: AlexeiFedorov <Alexei.Fedorov@arm.com>

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