1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright 2020-2021, 2023-2024 NXP 4 */ 5 #ifndef S32CC_CLK_REGS_H 6 #define S32CC_CLK_REGS_H 7 8 #include <lib/utils_def.h> 9 10 #define FXOSC_BASE_ADDR (0x40050000UL) 11 #define ARMPLL_BASE_ADDR (0x40038000UL) 12 13 /* FXOSC */ 14 #define FXOSC_CTRL(FXOSC) ((FXOSC) + 0x0UL) 15 #define FXOSC_CTRL_OSC_BYP BIT_32(31U) 16 #define FXOSC_CTRL_COMP_EN BIT_32(24U) 17 #define FXOSC_CTRL_EOCV_OFFSET 16U 18 #define FXOSC_CTRL_EOCV_MASK GENMASK_32(23U, FXOSC_CTRL_EOCV_OFFSET) 19 #define FXOSC_CTRL_EOCV(VAL) (FXOSC_CTRL_EOCV_MASK & \ 20 ((uint32_t)(VAL) << FXOSC_CTRL_EOCV_OFFSET)) 21 #define FXOSC_CTRL_GM_SEL_OFFSET 4U 22 #define FXOSC_CTRL_GM_SEL_MASK GENMASK_32(7U, FXOSC_CTRL_GM_SEL_OFFSET) 23 #define FXOSC_CTRL_GM_SEL(VAL) (FXOSC_CTRL_GM_SEL_MASK & \ 24 ((uint32_t)(VAL) << FXOSC_CTRL_GM_SEL_OFFSET)) 25 #define FXOSC_CTRL_OSCON BIT_32(0U) 26 27 #define FXOSC_STAT(FXOSC) ((FXOSC) + 0x4UL) 28 #define FXOSC_STAT_OSC_STAT BIT_32(31U) 29 30 /* PLL */ 31 #define PLLDIG_PLLCR(PLL) ((PLL) + 0x0UL) 32 #define PLLDIG_PLLCR_PLLPD BIT_32(31U) 33 34 #define PLLDIG_PLLSR(PLL) ((PLL) + 0x4UL) 35 #define PLLDIG_PLLSR_LOCK BIT_32(2U) 36 37 #define PLLDIG_PLLDV(PLL) ((PLL) + 0x8UL) 38 #define PLLDIG_PLLDV_RDIV_OFFSET 12U 39 #define PLLDIG_PLLDV_RDIV_MASK GENMASK_32(14U, PLLDIG_PLLDV_RDIV_OFFSET) 40 #define PLLDIG_PLLDV_RDIV_SET(VAL) (PLLDIG_PLLDV_RDIV_MASK & \ 41 ((VAL) << PLLDIG_PLLDV_RDIV_OFFSET)) 42 #define PLLDIG_PLLDV_MFI_MASK GENMASK_32(7U, 0U) 43 #define PLLDIG_PLLDV_MFI(DIV) (PLLDIG_PLLDV_MFI_MASK & (DIV)) 44 45 #define PLLDIG_PLLFD(PLL) ((PLL) + 0x10UL) 46 #define PLLDIG_PLLFD_SMDEN BIT_32(30U) 47 #define PLLDIG_PLLFD_MFN_MASK GENMASK_32(14U, 0U) 48 #define PLLDIG_PLLFD_MFN_SET(VAL) (PLLDIG_PLLFD_MFN_MASK & (VAL)) 49 50 #define PLLDIG_PLLCLKMUX(PLL) ((PLL) + 0x20UL) 51 52 #define PLLDIG_PLLODIV(PLL, N) ((PLL) + 0x80UL + ((N) * 0x4UL)) 53 #define PLLDIG_PLLODIV_DE BIT_32(31U) 54 #define PLLDIG_PLLODIV_DIV_OFFSET 16U 55 #define PLLDIG_PLLODIV_DIV_MASK GENMASK_32(23U, PLLDIG_PLLODIV_DIV_OFFSET) 56 #define PLLDIG_PLLODIV_DIV(VAL) (((VAL) & PLLDIG_PLLODIV_DIV_MASK) >> \ 57 PLLDIG_PLLODIV_DIV_OFFSET) 58 #define PLLDIG_PLLODIV_DIV_SET(VAL) (PLLDIG_PLLODIV_DIV_MASK & ((VAL) << \ 59 PLLDIG_PLLODIV_DIV_OFFSET)) 60 61 #endif /* S32CC_CLK_REGS_H */ 62