feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c689

feat(st-clock): add STM32MP2 clock driver

This driver manages the clocks on STM32MP2 platforms.
It uses a dedicated RCC (Reset and Clock Control) peripheral.

Change-Id: I6ba2173e73222269a2dfca4c6897229276a150c0
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

show more ...

Merge "fix(arm): string split into two lines causing error" into integration

fix(dt-bindings): update STM32MP2 clock and reset bindings

Fix some clocks and reset binding values.

Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.f

fix(dt-bindings): update STM32MP2 clock and reset bindings

Fix some clocks and reset binding values.

Change-Id: Ibe480aa77cd0abb63d08bbee08ad4ec9d5d2a397
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>

show more ...

feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479

feat(st-reset): add system reset management

Add the system reset management into the stm32mp
reset driver.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I748f10de2398e1323160f479f99e92abd2f65dca

show more ...

Merge changes from topic "utils_fixes" into integration

* changes:
refactor(lib): rename GENMASK parameters
fix(lib): avoid CWE-190 for GENMASK macros
fix(lib): fix MISRA 12.2 violations for B

Merge changes from topic "utils_fixes" into integration

* changes:
refactor(lib): rename GENMASK parameters
fix(lib): avoid CWE-190 for GENMASK macros
fix(lib): fix MISRA 12.2 violations for BIT32 and BIT64 macros
fix(intel): remove redundant BIT_32 macro

show more ...

fix(arm): string split into two lines causing error

Fix the code related error message when user provides RESET_TO_BL31=1 to
the make command but fails to provide "ARM_PRELOADED_DTB_BASE" macro at
t

fix(arm): string split into two lines causing error

Fix the code related error message when user provides RESET_TO_BL31=1 to
the make command but fails to provide "ARM_PRELOADED_DTB_BASE" macro at
the same command line. Remove the line break from the error string
causing the code error.

Additionally, make doesn't parse quote marks in strings, thus remove
quote marks within error strings in this file.

Change-Id: Ic131b6febebfb420ed588fe4fb0853cbdae0afb8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

show more ...

docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/hashtag:%22fvp_migration_11_26%22+(status:open%20OR%20status:merged)

Migrated FVP's to use version 11.26.11 an

docs(fvp): update FVP versions used

Patch series:
https://review.trustedfirmware.org/q/hashtag:%22fvp_migration_11_26%22+(status:open%20OR%20status:merged)

Migrated FVP's to use version 11.26.11 and 11.24.24, also removed
some model testing that are now no more available with newer model
configuration.

Change-Id: Ib93a7148270e2b6fb356a631dcc36061c7c8341c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

show more ...

Merge "refactor(cm): update SCTLR_EL2 initialisation" into integration

Merge "fix(gpt): fix GPT library fill_l1_tbl() function" into integration

Merge "refactor(qemu-sbsa): use fdt_read_uint32_default more" into integration

feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With EN

feat(zynqmp): enable ENABLE_LTO flag

Enabling Link Time Optimization in platform.mk for AMD-Xilinx
ZynqMP platform optimizes TF-A size.
With ENABLE_LTO=0, the release bl31.elf size is 86098.
With ENABLE_LTO=1, the release bl31.elf size reduces to 81866.
The size difference in OCM is 4232 bytes, saving up to 4KB.

Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I6d5001a9ac250e3a87b958e9b665962a917265d6

show more ...

refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by:

refactor(qemu-sbsa): use fdt_read_uint32_default more

We have fdt_read_uint32_default() function which allows us to use less
temporary variables. Let make use of it where applicable.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I6fc8a87d5aac427703fd3c8b689e153ed58fa8b7

show more ...

Merge "feat(qemu-sbsa): handle the information of CPU topology" into integration

Merge "fix(mbedtls): sign verification issue with invalid Key/Signature" into integration

refactor(lib): rename GENMASK parameters

Rename GENMASK parameters for better readability to avoid
misinterpreting the 'l' as '1' in BIT(l) usage.

Change-Id: I9a85c750607e098939d70c61c2e29f4788b990

refactor(lib): rename GENMASK parameters

Rename GENMASK parameters for better readability to avoid
misinterpreting the 'l' as '1' in BIT(l) usage.

Change-Id: I9a85c750607e098939d70c61c2e29f4788b99016
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

fix(lib): avoid CWE-190 for GENMASK macros

Redefine GENMASK_32 and GENMASK_64 to avoid the impact of CWE-190, which
applies due to (~0 << (l)) syntax, where a wraparound occurs.

Change-Id: I8d08911

fix(lib): avoid CWE-190 for GENMASK macros

Redefine GENMASK_32 and GENMASK_64 to avoid the impact of CWE-190, which
applies due to (~0 << (l)) syntax, where a wraparound occurs.

Change-Id: I8d08911664db7052351312d310566bb546dfb486
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

fix(lib): fix MISRA 12.2 violations for BIT32 and BIT64 macros

MISRA interprets all unsigned integer literals as UTLR, which has the
lowest rank required to represent a value. In this specific case,

fix(lib): fix MISRA 12.2 violations for BIT32 and BIT64 macros

MISRA interprets all unsigned integer literals as UTLR, which has the
lowest rank required to represent a value. In this specific case, the
value 1U was interpreted as an unsigned char. As a result, explicit
casts are necessary to avoid issues with MISRA 12.2.

Change-Id: I4c1231ffabb27442c6a48dabd96942574d27c719
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681e

fix(intel): remove redundant BIT_32 macro

BIT_32 macro is already defined as part of the utils_def.h and included
through mmc.h

Suggested-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I7921681ee9af7d65e8eab5a0bf1d5236ecfed1a4
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>

show more ...

feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting th

feat(qemu-sbsa): handle the information of CPU topology

We add the support for adding cpus/topology to device tree in sbsaQemu
platform, and we can get this information via SMC calls:

- counting the number of sockets
- counting the number of clusters in one socket
- counting the number of cores in one cluster
- counting the number of threads in one core

Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn>
Change-Id: I0059a5c7bb7055aba1aa5ec5bfd0ec78801874f8

show more ...

Merge changes from topic "fpga_update" into integration

* changes:
feat(fpga): enable new CPU features
feat(cpufeat): upgrade PMU to v8 (FEATURE_DETECTION)

feat(cm): context switch MDCR_EL3 register

Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).

With this approach, features enable/disable settings
rem

feat(cm): context switch MDCR_EL3 register

Currently MDCR_EL3 register value is same for all the
worlds(Non-secure, Secure, Realm and Root).

With this approach, features enable/disable settings
remain same across all the worlds. This is not ideal as
there must be flexibility in controlling feature as per
the requirements for individual world.

The patch addresses this by providing MDCR_EL3 a per world
value. Features with identical values for all the worlds are
grouped under ``manage_extensions_common`` API.

Change-Id: Ibc068d985fe165d8cb6d0ffb84119bffd743b3d1
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

show more ...

Merge "fix(versal): remove check for bl32 load address" into integration

Merge "fix(versal-net): remove check for bl32 load address" into integration

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl

fix(versal): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: I322b8d2fc1137297142704ea1087c185e16177cc
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...

fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address whe

fix(versal-net): remove check for bl32 load address

With PLM firmware version 2024.1 the bl32 load address is set
correctly in handoff parameters.
Hence the check to initialize bl32 load address when bl32
load address is indicated as 0 in handoff is removed.

Change-Id: Ie927787129816e79d43ba4803f6916e20d81458a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

show more ...